TWI844373B - Power supply device with low switching loss - Google Patents

Abstract

A power supply device with low switching loss includes a bridge rectifier, a first capacitor, a supply circuit, a transformer, a power switch element, a voltage divider circuit, an output stage circuit, a logic circuit, a switch circuit, and an MCU (Microcontroller Unit). The bridge rectifier generates a rectified voltage according to a first input voltage and a second input voltage. The supply circuit generates a supply voltage according to the rectified voltage. The transformer includes a main coil and a secondary coil. The voltage divider circuit is coupled to the main coil, and is configured to generate a divided voltage. The MCU is supplied by the supply voltage. The MCU controls the switch circuit according to a first logic voltage and a second logic voltage, such that the switch circuit selectively couples the main coil to the supply circuit.

Description

Low switching loss power supply

The present invention relates to a power supply, and more particularly to a power supply with low switching loss.

The power supply is an indispensable component in the field of laptop computers. However, if the switching loss of the power supply is too large, it is easy to cause the overall operating performance of the related laptop to decline. In view of this, it is necessary to propose a new solution to overcome the difficulties faced by the previous technology.

In a preferred embodiment, the present invention provides a power supply with low switching loss, comprising: a bridge rectifier, generating a rectified potential according to a first input potential and a second input potential; a first capacitor, storing the rectified potential; a supply circuit, generating a supply potential according to the rectified potential; a transformer, comprising a main coil and a secondary coil, wherein the main coil is used to receive the rectified potential, and the secondary coil is used to output an induced potential; a power switch, selectively coupling the main coil to a ground potential according to a clock potential; a voltage divider circuit , coupled to the main coil and generating a divided voltage potential; an output stage circuit, generating an output potential according to the induced potential; a microcontroller, generating the clock potential, wherein the microcontroller is powered by the supply potential; a logic circuit, generating a first logic potential and a second logic potential according to the clock potential, the divided voltage potential, and the output potential; and a switching circuit, wherein the microcontroller further controls the switching circuit according to the first logic potential and the second logic potential, so that the switching circuit selectively couples the main coil to the supply circuit.

In some embodiments, the bridge rectifier includes: a first diode having an anode and a cathode, wherein the anode of the first diode is coupled to a first input node to receive the first input potential, and the cathode of the first diode is coupled to a first node to output the rectified potential; a second diode having an anode and a cathode, wherein the anode of the second diode is coupled to a second input node to receive the second input potential, and the cathode of the second diode is coupled to the first node; a third diode having an anode and a cathode an anode of the third diode, wherein the anode of the third diode is coupled to the ground potential, and the cathode of the third diode is coupled to the first input node; and a fourth diode having an anode and a cathode, wherein the anode of the fourth diode is coupled to the ground potential, and the cathode of the fourth diode is coupled to the second input node; wherein the first capacitor has a first end and a second end, the first end of the first capacitor is coupled to the first node to receive and store the rectified potential, and the second end of the first capacitor is coupled to the ground potential.

In some embodiments, the supply circuit includes: a first resistor having a first end and a second end, wherein the first end of the first resistor is coupled to the first node to receive the rectified potential, and the second end of the first resistor is coupled to a second node; a fifth diode having an anode and a cathode, wherein the anode of the fifth diode is coupled to the second node, and the cathode of the fifth diode is coupled to a supply node to output the supply potential; a second resistor having a first end and a second end, wherein the first end of the second resistor is coupled to the supply node, and the second end of the second resistor is coupled to the ground potential; and a second capacitor having a first end and a second end, wherein the first end of the second capacitor is coupled to the supply node, and the second end of the second capacitor is coupled to the ground potential.

In some embodiments, the transformer further has a built-in excitation inductor, the main coil has a first end and a second end, the first end of the main coil is coupled to the first node to receive the rectified potential, the second end of the main coil is coupled to a third node, the excitation inductor has a first end and a second end, the first end of the excitation inductor is coupled to the first node, the second end of the excitation inductor is coupled to the third node, the secondary coil has a first end and a second end, the first end of the secondary coil is coupled to a fourth node to output the induced potential, and the second end of the secondary coil is coupled to a common node.

In some embodiments, the power switch includes: a first transistor having a control end, a first end, and a second end, wherein the control end of the first transistor is used to receive the clock potential, the first end of the first transistor is coupled to a fifth node, and the second end of the first transistor is coupled to the third node.

In some embodiments, the voltage divider circuit includes: a third resistor having a first end and a second end, wherein the first end of the third resistor is coupled to the fifth node, and the second end of the third resistor is coupled to the ground potential; a fourth resistor having a first end and a second end, wherein the first end of the fourth resistor is coupled to the third node, and the second end of the fourth resistor is coupled to a voltage divider node to output the voltage divider potential; and a fifth resistor having a first end and a second end, wherein the first end of the fifth resistor is coupled to the voltage divider node, and the second end of the fifth resistor is coupled to the ground potential.

In some embodiments, the output stage circuit includes: a sixth diode having an anode and a cathode, wherein the anode of the sixth diode is coupled to the fourth node to receive the induced potential, and the cathode of the sixth diode is coupled to an output node to output the output potential; and a third capacitor having a first end and a second end, wherein the first end of the third capacitor is coupled to the output node, and the second end of the third capacitor is coupled to the common node.

In some embodiments, the logic circuit includes: an inverter having an input terminal and an output terminal, wherein the input terminal of the inverter is used to receive the clock potential, and the output terminal of the inverter is used to output an inverted clock potential; a first AND gate having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the first AND gate is used to receive the inverted clock potential, and the second input terminal of the first AND gate is used to output an inverted clock potential. Two input terminals are used to receive the output potential, and the output terminal of the first AND gate is used to output the first logic potential; and a second AND gate has a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the second AND gate is used to receive the divided voltage, the second input terminal of the second AND gate is used to receive the output potential, and the output terminal of the second AND gate is used to output the second logic potential.

In some embodiments, the switching circuit includes: a second transistor having a control end, a first end, and a second end, wherein the control end of the second transistor is used to receive a first control potential, the first end of the second transistor is coupled to the supply node, and the second end of the second transistor is coupled to a sixth node; and a third transistor having a control end, a first end, and a second end, wherein the control end of the third transistor is used to receive a second control potential, the first end of the third transistor is coupled to the sixth node, and the second end of the third transistor is coupled to the third node.

In some embodiments, the microcontroller further generates the first control potential and the second control potential according to the first logic potential and the second logic potential, the first control potential has the same logic level as the first logic potential, and the second control potential has the same logic level as the second logic potential.

In order to make the purpose, features and advantages of the present invention more clearly understood, specific embodiments of the present invention are specifically listed below and described in detail with reference to the accompanying drawings.

Certain terms are used in the specification and patent application to refer to specific components. Those skilled in the art should understand that hardware manufacturers may use different terms to refer to the same component. This specification and patent application do not use differences in names as a way to distinguish components, but use differences in the functions of components as the criterion for distinction. The words "include" and "including" mentioned throughout the specification and patent application are open terms and should be interpreted as "including but not limited to". The word "substantially" means that within an acceptable error range, a person skilled in the art can solve the technical problem within a certain error range and achieve the basic technical effect. In addition, the word "coupled" in this specification includes any direct and indirect electrical connection means. Therefore, if a first device is described herein as being coupled to a second device, it means that the first device may be directly electrically connected to the second device, or may be indirectly electrically connected to the second device via other devices or connection means.

FIG. 1 is a schematic diagram showing a power supply 100 according to an embodiment of the present invention. For example, the power supply 100 can be applied to a desktop computer, a laptop computer, or an all-in-one computer. As shown in FIG. 1, the power supply 100 includes: a bridge rectifier 110, a first capacitor C1, a supply circuit 120, a transformer 130, a power switch 140, a voltage divider circuit 150, an output stage circuit 160, a logic circuit 170, a switching circuit 180, and a microcontroller unit (MCU) 190. It should be noted that, although not shown in FIG. 1, the power supply 100 may further include other components, such as: a voltage regulator or (and) a negative feedback circuit.

The bridge rectifier 110 can generate a rectified potential VR according to a first input potential VIN1 and a second input potential VIN2, wherein an AC voltage with any frequency and any amplitude can be formed between the first input potential VIN1 and the second input potential VIN2. For example, the frequency of the AC voltage can be about 50 Hz or 60 Hz, and the root mean square (RMS) value of the AC voltage can be between 90 V and 264 V, but is not limited thereto. The first capacitor C1 can be used to receive and store the rectified potential VR. The supply circuit 120 can generate a supply potential VP according to the rectified potential VR. The transformer 130 includes a main coil 131 and a secondary coil 132, wherein the main coil 131 may be located at one side of the transformer 130, and the secondary coil 132 may be located at the other side of the transformer 130. The main coil 131 may be used to receive the rectified potential VR, and in response to the rectified potential VR, the secondary coil 132 may be used to output an induced potential VS. The power switch 140 may selectively couple the main coil 131 to a ground potential VSS (e.g., 0V) according to a clock potential VA. For example, if the clock potential VA is a high logic level (i.e., logic "1"), the power switch 140 can couple the main coil 131 to the ground potential VSS (i.e., the power switch 140 can be similar to a short circuit path); conversely, if the clock potential VA is a low logic level (i.e., logic "0"), the power switch 140 will not couple the main coil 131 to the ground potential VSS (i.e., the power switch 140 can be similar to an open circuit path). The voltage divider circuit 150 is coupled to the main coil 131 and can be used to generate a voltage divider potential VD. The output stage circuit 160 can generate an output potential VOUT according to the sensed potential VS. For example, the output potential VOUT may be a DC potential, and its potential level may be between 18V and 20V, but is not limited thereto. The microcontroller 190 may be used to generate a clock potential VA, wherein the microcontroller 190 may be powered by the supply potential VP of the supply circuit 120. The logic circuit 170 may generate a first logic potential VL1 and a second logic potential VL2 according to the clock potential VA, the voltage division potential VD, and the output potential VOUT. In addition, the microcontroller 190 may further control the switching circuit 180 according to the first logic potential VL1 and the second logic potential VL2, so that the switching circuit 180 may selectively couple the main coil 131 to the supply circuit 120. That is, in response to different first logic potentials VL1 and second logic potentials VL2, the switching circuit 180 can be selected as a short circuit path or an open circuit path. According to actual measurement results, the design of the present invention helps the power switch 140 to perform a soft switching operation, so that the overall switching loss of the power supply 100 can be greatly reduced.

The following embodiments will introduce the detailed structure and operation of the power supply 100. It must be understood that these drawings and descriptions are only examples and are not intended to limit the scope of the present invention.

FIG. 2 is a circuit diagram of a power supply 200 according to an embodiment of the present invention. In the embodiment of FIG. 2, the power supply 200 has a first input node NIN1, a second input node NIN2, and an output node NOUT, and includes a bridge rectifier 210, a first capacitor C1, a supply circuit 220, a transformer 230, a power switch 240, a voltage divider circuit 250, an output stage circuit 260, a logic circuit 270, a switching circuit 280, and a microcontroller 290. The first input node NIN1 and the second input node NIN2 of the power supply 200 can receive a first input potential VIN1 and a second input potential VIN2 from an external input power source (not shown), respectively. The output node NOUT of the power supply 200 can be used to output an output potential VOUT to an electronic device (not shown).

The bridge rectifier 210 includes a first diode D1, a second diode D2, a third diode D3, and a fourth diode D4. The first diode D1 has an anode and a cathode, wherein the anode of the first diode D1 is coupled to the first input node NIN1, and the cathode of the first diode D1 is coupled to a first node N1 to output a rectified potential VR. The second diode D2 has an anode and a cathode, wherein the anode of the second diode D2 is coupled to the second input node NIN2, and the cathode of the second diode D2 is coupled to the first node N1. The third diode D3 has an anode and a cathode, wherein the anode of the third diode D3 is coupled to a ground potential VSS, and the cathode of the third diode D3 is coupled to the first input node NIN1. The fourth diode D4 has an anode and a cathode, wherein the anode of the fourth diode D4 is coupled to the ground potential VSS, and the cathode of the fourth diode D4 is coupled to the second input node NIN2.

The first capacitor C1 has a first terminal and a second terminal, wherein the first terminal of the first capacitor C1 is coupled to the first node N1 to receive and store the rectified potential VR, and the second terminal of the first capacitor C1 is coupled to the ground potential VSS.

The supply circuit 220 includes a fifth diode D5, a second capacitor C2, a first resistor R1, and a second resistor R2. The first resistor R1 has a first end and a second end, wherein the first end of the first resistor R1 is coupled to the first node N1 to receive the rectified potential VR, and the second end of the first resistor R1 is coupled to the second node N2. The fifth diode D5 has an anode and a cathode, wherein the anode of the fifth diode D5 is coupled to the second node N2, and the cathode of the fifth diode D5 is coupled to a supply node NP to output a supply potential VP. The second resistor R2 has a first end and a second end, wherein the first end of the second resistor R2 is coupled to the supply node NP, and the second end of the second resistor R2 is coupled to the ground potential VSS. The second capacitor C2 has a first terminal and a second terminal, wherein the first terminal of the second capacitor C2 is coupled to the supply node NP, and the second terminal of the second capacitor C2 is coupled to the ground potential VSS.

The transformer 230 includes a main coil 231 and a secondary coil 232, wherein the transformer 230 may further have a built-in excitation inductor LM. The excitation inductor LM may be an inherent component that is produced when the transformer 230 is manufactured, and it is not an external independent component. The main coil 231 and the excitation inductor LM may be located on the same side of the transformer 230 (e.g., the primary side), and the secondary coil 232 may be located on the other side of the transformer 230 (e.g., the secondary side, which may be isolated from the primary side). In detail, the main coil 231 has a first end and a second end, wherein the first end of the main coil 231 is coupled to the first node N1 to receive the rectified potential VR, and the second end of the main coil 231 is coupled to a third node N3. The magnetizing inductor LM has a first end and a second end, wherein the first end of the magnetizing inductor LM is coupled to the first node N1, and the second end of the magnetizing inductor LM is coupled to the third node N3. The secondary coil 232 has a first end and a second end, wherein the first end of the secondary coil 232 is coupled to a fourth node N4 to output an induced potential VS, and the second end of the secondary coil 232 is coupled to a common node NCM. For example, the common node NCM can be regarded as another ground potential, which can be the same as or different from the aforementioned ground potential VSS.

The power switch 240 includes a first transistor M1. For example, the first transistor M1 may be an N-type Metal-Oxide-Semiconductor Field-Effect Transistor (NMOSFET). The first transistor M1 has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain), wherein the control terminal of the first transistor M1 is used to receive a clock potential VA, the first terminal of the first transistor M1 is coupled to a fifth node N5, and the second terminal of the first transistor M1 is coupled to the third node N3. In some embodiments, a potential difference ΔV may be formed between the second terminal and the first terminal of the first transistor M1, which may also be regarded as the potential difference ΔV obtained by subtracting the potential at the fifth node N5 from the potential at the third node N3.

The voltage divider circuit 250 includes a third resistor R3, a fourth resistor R4, and a fifth resistor R5. The third resistor R3 has a first end and a second end, wherein the first end of the third resistor R3 is coupled to the fifth node N5, and the second end of the third resistor R3 is coupled to the ground potential VSS. It should be noted that the third resistor R3 has a very small resistance value (for example, less than or equal to 1 mΩ), so it can almost be regarded as a short circuit path. The fourth resistor R4 has a first end and a second end, wherein the first end of the fourth resistor R4 is coupled to the third node N3, and the second end of the fourth resistor R4 is coupled to a voltage divider node ND to output a voltage divider potential VD. The fifth resistor R5 has a first end and a second end, wherein the first end of the fifth resistor R5 is coupled to the voltage dividing node ND, and the second end of the fifth resistor R5 is coupled to the ground potential VSS.

The output stage circuit 260 includes a sixth diode D6 and a third capacitor C3. The sixth diode D6 has an anode and a cathode, wherein the anode of the sixth diode D6 is coupled to the fourth node N4 to receive the induced potential VS, and the cathode of the sixth diode D6 is coupled to the output node NOUT. The third capacitor C3 has a first end and a second end, wherein the first end of the third capacitor C3 is coupled to the output node NOUT, and the second end of the third capacitor C3 is coupled to the common node NCM. In some embodiments, an output current IOUT of the power supply 200 can flow through the sixth diode D6 and the third capacitor C3.

The logic circuit 270 includes an inverter 272, a first AND gate 274, and a second AND gate 276, and their connection methods and related functions are described as follows.

The inverter 272 has an input terminal and an output terminal, wherein the input terminal of the inverter 272 is used to receive the clock potential VA, and the output terminal of the inverter 272 is used to output an inverted clock potential VB. It should be understood that the inverted clock potential VB and the clock potential VA may have complementary logic levels.

The first AND gate 274 has a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the first AND gate 274 is used to receive the inverted clock potential VB, the second input terminal of the first AND gate 274 is used to receive the output potential VOUT, and the output terminal of the first AND gate 274 is used to output a first logic potential VL1. For example, if both the inverting clock potential VB and the output potential VOUT are high logic levels, the first AND gate 274 can output the first logic potential VL1 with a high logic level; conversely, if either the inverting clock potential VB or the output potential VOUT is a low logic level, the first AND gate 274 can output the first logic potential VL1 with a low logic level.

The second AND gate 276 has a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the second AND gate 276 is used to receive the divided voltage VD, the second input terminal of the second AND gate 276 is used to receive the output voltage VOUT, and the output terminal of the second AND gate 276 is used to output a second logic potential VL2. For example, if both the divided potential VD and the output potential VOUT are high logic levels, the second AND gate 276 can output the second logic potential VL2 with a high logic level; conversely, if either the divided potential VD or the output potential VOUT is a low logic level, the second AND gate 276 can output the second logic potential VL2 with a low logic level.

The switching circuit 280 includes a second transistor M2 and a third transistor M3, wherein the two can be coupled in series with each other. For example, the second transistor M2 and the third transistor M3 can each be an N-type metal oxide semi-conductor field effect transistor. The second transistor M2 has a control end (e.g., a gate), a first end (e.g., a source), and a second end (e.g., a drain), wherein the control end of the second transistor M2 is used to receive a first control potential VC1, the first end of the second transistor M2 is coupled to the supply node NP, and the second end of the second transistor M2 is coupled to a sixth node N6. The third transistor M3 has a control end (e.g., a gate), a first end (e.g., a source), and a second end (e.g., a drain), wherein the control end of the third transistor M3 is used to receive a second control potential VC2, the first end of the third transistor M3 is coupled to the sixth node N6, and the second end of the third transistor M3 is coupled to the third node N3.

The microcontroller 290 can generate a clock potential VA, wherein the microcontroller 290 can be powered by the supply potential VP of the supply circuit 220. For example, the clock potential VA can be maintained at a fixed potential when the power supply 200 is just initialized, and can provide a periodic clock waveform after the power supply 200 enters the normal use stage. In addition, the microcontroller 290 can generate the aforementioned first control potential VC1 and second control potential VC2 according to the first logic potential VL1 and the second logic potential VL2. For example, the first control potential VC1 can have the same logic level as the first logic potential VL1, and the second control potential VC2 can have the same logic level as the second logic potential VL2, but it is not limited thereto.

In some embodiments, the operating principle of the power supply 200 may be as described below. First, the bridge rectifier 110 may receive the first input potential VIN1 and the second input potential VIN2, and may generate a rectified potential VR. In response to the rectified potential VR, the fifth diode D5 of the supply circuit 220 may be turned on. At this time, in the supply circuit 220, the first resistor R1 and the second resistor R2 may jointly generate a supply potential VP, and the second capacitor C2 may perform voltage regulation and filtering operations on the supply potential VP. In some embodiments, the capacitance value of the second capacitor C2 may be as described in the following equation (1) to optimize its voltage regulation effect:

……………………………………(1) Wherein “C2” represents the capacitance value of the second capacitor C2, “PMAX” represents the maximum output power of the power supply 200, and “CF” represents a reference capacitance value, which may be approximately equal to 4.7 μF.

In response to the aforementioned supply potential VP, the microcontroller 290 will be activated to generate a clock potential VA. When the clock potential VA has a high logic level, the first transistor M1 will be enabled, and the power supply 200 can operate in a first mode. On the contrary, when the clock potential VA has a low logic level, the first transistor M1 will be disabled, and the power supply 200 can operate in a second mode. In other words, the power supply 200 can alternately operate in the aforementioned first mode and second mode.

In the first mode, the inverted clock potential VB is a low logic level, so the first logic potential VL1 of the first AND gate 274 will have a low logic level. Since the first transistor M1 is enabled, the potential difference ΔV of the first transistor M1 and the corresponding voltage-dividing potential VD are almost equal to 0, and the second logic potential VL2 of the second AND gate 276 will also have a low logic level. At this time, the microcontroller 290 will output the first control potential VC1 and the second control potential VC2 with a low logic level to simultaneously disable the second transistor M2 and the third transistor M3. That is, the switching circuit 280 can be equivalent to an open circuit path, and the transformer 230 is not coupled to the supply circuit 220.

In the second mode, both the inverted clock potential VB and the output potential VOUT are high logic levels, so the first logic potential VL1 of the first AND gate 274 will have a high logic level. Since the first transistor M1 is disabled, the voltage divider potential VD can be a high logic level, and the second logic potential VL2 of the second AND gate 276 will also have a high logic level. At this time, the microcontroller 290 will output the first control potential VC1 and the second control potential VC2 with a high logic level to enable the second transistor M2 and the third transistor M3 at the same time. That is, the switching circuit 280 can be equivalent to a short circuit path, and the transformer 230 is coupled to the supply circuit 220. It should be noted that if the main coil 231 of the transformer 230 is coupled to the supply circuit 220, the magnetizing inductor LM of the transformer 230 will resonate with the second resistor R2 and the second capacitor C2 of the supply circuit 220, which can also be called "RLC series resonance". In addition, the fifth diode D5 of the supply circuit 220 can be used to prevent the energy of the aforementioned RLC series resonance from causing negative effects on the first input node NIN1 and the second input node NIN2 of the power supply 200.

FIG. 3 shows a signal waveform diagram of the power supply 200 according to an embodiment of the present invention, wherein the horizontal axis represents time and the vertical axis represents potential level or current value. Please refer to FIG. 2 and FIG. 3 together to understand the operating principle of the power supply 200. According to the measurement results of FIG. 3, when the clock potential VA has a low logic level, the output current IOUT will resonate, and the potential difference ΔV of the first transistor M1 will gradually decrease to 0 due to the aforementioned RLC series resonance. Therefore, even if the clock potential VA switches from a low logic level back to a high logic level, the first transistor M1 can achieve a high-efficiency flexible switching operation (as shown in a first dotted frame 301).

FIG. 4 shows a signal waveform diagram according to a conventional power supply, wherein the horizontal axis represents time and the vertical axis represents potential level or current value. Under conventional design, when the pulse potential VA switches from a low logic level back to a high logic level, the potential difference ΔV of the first transistor M1 is still very large, which can be regarded as a rigid switching operation (as shown in a second dotted frame 302). It must be understood that such a rigid switching operation often causes a more serious switching loss in the conventional power supply.

The present invention proposes a novel power supply. According to actual measurement results, the power supply with the above design can significantly reduce the overall switching loss, so it is very suitable for application in various devices.

It is worth noting that the potential, current, resistance, inductance, capacitance, and other component parameters described above are not limiting conditions of the present invention. Designers can adjust these settings according to different needs. The power supply of the present invention is not limited to the states shown in Figures 1-3. The present invention may only include any one or more features of any one or more embodiments of Figures 1-3. In other words, not all of the features shown in the diagrams need to be implemented in the power supply of the present invention at the same time. Although the embodiments of the present invention use metal oxide semi-conductor field effect transistors as an example, the present invention is not limited to this. People in the technical field can use other types of transistors, such as junction field effect transistors, or fin field effect transistors, etc., without affecting the effects of the present invention.

Ordinal numbers in this specification and the scope of the patent application, such as "first", "second", "third", etc., have no sequential relationship with each other, and are only used to mark and distinguish two different components with the same name.

Although the present invention is disclosed as above with the preferred embodiments, it is not intended to limit the scope of the present invention. Anyone skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the attached patent application.

100,200: Power supply 110,210: Bridge rectifier 120,220: Supply circuit 130,230: Transformer 131,231: Main coil 132,232: Secondary coil 140,240: Power switch 150,250: Voltage divider circuit 160,260: Output stage circuit 170,270: Logic circuit 180,280: Switching circuit 190,290: Microcontroller 272: Inverter 274: First and gate 276: Second and gate 301: First dashed frame 302: Second dashed frame C1: First capacitor C2: Second capacitor C3: Third capacitor D1: First diode D2: Second diode D3: Third diode D4: Fourth diode D5: Fifth diode D6: Sixth diode IOUT: Output current M1: First transistor M2: Second transistor M3: Third transistor N1: First node N2: Second node N3: Third node N4: Fourth node N5: Fifth node N6: Sixth node NCM: Common node ND: Voltage divider node NIN1: First input node NIN2: Second input node NOUT: Output node NP: Supply node R1: First resistor R2: Second resistor R3: Third resistor R4: Fourth resistor R5: Fifth resistor VA: Clock potential VB: Inverting clock potential VC1: First control potential VC2: Second control potential VD: Voltage divider potential VIN1: First input potential VIN2: Second input potential VL1: First logic potential VL2: Second logic potential VOUT: Output potential VP: Supply potential VR: Rectification potential VS: Sense potential VSS: Ground potential ΔV: Potential difference

FIG. 1 is a schematic diagram showing a power supply according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing a power supply according to an embodiment of the present invention. FIG. 3 is a signal waveform diagram showing a power supply according to an embodiment of the present invention. FIG. 4 is a signal waveform diagram showing a conventional power supply.

100: Power supply

110: Bridge rectifier

120: Supply circuit

130: Transformer

131: Main coil

132: Secondary coil

140: Power switch

150: Voltage divider circuit

160: Output stage circuit

170:Logic circuit

180: Switching circuit

190: Microcontroller

C1: First capacitor

VA: pulse potential

VD: voltage divider potential

VIN1: first input potential

VIN2: Second input potential

VL1: first logic potential

VL2: Second logic potential

VOUT: output voltage

VP: Supply potential

VR: Rectification potential

VS: Induction potential

VSS: ground potential

Claims (10)

A low switching loss power supply comprises: A bridge rectifier, generating a rectified potential according to a first input potential and a second input potential; A first capacitor, storing the rectified potential; A supply circuit, generating a supply potential according to the rectified potential; A transformer, comprising a main coil and a secondary coil, wherein the main coil is used to receive the rectified potential, and the secondary coil is used to output an induced potential; A power switch, selectively coupling the main coil to a ground potential according to a pulse potential; A voltage divider circuit, coupled to the main coil and generating a voltage divider potential; An output stage circuit, generating an output potential according to the induced potential; A microcontroller generates the clock potential, wherein the microcontroller is powered by the supply potential; A logic circuit generates a first logic potential and a second logic potential according to the clock potential, the voltage division potential, and the output potential; and A switching circuit, wherein the microcontroller further controls the switching circuit according to the first logic potential and the second logic potential, so that the switching circuit selectively couples the main coil to the supply circuit. A power supply as claimed in claim 1, wherein the bridge rectifier comprises: a first diode having an anode and a cathode, wherein the anode of the first diode is coupled to a first input node to receive the first input potential, and the cathode of the first diode is coupled to a first node to output the rectified potential; a second diode having an anode and a cathode, wherein the anode of the second diode is coupled to a second input node to receive the second input potential, and the cathode of the second diode is coupled to the first node; A third diode having an anode and a cathode, wherein the anode of the third diode is coupled to the ground potential, and the cathode of the third diode is coupled to the first input node; and A fourth diode having an anode and a cathode, wherein the anode of the fourth diode is coupled to the ground potential, and the cathode of the fourth diode is coupled to the second input node; wherein the first capacitor has a first end and a second end, the first end of the first capacitor is coupled to the first node to receive and store the rectified potential, and the second end of the first capacitor is coupled to the ground potential. A power supply as claimed in claim 2, wherein the supply circuit comprises: a first resistor having a first end and a second end, wherein the first end of the first resistor is coupled to the first node to receive the rectified potential, and the second end of the first resistor is coupled to a second node; a fifth diode having an anode and a cathode, wherein the anode of the fifth diode is coupled to the second node, and the cathode of the fifth diode is coupled to a supply node to output the supply potential; a second resistor having a first end and a second end, wherein the first end of the second resistor is coupled to the supply node, and the second end of the second resistor is coupled to the ground potential; and A second capacitor having a first end and a second end, wherein the first end of the second capacitor is coupled to the supply node, and the second end of the second capacitor is coupled to the ground potential. A power supply as in claim 3, wherein the transformer further has a built-in excitation inductor, the main coil having a first end and a second end, the first end of the main coil being coupled to the first node to receive the rectified potential, the second end of the main coil being coupled to a third node, the excitation inductor having a first end and a second end, the first end of the excitation inductor being coupled to the first node, the second end of the excitation inductor being coupled to the third node, the secondary coil having a first end and a second end, the first end of the secondary coil being coupled to a fourth node to output the induced potential, and the second end of the secondary coil being coupled to a common node. A power supply as claimed in claim 4, wherein the power switch comprises: A first transistor having a control end, a first end, and a second end, wherein the control end of the first transistor is used to receive the clock potential, the first end of the first transistor is coupled to a fifth node, and the second end of the first transistor is coupled to the third node. A power supply as claimed in claim 5, wherein the voltage divider circuit comprises: a third resistor having a first end and a second end, wherein the first end of the third resistor is coupled to the fifth node, and the second end of the third resistor is coupled to the ground potential; a fourth resistor having a first end and a second end, wherein the first end of the fourth resistor is coupled to the third node, and the second end of the fourth resistor is coupled to a voltage divider node to output the voltage divider potential; and a fifth resistor having a first end and a second end, wherein the first end of the fifth resistor is coupled to the voltage divider node, and the second end of the fifth resistor is coupled to the ground potential. A power supply as claimed in claim 4, wherein the output stage circuit comprises: a sixth diode having an anode and a cathode, wherein the anode of the sixth diode is coupled to the fourth node to receive the induced potential, and the cathode of the sixth diode is coupled to an output node to output the output potential; and a third capacitor having a first end and a second end, wherein the first end of the third capacitor is coupled to the output node, and the second end of the third capacitor is coupled to the common node. A power supply as claimed in claim 1, wherein the logic circuit comprises: an inverter having an input terminal and an output terminal, wherein the input terminal of the inverter is used to receive the clock potential, and the output terminal of the inverter is used to output an inverted clock potential; a first AND gate having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the first AND gate is used to receive the inverted clock potential, the second input terminal of the first AND gate is used to receive the output potential, and the output terminal of the first AND gate is used to output the first logic potential; and A second AND gate has a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the second AND gate is used to receive the divided voltage, the second input terminal of the second AND gate is used to receive the output voltage, and the output terminal of the second AND gate is used to output the second logic voltage. A power supply as claimed in claim 4, wherein the switching circuit comprises: a second transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the second transistor is used to receive a first control potential, the first terminal of the second transistor is coupled to the supply node, and the second terminal of the second transistor is coupled to a sixth node; and a third transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the third transistor is used to receive a second control potential, the first terminal of the third transistor is coupled to the sixth node, and the second terminal of the third transistor is coupled to the third node. A power supply as claimed in claim 9, wherein the microcontroller further generates the first control potential and the second control potential based on the first logic potential and the second logic potential, the first control potential has the same logic level as the first logic potential, and the second control potential has the same logic level as the second logic potential.

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