TWI844324B - Boost converter with high conversion efficiency - Google Patents

Abstract

A boost converter with high conversion efficiency includes a bridge rectifier, a first inductor, a sense circuit, an MCU (Microcontroller Unit), a power switch element, an output stage circuit, and an auxiliary boost circuit. The bridge rectifier generates a rectified voltage according to a first input voltage and a second input voltage. The sense circuit generates an average voltage according to the rectified voltage. The output stage circuit is coupled to the first inductor. The auxiliary boost circuit is coupled to the output stage circuit. The MCU controls the power switch element and the auxiliary boost circuit according to the average voltage. If the average voltage is lower than or equal to a threshold voltage, an output voltage will be generated by the output stage circuit and the auxiliary boost circuit together. If the average voltage is higher than the threshold voltage, the output voltage will be mainly provided by the output stage circuit.

Description

High conversion efficiency boost converter

The present invention relates to a boost converter, and more particularly to a boost converter with high conversion efficiency.

The boost converter is an indispensable component in the field of laptop computers. However, if the conversion efficiency of the boost converter is insufficient, it is easy to cause the overall operating performance of the related laptop to decline. In view of this, it is necessary to propose a new solution to overcome the difficulties faced by the previous technology.

In a preferred embodiment, the present invention provides a boost converter with high conversion efficiency, comprising: a bridge rectifier, generating a rectified potential according to a first input potential and a second input potential; a first inductor, receiving the rectified potential; a sensing circuit, generating an average potential according to the rectified potential; a microcontroller, generating a first drive potential, a second drive potential, and a control potential according to the average potential; a power switch, selectively switching the first drive potential to the second drive potential; and a control circuit. A first inductor is coupled to a ground potential; an output stage circuit is coupled to the first inductor; and an auxiliary boost circuit is coupled to the output stage circuit, wherein the auxiliary boost circuit operates according to the second driving potential and the control potential; wherein if the average potential is less than or equal to a critical potential, the output stage circuit will generate an output potential together with the auxiliary boost circuit; wherein if the average potential is greater than the critical potential, the output potential will be mainly provided by the output stage circuit.

In some embodiments, the bridge rectifier includes: a first diode having an anode and a cathode, wherein the anode of the first diode is coupled to a first input node to receive the first input potential, and the cathode of the first diode is coupled to a first node to output the rectified potential; a second diode having an anode and a cathode, wherein the anode of the second diode is coupled to a second input node to receive the second input potential, and the cathode of the second diode is coupled to the first node; a third diode having an anode and a cathode. cathode, wherein the anode of the third diode is coupled to the ground potential, and the cathode of the third diode is coupled to the first input node; and a fourth diode having an anode and a cathode, wherein the anode of the fourth diode is coupled to the ground potential, and the cathode of the fourth diode is coupled to the second input node; wherein the first inductor has a first end and a second end, the first end of the first inductor is coupled to the first node to receive the rectified potential, and the second end of the first inductor is coupled to a second node.

In some embodiments, the sensing circuit includes: a first resistor having a first end and a second end, wherein the first end of the first resistor is used to receive the rectified potential, and the second end of the first resistor is coupled to a third node to output a divided potential; a second resistor having a first end and a second end, wherein the first end of the second resistor is coupled to the third node, and the second end of the second resistor is coupled to the ground potential; and an averaging circuit that calculates an average value of the divided potential to generate the average potential.

In some embodiments, the power switch includes: a first transistor having a control end, a first end, and a second end, wherein the control end of the first transistor is used to receive the first driving potential, the first end of the first transistor is coupled to the ground potential, and the second end of the first transistor is coupled to the second node.

In some embodiments, the output stage circuit includes: a fifth diode having an anode and a cathode, wherein the anode of the fifth diode is coupled to the second node and the cathode of the fifth diode is coupled to a fourth node; and a first capacitor having a first end and a second end, wherein the first end of the first capacitor is coupled to the fourth node and the second end of the first capacitor is coupled to the ground potential.

In some embodiments, the auxiliary boost circuit includes: a second inductor having a first end and a second end, wherein the first end of the second inductor is coupled to the fourth node, and the second end of the second inductor is coupled to a fifth node.

In some embodiments, the auxiliary boost circuit further includes: a second transistor having a control end, a first end, and a second end, wherein the control end of the second transistor is used to receive the second driving potential, the first end of the second transistor is coupled to the ground potential, and the second end of the second transistor is coupled to the fifth node.

In some embodiments, the auxiliary boost circuit further includes: a sixth diode having an anode and a cathode, wherein the anode of the sixth diode is coupled to the fifth node, and the cathode of the sixth diode is coupled to an output node to output the output potential; and a second capacitor having a first end and a second end, wherein the first end of the second capacitor is coupled to the output node, and the second end of the second capacitor is coupled to the ground potential.

In some embodiments, the auxiliary boost circuit further includes: a third transistor having a control end, a first end, and a second end, wherein the control end of the third transistor is used to receive the control potential, the first end of the third transistor is coupled to a sixth node, and the second end of the third transistor is coupled to the fourth node; and a third resistor having a first end and a second end, wherein the first end of the third resistor is coupled to the sixth node, and the second end of the third resistor is coupled to the output node.

In some embodiments, if the average potential is less than or equal to the critical potential or the duty cycle of the first driving potential has reached 70%, the first transistor and the second transistor will be driven with the same switching frequency, and the third transistor will be disabled; if the average potential is greater than the critical potential, only the first transistor will be driven, the second transistor will be disabled, and the third transistor will be enabled.

In order to make the purpose, features and advantages of the present invention more clearly understood, specific embodiments of the present invention are specifically listed below and described in detail with reference to the accompanying drawings.

Certain terms are used in the specification and patent application to refer to specific components. Those skilled in the art should understand that hardware manufacturers may use different terms to refer to the same component. This specification and patent application do not use differences in names as a way to distinguish components, but use differences in the functions of components as the criterion for distinction. The words "include" and "including" mentioned throughout the specification and patent application are open terms and should be interpreted as "including but not limited to". The word "substantially" means that within an acceptable error range, a person skilled in the art can solve the technical problem within a certain error range and achieve the basic technical effect. In addition, the word "coupled" in this specification includes any direct and indirect electrical connection means. Therefore, if a first device is described herein as being coupled to a second device, it means that the first device may be directly electrically connected to the second device, or may be indirectly electrically connected to the second device via other devices or connection means.

FIG. 1 is a schematic diagram of a boost converter 100 according to an embodiment of the present invention. For example, the boost converter 100 may be applied to a desktop computer, a laptop computer, or an all-in-one computer. As shown in FIG. 1 , the boost converter 100 includes: a bridge rectifier 110, a first inductor L1, a sensing circuit 120, a microcontroller unit (MCU) 130, a power switch 140, an output stage circuit 150, and an auxiliary boost circuit 160. It should be noted that, although not shown in FIG. 1 , the boost converter 100 may further include other components, such as: a voltage regulator or (and) a negative feedback circuit.

The bridge rectifier 110 can generate a rectified potential VR according to a first input potential VIN1 and a second input potential VIN2, wherein an AC voltage with any frequency and any amplitude can be formed between the first input potential VIN1 and the second input potential VIN2. For example, the frequency of the AC voltage can be about 50 Hz or 60 Hz, and the RMS value of the AC voltage can be about 90 V to 264 V, but is not limited thereto. The first inductor L1 can receive the rectified potential VR. The sensing circuit 120 can generate an average potential VA according to the rectified potential VR. The microcontroller 130 can generate a first driving potential VG1, a second driving potential VG2, and a control potential VC according to the average potential VA. The power switch 140 can selectively couple the first inductor L1 to a ground potential VSS (e.g., 0V) according to the first driving potential VG1. For example, if the first driving potential VG1 is a high logic level (i.e., logic "1"), the power switch 140 can couple the first inductor L1 to the ground potential VSS (i.e., the power switch 140 can be similar to a short circuit path); conversely, if the first driving potential VG1 is a low logic level (i.e., logic "0"), the power switch 140 will not couple the first inductor L1 to the ground potential VSS (i.e., the power switch 140 can be similar to an open circuit path). The output stage circuit 150 is coupled to the first inductor L1. The auxiliary boost circuit 160 is coupled to the output stage circuit 150, wherein the auxiliary boost circuit 160 can operate according to the second driving potential VG2 and the control potential VC. In detail, the microcontroller 130 can compare the average potential VA with a critical potential VTH, and then control the auxiliary boost circuit 160 according to the comparison result. If the average potential VA is less than or equal to the critical potential VTH, the output stage circuit 150 and the auxiliary boost circuit 160 will jointly generate an output potential VOUT. For example, the output potential VOUT can be a DC potential, and its potential level can be between 360V and 440V, but it is not limited thereto. On the other hand, if the average potential VA is greater than the critical potential VTH, the output potential VOUT will be mainly provided by the output stage circuit 150, and the auxiliary boost circuit 160 will hardly participate in the generation of the output potential VOUT. According to actual measurement results, the design proposed by the present invention will help to significantly improve the conversion efficiency of the boost converter 100.

The following embodiments will introduce the detailed structure and operation of the boost converter 100. It must be understood that these drawings and descriptions are only examples and are not intended to limit the scope of the present invention.

FIG. 2 is a circuit diagram of a boost converter 200 according to an embodiment of the present invention. In the embodiment of FIG. 2, the boost converter 200 has a first input node NIN1, a second input node NIN2, and an output node NOUT, and includes a bridge rectifier 210, a first inductor L1, a sensing circuit 220, a microcontroller 230, a power switch 240, an output stage circuit 250, and an auxiliary boost circuit 260. The first input node NIN1 and the second input node NIN2 of the boost converter 200 can receive a first input potential VIN1 and a second input potential VIN2 from an external input power source (not shown), respectively. The output node NOUT of the boost converter 200 can be used to output an output potential VOUT to an electronic device (not shown).

The bridge rectifier 210 includes a first diode D1, a second diode D2, a third diode D3, and a fourth diode D4. The first diode D1 has an anode and a cathode, wherein the anode of the first diode D1 is coupled to the first input node NIN1, and the cathode of the first diode D1 is coupled to a first node N1 to output a rectified potential VR. The second diode D2 has an anode and a cathode, wherein the anode of the second diode D2 is coupled to the second input node NIN2, and the cathode of the second diode D2 is coupled to the first node N1. The third diode D3 has an anode and a cathode, wherein the anode of the third diode D3 is coupled to a ground potential VSS, and the cathode of the third diode D3 is coupled to the first input node NIN1. The fourth diode D4 has an anode and a cathode, wherein the anode of the fourth diode D4 is coupled to the ground potential VSS, and the cathode of the fourth diode D4 is coupled to the second input node NIN2.

The first inductor L1 has a first end and a second end, wherein the first end of the first inductor L1 is coupled to the first node N1 to receive the rectified potential VR, and the second end of the first inductor L1 is coupled to a second node N2.

The sensing circuit 220 includes an averaging circuit 225, a first resistor R1, and a second resistor R2. The first resistor R1 has a first end and a second end, wherein the first end of the first resistor R1 is used to receive the rectified potential VR, and the second end of the first resistor R1 is coupled to a third node N3 to output a divided potential VD. The second resistor R2 has a first end and a second end, wherein the first end of the second resistor R2 is coupled to the third node N3, and the second end of the second resistor R2 is coupled to the ground potential VSS. The averaging circuit 225 can calculate an average value of the divided potential VD within a given period of time to generate an average potential VA.

The microcontroller 230 can compare the average potential VA with a critical potential VTH, and then generate a first driving potential VG1, a second driving potential VG2, and a control potential VC according to the comparison result, which will be described in detail in the following embodiments. For example, the critical potential VTH can be a fixed 5V potential, but is not limited to this. In some embodiments, the microcontroller 230 can be a pulse width modulation (PWM) integrated circuit (IC), and the first driving potential VG1 and the second driving potential VG2 can each be a pulse width modulation potential.

The power switch 240 includes a first transistor M1. For example, the first transistor M1 may be an N-type Metal-Oxide-Semiconductor Field-Effect Transistor (NMOSFET). The first transistor M1 has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain), wherein the control terminal of the first transistor M1 is used to receive the first driving potential VG1, the first terminal of the first transistor M1 is coupled to the ground potential VSS, and the second terminal of the first transistor M1 is coupled to the second node N2.

The output stage circuit 250 includes a fifth diode D5 and a first capacitor C1. The fifth diode D5 has an anode and a cathode, wherein the anode of the fifth diode D5 is coupled to the second node N2, and the cathode of the fifth diode D5 is coupled to a fourth node N4. The first capacitor C1 has a first terminal and a second terminal, wherein the first terminal of the first capacitor C1 is coupled to the fourth node N4, and the second terminal of the first capacitor C1 is coupled to the ground potential VSS.

The auxiliary boost circuit 260 includes a second transistor M2, a third transistor M3, a sixth diode D6, a second inductor L2, a second capacitor C2, and a third resistor R3. For example, the second transistor M2 and the third transistor M3 may each be an N-type metal oxide semi-conductor field effect transistor.

The second inductor L2 has a first end and a second end, wherein the first end of the second inductor L2 is coupled to the fourth node N4, and the second end of the second inductor L2 is coupled to a fifth node N5.

The second transistor M2 has a control end (e.g., a gate), a first end (e.g., a source), and a second end (e.g., a drain), wherein the control end of the second transistor M2 is used to receive the second driving potential VG2, the first end of the second transistor M2 is coupled to the ground potential VSS, and the second end of the second transistor M2 is coupled to the fifth node N5.

The sixth diode D6 has an anode and a cathode, wherein the anode of the sixth diode D6 is coupled to the fifth node N5, and the cathode of the sixth diode D6 is coupled to the output node NOUT. The second capacitor C2 has a first terminal and a second terminal, wherein the first terminal of the second capacitor C2 is coupled to the output node NOUT, and the second terminal of the second capacitor C2 is coupled to the ground potential VSS.

The third transistor M3 has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain), wherein the control terminal of the third transistor M3 is used to receive the control potential VC, the first terminal of the third transistor M3 is coupled to a sixth node N6, and the second terminal of the third transistor M3 is coupled to the fourth node N4. The third resistor R3 has a first terminal and a second terminal, wherein the first terminal of the third resistor R3 is coupled to the sixth node N6, and the second terminal of the third resistor R3 is coupled to the output node NOUT.

FIG. 3 is a waveform diagram showing the first driving potential VG1 according to an embodiment of the present invention, wherein the horizontal axis represents time and the vertical axis represents potential level. As shown in FIG. 3, each operation cycle TT of the first driving potential VG1 includes a high logic interval TN and a low logic interval TF. It should be noted that the duty cycle of the first driving potential VG1 can be described as follows:

……………………………………………(1) Wherein "D" represents the duty cycle of the first driving potential VG1, "TT" represents the duration of the operating cycle TT, and "TN" represents the duration of the high logic interval TN.

In some embodiments, the boost converter 200 can selectively operate in either a single-stage boost mode or a double-stage boost mode, and the operating principles thereof can be described as follows.

FIG. 4 is a waveform diagram showing the rectified potential VR and the average potential VA according to an embodiment of the present invention, wherein the horizontal axis represents time and the vertical axis represents potential level. In the embodiment of FIG. 4, the microcontroller 230 determines that the average potential VA is greater than the critical potential VTH, so the boost converter 200 will operate in a single-stage boost mode. At this time, the microcontroller 230 can output a first drive potential VG1 with a switching frequency FS (e.g., 65kHz) to drive the first transistor M1, and can output a control potential VC with a high logic level to enable the third transistor M3. In addition, the microcontroller 230 may not output any second driving potential VG2, or maintain the second driving potential VG2 at a low logic level, so that the second transistor M2 is disabled. In the single-stage boost mode, the output potential VOUT of the boost converter 200 will be mainly provided by the output stage circuit 250, and the conversion ratio of the boost converter 200 can be described as follows:

…………………………………… (2) Wherein “G1” represents the conversion ratio of the boost converter 200 in the single-stage boost mode, “VOUT” represents the average level of the output potential VOUT, “VRA” represents the average level of the rectified potential VR, and “D” represents the duty cycle of the first driving potential VG1.

FIG. 5 is a waveform diagram showing the rectified potential VR and the average potential VA according to another embodiment of the present invention, wherein the horizontal axis represents time and the vertical axis represents potential level. In the embodiment of FIG. 5, the microcontroller 230 determines that the average potential VA is less than or equal to the critical potential VTH, so the boost converter 200 will operate in a double-stage boost mode. At this time, the microcontroller 230 can output a first drive potential VG1 and a second drive potential VG2 with the same switching frequency FS (e.g., 65kHz) to drive the first transistor M1 and the second transistor M2 at the same time. In addition, the microcontroller 230 may not output any control potential VC, or keep the control potential VC at a low logic level so that the third transistor M3 is disabled. In the dual-stage boost mode, the output voltage VOUT of the boost converter 200 is provided by both the output stage circuit 250 and the auxiliary boost circuit 260, and the conversion ratio of the boost converter 200 can be expressed as follows:

………………………………… (3) Wherein “G2” represents the conversion ratio of the boost converter 200 in the dual-stage boost mode, “VOUT” represents the average level of the output potential VOUT, “VRA” represents the average level of the rectified potential VR, and “D” represents the duty cycle of each of the first drive potential VG1 and the second drive potential VG2.

According to equations (2) and (3), if the required conversion ratio is the same, the dual-stage boost mode can use a smaller duty cycle than the single-stage boost mode. For example, assuming the required conversion ratio is 4, the single-stage boost mode must use a 75% duty cycle to achieve it, but the dual-stage boost mode can achieve it using only a 50% duty cycle. It must be understood that an excessively large duty cycle will result in higher transmission losses and lower conversion efficiency. Since the design of the present invention can automatically switch to the dual-stage boost mode when the rectified potential VR is relatively low, the overall conversion efficiency of the boost converter 200 can be greatly improved.

In other embodiments, if the microcontroller 230 detects that the duty cycle of the first driving potential VG1 has reached 70%, it may also force the boost converter 200 to switch from the single-stage boost mode to the double-stage boost mode, so that the transmission loss of the power switch 240 can be effectively reduced.

The present invention proposes a novel boost converter. According to actual measurement results, the boost converter designed as above can effectively improve the overall conversion efficiency, so it is very suitable for application in various devices.

It is worth noting that the potential, current, resistance, inductance, capacitance, and other component parameters described above are not limiting conditions of the present invention. Designers can adjust these settings according to different needs. The boost converter of the present invention is not limited to the states shown in Figures 1-5. The present invention may include only one or more features of any one or more embodiments of Figures 1-5. In other words, not all of the features shown in the diagrams need to be implemented in the boost converter of the present invention at the same time. Although the embodiments of the present invention use metal oxide semi-conductor field effect transistors as an example, the present invention is not limited thereto. Those skilled in the art may use other types of transistors, such as junction field effect transistors or fin field effect transistors, without affecting the effects of the present invention.

Ordinal numbers in this specification and the scope of the patent application, such as "first", "second", "third", etc., have no sequential relationship with each other, and are only used to mark and distinguish two different components with the same name.

Although the present invention is disclosed as above with the preferred embodiments, it is not intended to limit the scope of the present invention. Anyone skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the attached patent application.

100,200:Boost Converter

110,210: Bridge rectifier

120,220: Sensing circuit

130,230:Microcontroller

140,240: Power switch

150,250: Output stage circuit

160,260: Auxiliary boost circuit

225: Average circuit

C1: First capacitor

C2: Second capacitor

D1: The first diode

D2: Second diode

D3: The third diode

D4: The fourth second pole

D5: The fifth diode

D6: The sixth diode

FS: Switching frequency

L1: First inductor

L2: Second inductor

M1: First transistor

M2: Second transistor

M3: The third transistor

N1: First node

N2: Second node

N3: The third node

N4: The fourth node

N5: The fifth node

N6: Node 6

NIN1: First input node

NIN2: Second input node

NOUT: Output node

R1: The first resistor

R2: Second resistor

R3: The third resistor

VA: Average potential

VC: Control potential

VD: voltage divider

VG1: First driving potential

VG2: Second driving potential

VIN1: First input potential

VIN2: Second input potential

VOUT: output voltage

VR: Rectification potential

VSS: Ground potential

VTH: critical potential

TT: Operation period

TF: Low Logic Range

TN: High Logical Interval

FIG. 1 is a schematic diagram of a boost converter according to an embodiment of the present invention. FIG. 2 is a circuit diagram of a boost converter according to an embodiment of the present invention. FIG. 3 is a waveform diagram of a first drive potential according to an embodiment of the present invention. FIG. 4 is a waveform diagram of a rectified potential and an average potential according to an embodiment of the present invention. FIG. 5 is a waveform diagram of a rectified potential and an average potential according to another embodiment of the present invention.

100:Boost converter

110: Bridge rectifier

120: Sensing circuit

130: Microcontroller

140: Power switch

150: Output stage circuit

160: Auxiliary boost circuit

L1: First inductor

VA: Average potential

VC: control potential

VG1: first driving potential

VG2: Second driving potential

VIN1: first input potential

VIN2: Second input potential

VOUT: output voltage

VR: Rectification potential

VSS: ground potential

VTH: critical potential

Claims (10)

A boost converter with high conversion efficiency includes: a bridge rectifier, generating a rectified potential according to a first input potential and a second input potential; a first inductor, receiving the rectified potential; a sensing circuit, generating an average potential according to the rectified potential; a microcontroller, generating a first driving potential, a second driving potential, and a control potential according to the average potential; a power switch, selectively coupling the first inductor to the control circuit according to the first driving potential; to a ground potential; an output stage circuit coupled to the first inductor; and an auxiliary boost circuit coupled to the output stage circuit, wherein the auxiliary boost circuit operates according to the second driving potential and the control potential; wherein if the average potential is less than or equal to a critical potential, the output stage circuit will generate an output potential together with the auxiliary boost circuit; wherein if the average potential is greater than the critical potential, the output potential will be mainly provided by the output stage circuit. A boost converter as claimed in claim 1, wherein the bridge rectifier comprises: a first diode having an anode and a cathode, wherein the anode of the first diode is coupled to a first input node to receive the first input potential, and the cathode of the first diode is coupled to a first node to output the rectified potential; a second diode having an anode and a cathode, wherein the anode of the second diode is coupled to a second input node to receive the second input potential, and the cathode of the second diode is coupled to the first node; a third diode having an anode an anode and a cathode, wherein the anode of the third diode is coupled to the ground potential, and the cathode of the third diode is coupled to the first input node; and a fourth diode having an anode and a cathode, wherein the anode of the fourth diode is coupled to the ground potential, and the cathode of the fourth diode is coupled to the second input node; wherein the first inductor has a first end and a second end, the first end of the first inductor is coupled to the first node to receive the rectified potential, and the second end of the first inductor is coupled to a second node. A boost converter as claimed in claim 2, wherein the sensing circuit comprises: a first resistor having a first end and a second end, wherein the first end of the first resistor is used to receive the rectified potential, and the second end of the first resistor is coupled to a third node to output a divided potential; a second resistor having a first end and a second end, wherein the first end of the second resistor is coupled to the third node, and the second end of the second resistor is coupled to the ground potential; and an averaging circuit, calculating an average value of the divided potential to generate the average potential. A boost converter as claimed in claim 2, wherein the power switch comprises: A first transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the first transistor is used to receive the first driving potential, the first terminal of the first transistor is coupled to the ground potential, and the second terminal of the first transistor is coupled to the second node. A boost converter as claimed in claim 4, wherein the output stage circuit comprises: a fifth diode having an anode and a cathode, wherein the anode of the fifth diode is coupled to the second node, and the cathode of the fifth diode is coupled to a fourth node; and a first capacitor having a first end and a second end, wherein the first end of the first capacitor is coupled to the fourth node, and the second end of the first capacitor is coupled to the ground potential. A boost converter as claimed in claim 5, wherein the auxiliary boost circuit comprises: a second inductor having a first end and a second end, wherein the first end of the second inductor is coupled to the fourth node, and the second end of the second inductor is coupled to a fifth node. The boost converter of claim 6, wherein the auxiliary boost circuit further comprises: a second transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the second transistor is used to receive the second driving potential, the first terminal of the second transistor is coupled to the ground potential, and the second terminal of the second transistor is coupled to the fifth node. The boost converter of claim 7, wherein the auxiliary boost circuit further comprises: a sixth diode having an anode and a cathode, wherein the anode of the sixth diode is coupled to the fifth node, and the cathode of the sixth diode is coupled to an output node to output the output potential; and a second capacitor having a first end and a second end, wherein the first end of the second capacitor is coupled to the output node, and the second end of the second capacitor is coupled to the ground potential. A boost converter as claimed in claim 8, wherein the auxiliary boost circuit further comprises: a third transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the third transistor is used to receive the control potential, the first terminal of the third transistor is coupled to a sixth node, and the second terminal of the third transistor is coupled to the fourth node; and a third resistor having a first terminal and a second terminal, wherein the first terminal of the third resistor is coupled to the sixth node, and the second terminal of the third resistor is coupled to the output node. A boost converter as claimed in claim 9, wherein: if the average potential is less than or equal to the critical potential or the duty cycle of the first driving potential has reached 70%, the first transistor and the second transistor will be driven by the same switching frequency, and the third transistor will be disabled; If the average potential is greater than the critical potential, only the first transistor will be driven, the second transistor will be disabled, and the third transistor will be enabled.

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