TWI857781B - Power supply device with high conversion efficiency - Google Patents

Abstract

A power supply device with high conversion efficiency includes a switch circuit, a transformer, a first capacitor, an output stage circuit, a synchronous rectifier circuit, and a detection and control circuit. The first capacitor provides a capacitive voltage. The output stage circuit generates an output voltage according to a first control voltage and a second control voltage. The synchronous rectifier circuit generates the first control voltage and the second control volage with a dead zone time. The detection and control circuit is coupled to the synchronous rectifier circuit. The detection and control circuit can monitor the dead zone time. If the dead zone time is between a first threshold and a second threshold, the detection and control circuit can control the synchronous rectifier circuit according to the capacitive voltage, so as to update and increase the aforementioned dead zone time.

Description

High conversion efficiency power supply

The present invention relates to a power supply, and in particular to a power supply with high conversion efficiency.

The power supply is an indispensable component in the field of laptop computers. However, if the conversion efficiency of the power supply is insufficient, it is easy to cause the overall operating performance of the related laptop to decline. In view of this, it is necessary to propose a new solution to overcome the difficulties faced by the previous technology.

In a preferred embodiment, the present invention provides a power supply with high conversion efficiency, including: a switching circuit, which generates a switching potential according to an input potential, a first driving potential, and a second driving potential; a transformer, including a main coil, a first sub-coil, and a second sub-coil, wherein the transformer has a built-in leakage inductor and an excitation inductor, and the main coil receives the switching potential through the leakage inductor; a first capacitor, coupled to the excitation inductor, and provides a capacitance potential; an output stage circuit, coupled to the first sub-coil and the second sub-coil, wherein The output stage circuit generates an output potential according to a first control potential and a second control potential; a synchronous rectification circuit generates the first control potential and the second control potential with a dead time; and a detection and control circuit is coupled to the synchronous rectification circuit and generates the first drive potential and the second drive potential; wherein the detection and control circuit further monitors the dead time, and if the dead time is between a first critical value and a second critical value, the detection and control circuit controls the synchronous rectification circuit according to the capacitor potential to update and increase the dead time.

In some embodiments, the switching circuit includes: a first transistor having a control end, a first end, and a second end, wherein the control end of the first transistor is used to receive the first driving potential, the first end of the first transistor is coupled to a first node to output the switching potential, and the second end of the first transistor is coupled to an input node to receive the input potential; and a second transistor having a control end, a first end, and a second end, wherein the control end of the second transistor is used to receive the second driving potential, the first end of the second transistor is coupled to a ground potential, and the second end of the second transistor is coupled to the first node.

In some embodiments, the leakage inductor has a first end and a second end, the first end of the leakage inductor is coupled to the first node to receive the switching potential, the second end of the leakage inductor is coupled to a second node, the main coil has a first end and a second end, the first end of the main coil is coupled to the second node, the second end of the main coil is coupled to a third node, the excitation inductor has a first end and a second end, the first end of the excitation inductor is coupled to the second node, the second end of the excitation inductor is coupled to the third node, and the The first capacitor has a first end and a second end, the first end of the first capacitor is coupled to the third node to output the capacitance potential, the second end of the first capacitor is coupled to the ground potential, the first sub-coil has a first end and a second end, the first end of the first sub-coil is coupled to a fourth node, the second end of the first sub-coil is coupled to a common node, the second sub-coil has a first end and a second end, the first end of the second sub-coil is coupled to the common node, and the second end of the second sub-coil is coupled to a fifth node.

In some embodiments, the output stage circuit includes: a third transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the third transistor is used to receive the first control potential, the first terminal of the third transistor is coupled to an output node to output the output potential, and the second terminal of the third transistor is coupled to the fourth node; a fourth transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the fourth transistor is used to receive the second control potential, the first terminal of the fourth transistor is coupled to the output node, and the second terminal of the fourth transistor is coupled to the fifth node; and a second capacitor having a first terminal and a second terminal, wherein the first terminal of the second capacitor is coupled to the output node, and the second terminal of the second capacitor is coupled to the common node.

In some embodiments, the first threshold value is approximately equal to 60 ns, and the second threshold value is approximately equal to 300 ns.

In some embodiments, the detection and control circuit includes: an averaging circuit that averages the capacitor potential to generate an average potential.

In some embodiments, the detection and control circuit further includes: a divider that divides the average potential by a reference potential to generate a gain multiplier, wherein the divider is powered by a supply potential.

In some embodiments, the detection and control circuit further includes: a microcontroller, monitoring the dead time and generating the first drive potential, the second drive potential, and the reference potential, wherein if the dead time is between the first critical value and the second critical value, the microcontroller outputs the supply potential with a high logic level and further receives the gain multiplier from the divider.

In some embodiments, if the dead time is between the first critical value and the second critical value, the microcontroller further controls the synchronous rectification circuit to update the dead time by multiplying the dead time by the gain multiplier.

In some embodiments, if the dead time is less than the first threshold value, the microcontroller will send a notification level to a system end and force the power supply to enter a latching protection mode after a delay time.

In order to make the purpose, features and advantages of the present invention more clearly understood, specific embodiments of the present invention are specifically listed below and described in detail with reference to the accompanying drawings.

Certain terms are used in the specification and patent application to refer to specific components. Those skilled in the art should understand that hardware manufacturers may use different terms to refer to the same component. This specification and patent application do not use differences in names as a way to distinguish components, but use differences in the functions of components as the criterion for distinction. The words "include" and "including" mentioned throughout the specification and patent application are open terms and should be interpreted as "including but not limited to". The word "substantially" means that within an acceptable error range, those skilled in the art can solve the technical problem within a certain error range and achieve the basic technical effect. In addition, the word "coupled" in this specification includes any direct and indirect electrical connection means. Therefore, if a first device is described herein as being coupled to a second device, it means that the first device may be directly electrically connected to the second device, or may be indirectly electrically connected to the second device via other devices or connection means.

FIG. 1 is a schematic diagram showing a power supply 100 according to an embodiment of the present invention. For example, the power supply 100 can be applied to a desktop computer, a laptop computer, or an all-in-one computer. As shown in FIG. 1, the power supply 100 includes: a switching circuit 110, a transformer 120, a first capacitor C1, an output stage circuit 130, a synchronous rectification circuit 140, and a detection and control circuit 150. It should be noted that, although not shown in FIG. 1, the power supply 100 may further include other components, such as: a voltage regulator or (and) a negative feedback circuit.

The switching circuit 110 can generate a switching potential VW according to an input potential VIN, a first drive potential VG1, and a second drive potential VG2. For example, the input potential VIN can be a DC potential, and its potential level can be between 360V and 440V, but it is not limited to this. The transformer 120 includes a main coil 121, a first sub-coil 122, and a second sub-coil 123. The transformer 120 can further have a built-in leakage inductor LR and an excitation inductor LM, wherein the leakage inductor LR, the excitation inductor LM, and the main coil 121 can all be located on the same side of the transformer 120, and the first sub-coil 122 and the second sub-coil 123 can all be located on the opposite side of the transformer 120. The main coil 121 can receive the switching potential VW via the leakage inductor LR, and the first sub-coil 122 and the second sub-coil 123 can operate in response to the switching potential VW. The first capacitor C1 is coupled to the excitation inductor LM, wherein the first capacitor C1 can provide a capacitance potential VP. In some embodiments, the leakage inductor LR, the excitation inductor LM, and the first capacitor C1 can together form a resonant tank (Resonant Tank) of the power supply 100. The output stage circuit 130 is coupled to the first sub-coil 122 and the second sub-coil 123, wherein the output stage circuit 130 can generate an output potential VOUT according to a first control potential VC1 and a second control potential VC2. For example, the output potential VOUT can be another DC potential, and its potential level can be between 18V and 20V, but it is not limited thereto. The synchronous rectification circuit 140 can generate a first control potential VC1 and a second control potential VC2 with a dead zone time DZT. For example, the first control potential VC1 and the second control potential VC2 can be substantially complementary logic levels. However, within the aforementioned dead zone time DZT, the first control potential VC1 and the second control potential VC2 can both be low logic levels (i.e., logic "0") at the same time. The detection and control circuit 150 is coupled to the synchronous rectification circuit 140 and can generate a first drive potential VG1 and a second drive potential VG2. In addition, the detection and control circuit 150 can also monitor the dead zone time DZT. If the dead time DZT is between a first critical value TH1 and a second critical value TH2, the detection and control circuit 150 can control the synchronous rectification circuit 140 according to the capacitor potential VP to update and increase the dead time DZT. According to actual measurement results, the power supply 100 of the present invention can effectively avoid non-ideal switching losses caused by insufficient dead time, thereby greatly improving its overall conversion efficiency.

The following embodiments will introduce the detailed structure and operation of the power supply 100. It must be understood that these drawings and descriptions are only examples and are not intended to limit the scope of the present invention.

FIG. 2 is a circuit diagram of a power supply 200 according to an embodiment of the present invention. In the embodiment of FIG. 2, the power supply 200 has an input node NIN and an output node NOUT, and includes: a switching circuit 210, a transformer 220, a first capacitor C1, an output stage circuit 230, a synchronous rectification circuit 240, and a detection and control circuit 250. The input node NIN of the power supply 200 can receive an input potential VIN from an external input power source (not shown), and the output node NOUT of the power supply 200 can be used to output an output potential VOUT to a system end (not shown).

The switching circuit 210 includes a first transistor M1 and a second transistor M2. For example, the first transistor M1 and the second transistor M2 may each be an N-type Metal-Oxide-Semiconductor Field-Effect Transistor (NMOSFET). The first transistor M1 has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain), wherein the control terminal of the first transistor M1 is used to receive a first driving potential VG1, the first terminal of the first transistor M1 is coupled to a first node N1 to output a switching potential VW, and the second terminal of the first transistor M1 is coupled to the input node NIN. The second transistor M2 has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain), wherein the control terminal of the second transistor M2 is used to receive a second driving potential VG2, the first terminal of the second transistor M2 is coupled to a ground potential VSS (e.g., 0V), and the second terminal of the second transistor M2 is coupled to the first node N1. In some embodiments, the first driving potential VG1 and the second driving potential VG2 may have the same switching frequency and complementary logic levels.

The transformer 220 includes a main coil 221, a first secondary coil 222, and a second secondary coil 223, wherein the transformer 220 may further have a built-in leakage inductor LR and an excitation inductor LM. The leakage inductor LR and the excitation inductor LM may be inherent components generated when the transformer 220 is manufactured, and are not external independent components. The leakage inductor LR, the main coil 221, and the excitation inductor LM may all be located on the same side of the transformer 220 (e.g., the primary side), while the first secondary coil 222 and the second secondary coil 223 may all be located on the opposite side of the transformer 220 (e.g., the secondary side, which may be isolated from the primary side). The leakage inductor LR has a first end and a second end, wherein the first end of the leakage inductor LR is coupled to the first node N1 to receive the switching potential VW, and the second end of the leakage inductor LR is coupled to a second node N2. The main coil 221 has a first end and a second end, wherein the first end of the main coil 221 is coupled to the second node N2, and the second end of the main coil 221 is coupled to a third node N3. The excitation inductor LM has a first end and a second end, wherein the first end of the excitation inductor LM is coupled to the second node N2, and the second end of the excitation inductor LM is coupled to the third node N3. The first capacitor C1 has a first end and a second end, wherein the first end of the first capacitor C1 is coupled to the third node N3 to output a capacitance potential VP, and the second end of the first capacitor C1 is coupled to the ground potential VSS. In some embodiments, the leakage inductor LR, the excitation inductor LM, and the first capacitor C1 can together form a resonant tank of the power supply 200. The first sub-coil 222 has a first end and a second end, wherein the first end of the first sub-coil 222 is coupled to a fourth node N4, and the second end of the first sub-coil 222 is coupled to a common node NCM. For example, the common node NCM can provide a common potential, which can be regarded as another ground potential and can be the same as or different from the aforementioned ground potential VSS. The second sub-coil 223 has a first end and a second end, wherein the first end of the second sub-coil 223 is coupled to the common node NCM, and the second end of the second sub-coil 223 is coupled to a fifth node N5.

The output stage circuit 230 includes a third transistor M3, a fourth transistor M4, and a second capacitor C2. For example, the third transistor M3 and the fourth transistor M4 can each be an N-type metal oxide semi-conductor field effect transistor. The third transistor M3 has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain), wherein the control terminal of the third transistor M3 is used to receive a first control potential VC1, the first terminal of the third transistor M3 is coupled to the output node NOUT, and the second terminal of the third transistor M3 is coupled to the fourth node N4. The fourth transistor M4 has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain), wherein the control terminal of the fourth transistor M4 is used to receive a second control potential VC2, the first terminal of the fourth transistor M4 is coupled to the output node NOUT, and the second terminal of the fourth transistor M4 is coupled to the fifth node N5. The second capacitor C2 has a first terminal and a second terminal, wherein the first terminal of the second capacitor C2 is coupled to the output node NOUT, and the second terminal of the second capacitor C2 is coupled to the common node NCM. In some embodiments, a first current I1 may flow through the third transistor M3, and a second current I2 may flow through the fourth transistor M4.

The synchronous rectifier circuit 240 can generate a first control potential VC1 and a second control potential VC2 with a dead time DZT. For example, the first control potential VC1 and the second control potential VC2 can be substantially complementary logic levels. However, within the aforementioned dead time DZT, the first control potential VC1 and the second control potential VC2 can both be low logic levels at the same time, and this design can prevent the third transistor M3 and the fourth transistor M4 of the output stage circuit 230 from being turned on at the same time. It must be noted that the dead time DZT of the synchronous rectifier circuit 240 can also be adjusted by the detection and control circuit 250.

The detection and control circuit 250 includes an average circuit 252, a divider 254, and a microcontroller unit (MCU) 256, and its functions and operation methods will be described in detail in the following embodiments.

The averaging circuit 252 is coupled to the third node N3. The averaging circuit 252 can be used to average the capacitor potential VP to generate an average potential VA. For example, the average potential VA can be substantially equal to an average value of the capacitor potential VP within a given period of time, but is not limited thereto.

The divider 254 is coupled to the averaging circuit 252. The divider 254 can divide the average potential VA by a reference potential VR to generate a gain factor QN, wherein the divider 254 can be powered by a supply potential VCC. For example, if the supply potential VCC has a high logic level (i.e., logic "1"), the divider 254 will be enabled; conversely, if the supply potential VCC has a low logic level, the divider 254 will be disabled. In some embodiments, the operating principle of the divider 254 can be described as the following equation (1):

…………………………………………(1) Where “QN” represents the value of the gain factor QN, “VA” represents the potential level of the average potential VA, and “VR” represents the potential level of the reference potential VR.

The microcontroller 256 is coupled to the synchronous rectifier circuit 240 and the divider 254, respectively. The microcontroller 256 can monitor the dead time DZT of the synchronous rectifier circuit 240, and can generate the aforementioned first driving potential VG1, the second driving potential VG2, and the reference potential VR. For example, the reference potential VR can be a fixed value. In detail, the microcontroller 256 can compare the dead time DZT with a first critical value TH1 and a second critical value TH2. If the dead time DZT is between the first critical value TH1 and the second critical value TH2 (that is, ), the microcontroller 256 can output a supply potential VCC with a high logic level, and can further receive a gain factor QN from the divider 254. In some embodiments, the first threshold value TH1 can be approximately equal to 60ns, and the second threshold value TH2 can be approximately equal to 300ns, but is not limited thereto.

FIG. 3 shows a potential waveform diagram of the first control potential VC1 and the second control potential VC2 according to an embodiment of the present invention, wherein the horizontal axis represents time (s) and the vertical axis represents potential level (V). As shown in FIG. 3, if the dead time DZT is between the first critical value TH1 and the second critical value TH2, the microcontroller 256 can further control the synchronous rectifier circuit 240 to update the dead time DZT by multiplying the dead time DZT by the gain multiplier QN. Generally speaking, the updated dead time DZT' will be longer than the original dead time DZT. In some embodiments, the updated dead time DZT' can be as described in the following equation (2):

……………………………………(2) “DZT’” represents the length of the updated dead time DZT’, “QN” represents the value of the gain factor QN, and “DZT” represents the length of the original dead time DZT.

FIG. 4 is a schematic diagram showing a system end 290 according to an embodiment of the present invention. For example, the system end 290 may be a laptop computer, but is not limited thereto. In the embodiment of FIG. 4 , the system end 290 may include a main circuit board 292 and an embedded controller (EC) 294, wherein the main circuit board 292 may receive the output potential VOUT from the power supply 200, and the embedded controller 294 may be disposed on the main circuit board 292. It should be noted that the system end 290 is not a part of the power supply 200.

In some embodiments, if the dead time DZT is less than the first threshold value TH1 (ie, ), the microcontroller 256 will transmit a notification voltage VT to the embedded controller 294 of the system end 290, and force the power supply 200 to enter a latch protection mode after a delay time TD. Therefore, the system end 290 will be able to detect the abnormal state of the power supply 200 based on the notification voltage VT, and the power supply 200 operating in the latch protection mode will no longer provide any power to the system end 290. For example, the aforementioned delay time TD may be between 1ms and 2.5ms, but is not limited thereto.

FIG. 5 shows a signal waveform of a conventional power supply, wherein the horizontal axis represents time (s) and the vertical axis represents potential level (V) or current value (A). As shown in FIG. 5, under the premise that the dead time DZT is not long enough, the conventional power supply usually cannot achieve the goal of zero-current switching (ZCS) operation (as indicated by a plurality of dashed boxes 571, 572, 573, 574). Therefore, conventional power supplies often face the problem of excessive switching loss.

FIG. 6 shows a signal waveform diagram of a power supply 200 according to an embodiment of the present invention, wherein the horizontal axis represents time (s) and the vertical axis represents potential level (V) or current value (A). According to the measurement results of FIG. 6, under the design of the present invention, the power supply 200 can appropriately increase the dead time DZT of the synchronous rectification circuit 240, so that its output stage circuit 230 can almost achieve perfect zero current switching operation (as indicated by a plurality of dashed boxes 671, 672, 673, 674). Therefore, the power supply 200 of the present invention can provide a relatively high conversion efficiency.

The present invention proposes a novel power supply. According to actual measurement results, the overall conversion efficiency of the power supply using the above design will be significantly improved, so it is very suitable for application in various types of devices.

It is worth noting that the potential, current, resistance, inductance, capacitance, and other component parameters described above are not limiting conditions of the present invention. Designers can adjust these settings according to different needs. The power supply of the present invention is not limited to the states shown in Figures 1-6. The present invention may only include any one or more features of any one or more embodiments of Figures 1-6. In other words, not all of the features shown in the diagrams need to be implemented in the power supply of the present invention at the same time. Although the embodiments of the present invention use metal oxide semi-conductor field effect transistors as an example, the present invention is not limited to this. People in the technical field can use other types of transistors, such as junction field effect transistors, or fin field effect transistors, etc., without affecting the effects of the present invention.

Ordinal numbers in this specification and the scope of the patent application, such as "first", "second", "third", etc., have no sequential relationship with each other, and are only used to mark and distinguish two different components with the same name.

Although the present invention is disclosed as above with the preferred embodiments, it is not intended to limit the scope of the present invention. Anyone skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the attached patent application.

100,200: Power supply 110,210: Switching circuit 120,220: Transformer 121,221: Main coil 122,222: First secondary coil 123,223: Second secondary coil 130,230: Output stage circuit 140,240: Synchronous rectification circuit 150,250: Detection and control circuit 252: Averaging circuit 254: Divider 256: Microcontroller 290: System side 292: Main circuit board 294: Embedded controller 571,572,573,574,671,672,673,674: Dashed frame C1: First capacitor C2: Second capacitor DZT: Dead time DZT’: Dead time after update I1: First current I2: Second current LM: Excitation inductor LR: Leakage inductor M1: First transistor M2: Second transistor M3: Third transistor M4: Fourth transistor N1: First node N2: Second node N3: Third node N4: Fourth node N5: Fifth node NCM: Common node NIN: Input node NOUT: Output node QN: Gain multiplier TD: Delay time TH1: First threshold value TH2: Second threshold value VA: Average potential VC1: First control potential VC2: Second control potential VCC: Supply potential VIN: Input potential VG1: First drive potential VG2: Second drive potential VOUT: Output potential VP: Capacitor potential VR: Reference potential VSS: Ground potential VT: Notification potential VW: Switching potential

FIG. 1 is a schematic diagram showing a power supply according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing a power supply according to an embodiment of the present invention. FIG. 3 is a potential waveform diagram showing a first control potential and a second control potential according to an embodiment of the present invention. FIG. 4 is a schematic diagram showing a system end according to an embodiment of the present invention. FIG. 5 is a signal waveform diagram showing a conventional power supply. FIG. 6 is a signal waveform diagram showing a power supply according to an embodiment of the present invention.

100: Power supply

110: Switching circuit

120: Transformer

121: Main coil

122: First coil

123: Second coil

130: Output stage circuit

140: Synchronous rectification circuit

150: Detection and control circuit

C1: First capacitor

DZT: Dead Zone Time

LM: Magnetizing inductor

LR: Leakage Inductor

TH1: First critical value

TH2: Second critical value

VC1: first control potential

VC2: Second control potential

VIN: input voltage

VG1: first driving potential

VG2: Second driving potential

VOUT: output voltage

VP: Capacitor potential

VW: Switching potential

Claims (10)

A power supply with high conversion efficiency, comprising: A switching circuit, generating a switching potential according to an input potential, a first drive potential, and a second drive potential; A transformer, comprising a main coil, a first sub-coil, and a second sub-coil, wherein the transformer has a built-in leakage inductor and an excitation inductor, and the main coil receives the switching potential through the leakage inductor; A first capacitor, coupled to the excitation inductor and providing a capacitance potential; An output stage circuit, coupled to the first sub-coil and the second sub-coil, wherein the output stage circuit generates an output potential according to a first control potential and a second control potential; A synchronous rectification circuit, generating the first control potential and the second control potential with a dead time; and A detection and control circuit is coupled to the synchronous rectification circuit and generates the first driving potential and the second driving potential; Wherein, the detection and control circuit further monitors the dead time, and if the dead time is between a first critical value and a second critical value, the detection and control circuit controls the synchronous rectification circuit according to the capacitor potential to update and increase the dead time. A power supply as claimed in claim 1, wherein the switching circuit comprises: a first transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the first transistor is used to receive the first driving potential, the first terminal of the first transistor is coupled to a first node to output the switching potential, and the second terminal of the first transistor is coupled to an input node to receive the input potential; and a second transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the second transistor is used to receive the second driving potential, the first terminal of the second transistor is coupled to a ground potential, and the second terminal of the second transistor is coupled to the first node. A power supply as claimed in claim 2, wherein the leakage inductor has a first end and a second end, the first end of the leakage inductor is coupled to the first node to receive the switching potential, the second end of the leakage inductor is coupled to a second node, the main coil has a first end and a second end, the first end of the main coil is coupled to the second node, the second end of the main coil is coupled to a third node, the excitation inductor has a first end and a second end, the first end of the excitation inductor is coupled to the second node, the second end of the excitation inductor is coupled to the third node point, the first capacitor has a first end and a second end, the first end of the first capacitor is coupled to the third node to output the capacitance potential, the second end of the first capacitor is coupled to the ground potential, the first sub-coil has a first end and a second end, the first end of the first sub-coil is coupled to a fourth node, the second end of the first sub-coil is coupled to a common node, the second sub-coil has a first end and a second end, the first end of the second sub-coil is coupled to the common node, and the second end of the second sub-coil is coupled to a fifth node. A power supply as claimed in claim 3, wherein the output stage circuit comprises: a third transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the third transistor is used to receive the first control potential, the first terminal of the third transistor is coupled to an output node to output the output potential, and the second terminal of the third transistor is coupled to the fourth node; a fourth transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the fourth transistor is used to receive the second control potential, the first terminal of the fourth transistor is coupled to the output node, and the second terminal of the fourth transistor is coupled to the fifth node; and a second capacitor having a first terminal and a second terminal, wherein the first terminal of the second capacitor is coupled to the output node, and the second terminal of the second capacitor is coupled to the common node. A power supply as claimed in claim 1, wherein the first critical value is approximately equal to 60ns, and the second critical value is approximately equal to 300ns. A power supply as claimed in claim 1, wherein the detection and control circuit comprises: An averaging circuit that averages the capacitor potential to generate an average potential. A power supply as claimed in claim 6, wherein the detection and control circuit further comprises: A divider that divides the average potential by a reference potential to generate a gain multiplier, wherein the divider is powered by a supply potential. The power supply of claim 7, wherein the detection and control circuit further comprises: A microcontroller, monitoring the dead time, and generating the first drive potential, the second drive potential, and the reference potential, wherein if the dead time is between the first critical value and the second critical value, the microcontroller outputs the supply potential with a high logic level, and further receives the gain multiplier from the divider. A power supply as claimed in claim 8, wherein if the dead time is between the first critical value and the second critical value, the microcontroller further controls the synchronous rectification circuit to update the dead time by multiplying the dead time by the gain factor. As in the power supply of claim 8, if the dead time is less than the first critical value, the microcontroller will transmit a notification potential to a system end and force the power supply to enter a latching protection mode after a delay time.

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