TW202207595A - Boost converter with low noise - Google Patents

Abstract

A power supply device with low noise includes a bridge rectifier, a first inductor, a second inductor, a first power switch element, a second power switch element, an energy release circuit, an energy recovery circuit, and an output stage circuit. The bridge rectifier generates a rectified voltage according to a first input voltage and a second input voltage. The first inductor and the second inductor receive the rectified voltage. The first power switch element selectively couples the first inductor to a ground voltage. The second power switch element selectively couples the second inductor to the ground voltage. The output stage circuit includes an energy compensation circuit and generates an output voltage. The electromagnetic energy stored in the first inductor and the second inductor is transferred through the energy recovery circuit and the energy release circuit to the energy compensation circuit.

Description

Low noise boost converter

The present invention relates to a boost converter, in particular to a low noise boost converter.

Traditional boost converters typically employ current-mode control. However, when the duty cycle of the power switch is greater than 50%, the conventional boost converter is prone to sub-harmonic oscillation, and the associated noise rises. In view of this, it is necessary to propose a new solution to overcome the difficulties faced by the previous technology.

In a preferred embodiment, the present invention provides a low-noise boost converter, comprising: a bridge rectifier for generating a rectified potential according to a first input potential and a second input potential; a first inductor, receiving the rectified potential; a first power switch selectively coupling the first inductor to a ground potential according to a first pulse width modulation potential; a second inductor receiving the rectified potential; a second power switch selectively coupling the second inductor to the ground potential according to a second PWM potential; a PWM integrated circuit generating the first PWM variable potential and the second pulse width modulated potential; an energy release circuit; an energy recovery circuit coupled in parallel with the energy release circuit; and an output stage circuit including an energy compensation circuit and generating an output potential , wherein the output stage circuit is coupled to the first inductor, the second inductor, the energy release circuit, and the energy recovery circuit; wherein the electromagnetic energy stored by the first inductor and the second inductor It is transferred to the energy compensation circuit via the energy recovery circuit and the energy release circuit.

In order to make the objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are given in the following, and are described in detail as follows in conjunction with the accompanying drawings.

Certain terms are used throughout the specification and claims to refer to particular elements. It should be understood by those skilled in the art that hardware manufacturers may refer to the same element by different nouns. This specification and the scope of the patent application do not use the difference in name as a way to distinguish elements, but use the difference in function of the elements as a criterion for distinguishing. The words "including" and "including" mentioned in the entire specification and the scope of the patent application are open-ended terms, so they should be interpreted as "including but not limited to". The word "substantially" means that within an acceptable error range, those skilled in the art can solve the technical problem within a certain error range and achieve the basic technical effect. Furthermore, the term "coupled" in this specification includes any direct and indirect electrical connection means. Therefore, if a first device is described as being coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices or connecting means. Second device.

FIG. 1 shows a schematic diagram of a boost converter 100 according to an embodiment of the present invention. For example, the boost converter 100 may be applied to a desktop computer, a notebook computer, or an all-in-one computer. As shown in FIG. 1, the boost converter 100 includes: a bridge rectifier 110, a first inductor L1, a second inductor L2, a first power switch 120, a second power switch 130, a The pulse width modulation integrated circuit 140 , an energy release circuit 150 , an energy recovery circuit 160 , and an output stage circuit 170 , wherein the output stage circuit 170 includes an energy compensation circuit 180 . It should be noted that, although not shown in FIG. 1, the boost converter 100 may further include other components, such as a voltage regulator or/and a negative feedback circuit.

The bridge rectifier 110 can generate a rectified potential VR according to a first input potential VIN1 and a second input potential VIN2. Both the first input potential VIN1 and the second input potential VIN2 can come from an external input power source, wherein an AC voltage with any frequency and any amplitude can be formed between the first input potential VIN1 and the second input potential VIN2. For example, the frequency of the AC voltage can be about 50Hz or 60Hz, and the RMS value of the AC voltage can be from 90V to 264V, but it is not limited thereto. The first inductor L1 can receive the rectified potential VR. The first power switch 120 can selectively couple the first inductor L1 to a ground potential VSS (eg, 0V) according to a first PWM potential VM1. For example, if the first PWM potential VM1 is at a high logic level, the first power switch 120 can couple the first inductor L1 to the ground potential VSS (that is, the first power switch 120 can approximating a short-circuit path); otherwise, if the first PWM potential VM1 is at a low logic level, the first power switch 120 will not couple the first inductor L1 to the ground potential VSS (ie, The first power switch 120 may approximate an open path). The second inductor L2 can also receive the rectified potential VR. The second power switch 130 can selectively couple the second inductor L2 to the ground potential VSS according to a second PWM potential VM2. For example, if the second PWM potential VM2 is at a high logic level, the second power switch 130 can couple the second inductor L2 to the ground potential VSS (that is, the second power switch 130 can similar to a short-circuit path); otherwise, if the second PWM potential VM2 is at a low logic level, the second power switch 130 will not couple the second inductor L2 to the ground potential VSS (ie, The second power switch 130 may approximate an open path). The PWM integrated circuit 140 can generate a first PWM potential VM1 and a second PWM potential VM2. In some embodiments, the first PWM potential VM1 and the second PWM potential VM2 may have the same waveform but have a phase difference therebetween, so that the two are not at high logic levels at the same time. The energy recovery circuit 160 may be coupled in parallel with the energy release circuit 150 . The output stage circuit 170 can generate an output potential VOUT. For example, the output potential VOUT may be approximately a DC potential, and its level may be approximately 400V, but it is not limited thereto. The output stage circuit 170 may be coupled to the first inductor L1 , the second inductor L2 , the energy release circuit 150 , and the energy recovery circuit 160 at the same time. It should be noted that the electromagnetic energy stored in the first inductor L1 and the second inductor L2 can be transferred to the energy compensation circuit 180 of the output stage circuit 170 via the energy recovery circuit 160 and the energy release circuit 150 . Under this design, the duty cycle of each of the first power switch 120 and the second power switch 130 can be less than 50% to suppress unnecessary sub-harmonic oscillation in the boost converter 100 . Therefore, the related noise of the boost converter 100 can be effectively reduced.

The following embodiments will introduce the detailed structure and operation of the boost converter 100 . It must be understood that these drawings and descriptions are only examples and are not intended to limit the scope of the present invention.

FIG. 2 shows a schematic diagram of a boost converter 200 according to an embodiment of the present invention. In the embodiment of FIG. 2, the boost converter 200 has a first input node NIN1, a second input node NIN2, and an output node NOUT, and includes a bridge rectifier 210, a first inductor L1, A second inductor L2, a first power switch 220, a second power switch 230, a pulse width modulation integrated circuit 240, an energy release circuit 250, an energy recovery circuit 260, and an output stage circuit 270 , wherein the output stage circuit 270 includes an energy compensation circuit 280 . The first input node NIN1 and the second input node NIN2 of the boost converter 200 can respectively receive a first input potential VIN1 and a second input potential VIN2 from an external input power source, and the output node NOUT of the boost converter 200 It can be used to output an output potential VOUT to an electronic device (not shown).

The bridge rectifier 210 includes a first diode D1, a second diode D2, a third diode D3, and a fourth diode D4. The anode of the first diode D1 is coupled to the first input node NIN1, and the cathode of the first diode D1 is coupled to a first node N1 to output a rectified potential VR. The anode of the second diode D2 is coupled to the second input node NIN2, and the cathode of the second diode D2 is coupled to the first node N1. The anode of the third diode D3 is coupled to a ground potential VSS, and the cathode of the third diode D3 is coupled to the first input node NIN1. The anode of the fourth diode D4 is coupled to the ground potential VSS, and the cathode of the fourth diode D4 is coupled to the second input node NIN2.

The first end of the first inductor L1 is coupled to the first node N1 to receive the rectified potential VR, and the second end of the first inductor L1 is coupled to a second node N2.

The first end of the second inductor L2 is coupled to the first node N1 to receive the rectified potential VR, and the second end of the second inductor L2 is coupled to a third node N3.

The first power switch 220 includes a first transistor M1. The first transistor M1 can be an N-type MOSFET. The first transistor M1 has a control terminal (eg, a gate), a first terminal (eg, a source), and a second terminal (eg, a drain), wherein the control of the first transistor M1 The terminal is used for receiving a first pulse width modulation potential VM1, the first terminal of the first transistor M1 is coupled to the ground potential VSS, and the second terminal of the first transistor M1 is coupled to the second node N2. The first PWM potential VM1 can be used to adjust the duty cycle of the first power switch 220 . For example, if the first PWM potential VM1 is at a high logic level, the first transistor M1 will be enabled; on the contrary, if the first PWM potential VM1 is at a low logic level, the first transistor M1 will be enabled. A transistor M1 will be disabled.

The second power switch 230 includes a second transistor M2. The second transistor M2 can be an N-type MOSFET. The control terminal of the second transistor M2 is used for receiving a second PWM potential VM2, the first terminal of the second transistor M2 is coupled to the ground potential VSS, and the second terminal of the second transistor M2 is coupled to the third node N3. The second PWM potential VM2 can be used to adjust the duty cycle of the second power switch 230 . For example, if the second PWM potential VM2 is at a high logic level, the second transistor M2 will be enabled; on the contrary, if the second PWM potential VM2 is at a low logic level, the first transistor M2 will be enabled. The second transistor M2 will be disabled.

The PWM integrated circuit 240 can generate a first PWM potential VM1 and a second PWM potential VM2. For example, the first PWM potential VM1 and the second PWM potential VM2 can be maintained at a fixed potential when the boost converter 200 is initialized, and can be maintained at a fixed potential when the boost converter 200 enters a normal use stage. Provides periodic clock waveforms.

The energy release circuit 250 includes a fifth diode D5 and a third inductor L3. The anode of the fifth diode D5 is coupled to the ground potential VSS, and the cathode of the fifth diode D5 is coupled to a fourth node N4. The first end of the third inductor L3 is coupled to the fourth node N4, and the second end of the third inductor L3 is coupled to a fifth node N5.

The energy recovery circuit 260 includes a fourth inductor L4, a first resistor R1, and a sixth diode D6. The first end of the fourth inductor L4 is coupled to the ground potential VSS, and the second end of the fourth inductor L4 is coupled to a sixth node N6. The first end of the first resistor R1 is coupled to the sixth node N6, and the second end of the first resistor R1 is coupled to a seventh node N7. The anode of the sixth diode D6 is coupled to the fifth node N5, and the cathode of the sixth diode D6 is coupled to the seventh node N7. In some embodiments, the first inductor L1 and the fourth inductor L4 are coupled to each other, and the second inductor L2 and the fourth inductor L4 are also coupled to each other.

The energy compensation circuit 280 of the output stage circuit 270 includes a first capacitor C1, a second resistor R2, a fifth inductor L5, and a seventh diode D7. The first end of the first capacitor C1 is coupled to the fifth node N5, and the second end of the first capacitor C1 is coupled to a common node NCM. For example, the common node NCM may provide another ground potential, which may be the same as or different from the aforementioned ground potential VSS. The first end of the second resistor R2 is coupled to an eighth node N8, and the second end of the second resistor R2 is coupled to the fifth node N5. The first end of the fifth inductor L5 is coupled to the eighth node N8, and the second end of the fifth inductor L5 is coupled to a ninth node N9. The anode of the seventh diode D7 is coupled to the common node NCM, and the cathode of the seventh diode D7 is coupled to the ninth node N9. In some embodiments, the third inductor L3 and the fifth inductor L5 are coupled to each other.

In addition to the energy compensation circuit 280, the output stage circuit 270 further includes an eighth diode D8, a ninth diode D9, a second capacitor C2, and a third capacitor C3. The anode of the eighth diode D8 is coupled to the second node N2, and the cathode of the eighth diode D8 is coupled to the output node NOUT. The anode of the ninth diode D9 is coupled to the third node N3, and the cathode of the ninth diode D9 is coupled to the output node NOUT. The second capacitor C2 has a first terminal and a second terminal, wherein the first terminal of the second capacitor C2 is coupled to the output node NOUT, and the second terminal of the second capacitor C2 is coupled to the fifth node N5. The first terminal of the third capacitor C3 is coupled to the output node NOUT, and the second terminal of the third capacitor C3 is coupled to the common node NCM.

FIG. 3 shows a potential waveform diagram of the boost converter 200 according to an embodiment of the present invention, wherein the horizontal axis represents time and the vertical axis represents potential level. According to the measurement results in FIG. 3 , the boost converter 200 can operate in a first stage T1 , a second stage T2 , a third stage T3 , and a fourth stage T4 one by one, the principle of which can be described as follows . It must be noted that there is a first potential difference VD1 between the first end and the second end of the first capacitor C1, a second potential difference VD2 between the first end and the second end of the second capacitor C2, and the third There is a third potential difference VD3 between the first end and the second end of the capacitor C3. When the potential of the common node NCM is set to 0V, the potential level of the output potential VOUT may be approximately equal to the third potential difference VD3.

During the first phase T1, the first PWM potential VM1 is at a high logic level and the second PWM potential VM2 is at a low logic level, so that the first transistor M1 is enabled, and the second Transistor M2 is disabled. At this time, the first inductor L1 gradually stores electromagnetic energy. Neither the energy release circuit 250 nor the energy recovery circuit 260 operates. The first potential difference VD1 of the first capacitor C1, the second potential difference VD2 of the second capacitor C2, and the third potential difference VD3 of the third capacitor C3 are all maintained at 0V.

During the second phase T2, both the first PWM potential VM1 and the second PWM potential VM2 are at low logic levels, so that both the first transistor M1 and the second transistor M2 are disabled. At this time, the electromagnetic energy stored in the first inductor L1 will charge the second capacitor C2 through the eighth diode D8. The fourth inductor L4 of the energy recovery circuit 260 gradually stores electromagnetic energy, but the energy release circuit 250 does not operate. Since the first capacitor C1 is not yet charged, the third potential difference VD3 of the third capacitor C3 is equal to the second potential difference VD2 of the second capacitor C2, which gradually increases from 0V.

During the third phase T3, the first PWM potential VM1 is at a low logic level and the second PWM potential VM2 is at a high logic level, so that the first transistor M1 is disabled and the second transistor M1 is disabled. Transistor M2 is enabled. At this time, the voltage of the fourth inductor L4 of the energy recovery circuit 260 is reversed due to the cold second law, and the fifth diode D5 of the energy release circuit 250 is forced to be enabled. Since the electromagnetic energy stored in the fourth inductor L4 is transferred to the first capacitor C1 through the third inductor L3 and the fifth inductor L5, the first capacitor C1 is charged. Therefore, the third potential difference VD3 of the third capacitor C3 is approximately equal to the sum of the first potential difference VD1 and the second potential difference VD2.

During the fourth phase T4, both the first PWM potential VM1 and the second PWM potential VM2 are at low logic levels, so that both the first transistor M1 and the second transistor M2 are disabled. At this time, the electromagnetic energy stored in the second inductor L2 will charge the second capacitor C2 through the ninth diode D9. The fourth inductor L4 of the energy recovery circuit 260 gradually stores electromagnetic energy, but the energy release circuit 250 does not operate. Because the seventh diode D7 of the energy compensation circuit 280 is disabled, the first potential difference VD1 of the first capacitor C1 can remain unchanged. Therefore, the third potential difference VD3 of the third capacitor C3 is also approximately equal to the sum of the first potential difference VD1 and the second potential difference VD2.

Briefly, the different operating stages of the boost converter 200 can be described in Table 1 below: The first transistor M1 The second transistor M2 Energy Release Circuit 250 Energy Release and Recovery Road 260 The third potential difference VD3 The first stage T1 enable Disable no action no action 0 The second stage T2 Disable Disable no action action VD2 The third stage T3 Disable enable action action VD1+VD2 Fourth stage T4 Disable Disable no action action VD1+VD2 Table 1: Operating Characteristics of Different Stages of Boost Converter

According to the measurement result in Fig. 3, the present invention additionally uses the first potential difference VD1 of the first capacitor C1 to compensate the third potential difference VD3 (or the output potential VOUT) of the third capacitor C3, so that the second potential difference of the second capacitor C2 The potential difference VD2 can be set to a relatively low value (eg, the conventional second potential difference VD2 must be equal to 400V, but the second potential difference VD2 of the present invention can be only about 250V, but not limited thereto). Under this design, the proposed boost converter 200 can ensure that the duty cycle of each of the first power switch 220 and the second power switch 230 can be less than 50%, so that the boost converter 200 can be effectively reduced related news.

In some embodiments, the component parameters of the boost converter 200 may be as follows. The capacitance value of the first capacitor C1 can be between 544 μF and 816 μF, preferably 680 μF. The capacitance value of the second capacitor C2 may be between 544 μF and 816 μF, preferably 680 μF. The capacitance value of the third capacitor C3 may be between 1200 μF and 1800 μF, preferably 1500 μF. The inductance value of the first inductor L1 may be between 315 μH and 385 μH, preferably 350 μH. The inductance value of the second inductor L2 can be between 315μH and 385μH, preferably 350μH. The inductance value of the third inductor L3 can be between 127.5 μH and 172.5 μH, preferably 150 μH. The inductance value of the fourth inductor L4 may be between 187 μH and 253 μH, preferably 220 μH. The inductance value of the fifth inductor L5 may be between 382.5 μH and 517.5 μH, preferably 450 μH. The resistance value of the first resistor R1 may be between 90Ω and 110Ω, preferably 100Ω. The resistance value of the second resistor R2 may be between 0.9KΩ and 1.1KΩ, preferably 1KΩ. The maximum duty cycle of each of the first power switch 220 and the second power switch 230 may be approximately 49.2%. The maximum value of the first potential difference VD1 may be about 150V. The maximum value of the second potential difference VD2 may be about 250V. The maximum value of the third potential difference VD3 may be about 400V. The above parameter ranges are derived from multiple experimental results, which help to minimize sub-harmonic oscillations of the boost converter 200 .

The present invention proposes a novel boost converter that includes an energy release circuit and an energy recovery circuit to minimize the duty cycle of the power switch. According to the actual measurement results, using the boost converter of the above design can greatly reduce the related noise, so it is very suitable for use in various devices.

It should be noted that the potential, current, resistance value, inductance value, capacitance value and other component parameters mentioned above are not limitations of the present invention. Designers can adjust these settings according to different needs. The boost converter of the present invention is not limited to the state illustrated in FIGS. 1-3. The present invention may include only any one or more of the features of any one or more of the embodiments of Figures 1-3. In other words, not all of the features shown must be simultaneously implemented in the boost converter of the present invention.

Although the present invention is disclosed above with preferred embodiments, it is not intended to limit the scope of the present invention. Anyone skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the scope of the appended patent application.

100,200: Boost Converter 110, 210: Bridge Rectifiers 120,220: First power switch 130,230: Second power switch 140, 240: Pulse Width Modulation Integrated Circuits 150,250: Energy Release Circuit 160, 260: Energy Recovery Circuits 170, 270: Output stage circuit 180,280: Energy Compensation Circuit C1: first capacitor C2: Second capacitor C3: Third capacitor D1: first diode D2: Second diode D3: Third diode D4: Fourth diode D5: Fifth diode D6: sixth diode D7: seventh diode D8: Eighth diode D9: ninth diode L1: first inductor L2: Second Inductor L3: Third Inductor L4: Fourth Inductor L5: Fifth inductor M1: first transistor M2: second transistor N1: the first node N2: second node N3: The third node N4: Fourth Node N5: Fifth node N6: sixth node N7: seventh node N8: Eighth Node N9: ninth node NCM: Common Node NIN1: The first input node NIN2: Second input node NOUT: output node R1: first resistor R2: Second resistor T1: Phase 1 T2: Phase 2 T3: Stage Three T4: Stage Four VD1: The first potential difference VD2: The second potential difference VD3: The third potential difference VIN1: the first input potential VIN2: The second input potential VM1: The first PWM potential VM2: The second PWM potential VOUT: output potential VR: rectified potential VSS: ground potential

FIG. 1 shows a schematic diagram of a boost converter according to an embodiment of the present invention. FIG. 2 shows a schematic diagram of a boost converter according to an embodiment of the present invention. FIG. 3 shows a potential waveform diagram of a boost converter according to an embodiment of the present invention.

100: Boost Converter

110: Bridge Rectifier

120: The first power switch

130: Second power switch

140: Pulse width modulation integrated circuit

150: Energy release circuit

160: Energy Recovery Circuit

170: Output stage circuit

180: Energy compensation circuit

L1: first inductor

L2: Second Inductor

VIN1: the first input potential

VIN2: The second input potential

VM1: The first PWM potential

VM2: The second PWM potential

VOUT: output potential

VR: rectified potential

VSS: ground potential

Claims (10)

A low noise boost converter comprising: a bridge rectifier, generating a rectified potential according to a first input potential and a second input potential; a first inductor, receiving the rectified potential; a first power switch selectively coupling the first inductor to a ground potential according to a first PWM potential; a second inductor, receiving the rectified potential; a second power switch selectively coupling the second inductor to the ground potential according to a second PWM potential; a pulse width modulation integrated circuit generating the first pulse width modulation potential and the second pulse width modulation potential; an energy release circuit; an energy recovery circuit coupled in parallel with the energy release circuit; and an output stage circuit including an energy compensation circuit and generating an output potential, wherein the output stage circuit is coupled to the first inductor, the second inductor, the energy release circuit, and the energy recovery circuit; The electromagnetic energy stored in the first inductor and the second inductor is transferred to the energy compensation circuit via the energy recovery circuit and the energy release circuit. The boost converter of claim 1, wherein the bridge rectifier comprises: a first diode having an anode and a cathode, wherein the anode of the first diode is coupled to a first input node to receive the first input potential, and the first diode the cathode is coupled to a first node to output the rectified potential; a second diode having an anode and a cathode, wherein the anode of the second diode is coupled to a second input node to receive the second input potential, and the second diode the cathode is coupled to the first node; a third diode having an anode and a cathode, wherein the anode of the third diode is coupled to the ground potential and the cathode of the third diode is coupled to the first input node; and a fourth diode having an anode and a cathode, wherein the anode of the fourth diode is coupled to the ground potential, and the cathode of the fourth diode is coupled to the second input node. The boost converter of claim 2, wherein the first inductor has a first terminal and a second terminal, the first terminal of the first inductor is coupled to the first node to receive the rectification potential, the second end of the first inductor is coupled to a second node, the second inductor has a first end and a second end, the first end of the second inductor is coupled to The first node receives the rectified potential, and the second end of the second inductor is coupled to a third node. The boost converter of claim 3, wherein the first power switch comprises: A first transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the first transistor is used for receiving the first pulse width modulation potential, the first voltage The first terminal of the crystal is coupled to the ground potential, and the second terminal of the first transistor is coupled to the second node. The boost converter of claim 3, wherein the second power switch comprises: a second transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the second transistor is used for receiving the second pulse width modulation potential, the second voltage The first terminal of the crystal is coupled to the ground potential, and the second terminal of the second transistor is coupled to the third node. The boost converter of claim 3, wherein the energy release circuit comprises: a fifth diode having an anode and a cathode, wherein the anode of the fifth diode is coupled to the ground potential, and the cathode of the fifth diode is coupled to a fourth node ;as well as a third inductor having a first end and a second end, wherein the first end of the third inductor is coupled to the fourth node, and the second end of the third inductor is coupled Connect to a fifth node. The boost converter of claim 6, wherein the energy recovery circuit comprises: a fourth inductor having a first end and a second end, wherein the first end of the fourth inductor is coupled to the ground potential, and the second end of the fourth inductor is coupled to a sixth node; a first resistor having a first end and a second end, wherein the first end of the first resistor is coupled to the sixth node, and the second end of the first resistor is coupled connected to a seventh node; and a sixth diode having an anode and a cathode, wherein the anode of the sixth diode is coupled to the fifth node, and the cathode of the sixth diode is coupled to the seventh node. The boost converter of claim 7, wherein the energy compensation circuit of the output stage circuit comprises: a first capacitor having a first terminal and a second terminal, wherein the first terminal of the first capacitor is coupled to the fifth node, and the second terminal of the first capacitor is coupled to a common node; a second resistor having a first end and a second end, wherein the first end of the second resistor is coupled to an eighth node, and the second end of the second resistor is coupled connected to the fifth node; a fifth inductor having a first end and a second end, wherein the first end of the fifth inductor is coupled to the eighth node, and the second end of the fifth inductor is coupled connected to a ninth node; and a seventh diode having an anode and a cathode, wherein the anode of the seventh diode is coupled to the common node, and the cathode of the seventh diode is coupled to the ninth node . The boost converter of claim 8, wherein the first inductor and the fourth inductor are coupled to each other, the second inductor is coupled to the fourth inductor, and the third inductor is coupled to each other coupled with the fifth inductor. The boost converter of claim 8, wherein the output stage circuit further comprises: An eighth diode having an anode and a cathode, wherein the anode of the eighth diode is coupled to the second node, and the cathode of the eighth diode is coupled to an output node to output the output potential; a ninth diode having an anode and a cathode, wherein the anode of the ninth diode is coupled to the third node, and the cathode of the ninth diode is coupled to the output node ; a second capacitor having a first terminal and a second terminal, wherein the first terminal of the second capacitor is coupled to the output node, and the second terminal of the second capacitor is coupled to the first terminal five nodes; and a third capacitor having a first terminal and a second terminal, wherein the first terminal of the third capacitor is coupled to the output node, and the second terminal of the third capacitor is coupled to the common node.

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