[go: up one dir, main page]

TW201620106A - 具有打線結合的多晶粒堆疊的積體電路封裝 - Google Patents

具有打線結合的多晶粒堆疊的積體電路封裝 Download PDF

Info

Publication number
TW201620106A
TW201620106A TW104127511A TW104127511A TW201620106A TW 201620106 A TW201620106 A TW 201620106A TW 104127511 A TW104127511 A TW 104127511A TW 104127511 A TW104127511 A TW 104127511A TW 201620106 A TW201620106 A TW 201620106A
Authority
TW
Taiwan
Prior art keywords
die
package
encapsulation layer
interconnect structures
level interconnect
Prior art date
Application number
TW104127511A
Other languages
English (en)
Other versions
TWI657557B (zh
Inventor
索斯登 梅爾
保利 傑維納
理查德 帕滕
Original Assignee
英特爾股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 英特爾股份有限公司 filed Critical 英特爾股份有限公司
Publication of TW201620106A publication Critical patent/TW201620106A/zh
Application granted granted Critical
Publication of TWI657557B publication Critical patent/TWI657557B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3178—Coating or filling in grooves made in the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group subclass H10D
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, the devices being individual devices of subclass H10D or integrated devices of class H10
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45139—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48105—Connecting bonding areas at different heights
    • H01L2224/48106—Connecting bonding areas at different heights the connector being orthogonal to a side surface of the semiconductor or solid-state body, e.g. parallel layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48235—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85444—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85455—Nickel (Ni) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06575—Auxiliary carrier between devices, the carrier having no electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00012—Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1433—Application-specific integrated circuit [ASIC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/1579—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Wire Bonding (AREA)

Abstract

本發明之實施例關於積體電路(IC)封裝，該封裝包括至少部分嵌入在第一封裝層中的第一晶粒和至少部分嵌入在第二封裝層中的第二晶粒。第一晶粒具有配置在第一封裝層之第一側的第一複數個晶粒互連結構。IC封裝也包括至少部分嵌入在第一封裝層內的複數個電路由特徵，且被組構成在第一封裝層的第一側與第二側之間路由電信號。第二側可配置在第一側的相對側。第二晶粒具有第二複數個晶粒級互連結構，其藉由接合線與至少複數個電路由特徵的子集電耦接。

Description

具有打線結合的多晶粒堆疊的積體電路封裝
通言之，本發明之實施例與積體電路的領域有關，且更特定地與具有打線結合之多晶粒堆疊的積體電路封裝有關。
晶粒(諸如處理器)的輸入/輸出密度不斷提高，同時，晶粒的尺寸也在持續地縮小。因此需要縮短多晶粒封裝中各晶粒之間的互連距離，並保持多晶粒封裝之較小的形狀因數，但由於這些技術的進步而具挑戰性。
本文提供背景描述之目的係基於呈現本揭示的來龍去脈。除非本文有其它的指示，本節中所描述的材料並非本申請案中申請專利範圍的習知技術，且不認可本節包括習知技術。
100‧‧‧積體電路總成
102‧‧‧IC封裝
104‧‧‧第一封裝層
106‧‧‧第一晶粒
108‧‧‧晶粒級互連結構
110‧‧‧電路由部件
112‧‧‧重佈層
114‧‧‧焊球
116‧‧‧電路板
118‧‧‧電性絕緣材料
120‧‧‧第二封裝層
122‧‧‧第二晶粒
124‧‧‧晶粒級互連結構
126‧‧‧引線
128‧‧‧接墊
302‧‧‧第一晶粒
304‧‧‧晶粒級互連結構
306‧‧‧載體
308‧‧‧黏著劑
310‧‧‧電性絕緣材料
312‧‧‧電路由部件
314‧‧‧接合墊
316‧‧‧第一封裝層
318‧‧‧空洞
320‧‧‧介電層
322‧‧‧重佈層
324‧‧‧阻焊層
326‧‧‧第二晶粒
328‧‧‧黏著劑
330‧‧‧晶粒級互連結構
332‧‧‧引線
334‧‧‧第二封裝層
500‧‧‧積體電路封裝
502‧‧‧焊球
600‧‧‧積體電路封裝
602‧‧‧第三晶粒
604‧‧‧互連結構
606‧‧‧焊球
700‧‧‧積體電路封裝
702‧‧‧第一晶粒
704‧‧‧晶粒級互連結構
710‧‧‧電性絕緣材料
712‧‧‧電路由特徵
714‧‧‧接合墊
716‧‧‧第一封裝層
720‧‧‧介電層
722‧‧‧重佈層
724‧‧‧阻焊層
726‧‧‧第二晶粒
728‧‧‧黏著劑
730‧‧‧晶粒級互連
732‧‧‧引線
734‧‧‧第二封裝層
736‧‧‧引線
738‧‧‧引線
740‧‧‧間隔件
742‧‧‧晶粒級互連
800‧‧‧計算裝置
802‧‧‧主機板
804‧‧‧處理器
806‧‧‧通訊晶片
藉由以上配合附圖的詳細描述可很容易瞭解各實施例。為有利於本描述，相同的參考數字指示相同的結構元 件。實施例係藉由例子來說明而非藉由附圖的圖式來限制。除非有明確的指示，否則，這些圖並非按比例繪製。
圖1示意說明積體電路(IC)總成例的橫斷面視圖，其包括具有打線結合之多晶粒堆疊的積體電路封裝。
圖2係按照本發明之某些實施例之積體電路封裝製造程序的說明性流程圖。
圖3-4描繪按照本發明之某些實施例所選擇之操作的說明性橫斷面視圖，用來說明圖2中所描述之積體電路封裝製造程序中的各階段。
圖5概示說明按照本發明之各種實施例之例示積體電路(IC)總成的橫斷面側視圖，其具有封裝級互連結構。
圖6概示說明按照本發明之各種實施例之例示積體電路(IC)總成的橫斷面側視圖，其具有封裝級互連結構及配置於重佈層(RDL)上的第三晶粒。
圖7概示說明按照本發明之各種實施例之例示積體電路(IC)總成的橫斷面側視圖，其具有堆疊並打線結合的附加晶粒。
圖8概示說明按照本發明之各種實施例之包括有積體電路封裝的計算裝置。
【發明內容及實施方式】
本發明的實施例描述具有打線結合之多晶粒堆疊的積體電路(IC)封裝組構。在以下的描述中，將使用熟悉此領域之技藝者一般用來傳達其工作內容給其它熟悉此領域 之技藝者所使用的名詞來描述說明性實施例的各種態樣。不過，熟悉此領域之技藝者應明瞭，本發明的實施例可僅以所描述的某些態樣來實施。基於解釋之目的，為了提供對說明性實施例之徹底的瞭解而陳述了特定的數字、材料、及組構。不過，熟悉此領域之技藝者應明瞭，實施本發明的實施例並不需要這些特定的細節。在其它的例中，為了不模糊了說明性的實施例，習知的特徵被省略或簡化。
在以下的詳細描述中將參考構成本文之一部分的附圖，其中，在全文中相同的數字指示相同的部分，且其中顯示用以實施本發明之主題的說明性實施例。須瞭解，也可利用其它的實施例，且可做結構或邏輯上的改變，不會偏離本發明的範圍。因此，以下的詳細描述並無限制之意，且實施例之範圍係由所附申請專利範圍及它們的相等物來界定。
基於本揭示之目的，片語“A及/或B”意指“(A)、(B)、或(A與B)”。基於本揭示之目的，片語“A、B、及/或C”意指(A)、(B)、(C)、(A)與(B)、(A)與(C)、(B)與(C)、或(A、B與C)。
本描述使用基於透視的描述，諸如頂部/底部、內/外、之上/之下、等類似用語。使用此等描述僅取其有助於討論，而無意將本文所描述之實施例的應用限制在任何特定的方向。
描述所使用的片語“在一實施例中”、或“在各實施例 中”皆與一或多個相同或不同實施例有關。此外，關於本發明之實施例所使用的名詞“包含”、“包括”、“具有”等係同義字。
本文中會使用名詞“與...耦接”及其衍生名詞。“耦接”具有以下一或多種意義。“耦接”可意指兩或多個元件直接物理或電接觸。不過，“耦接”也可意指兩或多個元件彼此間接接觸，但仍彼此合作或互動，且可意指有一或多個其它元件被耦接或連接於該等被稱之為彼此耦接的元件之間。名詞“直接耦接”意指兩或多個元件直接接觸。
在各不同的實施例中，“第一特徵被形成、沉積、或以其它方式配置在第二特徵上”可意指第一特徵被形成、沉積、或配置在第二特徵之上，且至少部分的第一特徵與至少部分的第二特徵直接接觸(例如，直接物理及/或電接觸)或間接接觸(例如，第一特徵與第二特徵之間具有一或多個其它特徵)。
如本文中所使用的名詞“模組”，意指或包括提供所描述之功能的特殊用途積體電路(ASIC)、電子電路、系統單晶片(SoC)、執行一或多個軟體或韌體程式的處理器(共用、專用、或群組)及/或記憶體(共用、專用、或群組)、組合邏輯電路、及/或其它適組合組件，或以上這些的一部分。
圖1示意說明按照本發明之實施例之積體電路(IC)總成例的橫斷面視圖，其包括IC封裝102，與電路板116電及實體地耦接。在實施例中，IC封裝102包括一或多 個晶粒(例如，第一晶粒106)。第一晶粒106可至少部分嵌入在第一封裝層104中。第一晶粒106可包括複數個晶粒級的互連結構(例如，晶粒級互連結構108)，其配置在第一封裝層104的第一側。
IC封裝102也包括至少部分嵌入在第一封裝層104中的複數個電路由特徵(例如，電路由特徵110)。該複數個電路由特徵被組構成在第一封裝層104的第二側與配置在第二側之相對側之第一封裝層104的第一側之間路由電信號，如圖中所見。在某些實施例中，如圖之描繪，電路由特徵可以是形成在電性絕緣材料(例如，電性絕緣材料118)中的貫通孔柱。此電性絕緣材料包括矽、陶瓷、聚合物、或任何其它可被填充或不填充(例如，以氧化矽填料或其它適合的填料填充)的適合材料。
IC封裝102可進一步包括配置在第一封裝層104之第二側上，且至少部分嵌入在第二封裝層層120中的第二晶粒122。第二晶粒122也具有第二複數個晶粒級互連結構(例如，晶粒級互連結構124)。第二複數個晶粒級互連結構可藉由接合線(例如，接合線126)與電路由特徵電耦接。
在某些實施例中，IC封裝102可具有重佈層112。重佈層112被組構成藉由電路由特徵將晶粒106和晶粒122與一或多個封裝級互連結構(例如，焊球114)電耦接。封裝級互連結構可被組構成將IC封裝102與電路板116電性地並實體地耦接。IC封裝102可按照各種適合的組 構與電路板116耦接，包括彈性體組構或任何其它適合的組構。雖然本文是以焊球114來描繪，但封裝級互連結構可包括導電柱體或其它適合的結構來取代或附加於焊球114，經由配置在電路板116中的一或多個接墊(例如，接墊128)將IC封裝102與電路板116電耦接。IC封裝102可代表製造自半導體材料的獨立晶片，且在某些實施例中可包括處理器、記憶體、或ASIC，或其一部分。在某些實施例中，IC封裝102可以是嵌入式晶圓級球柵陣列(eWLB)封裝。
電路板116包括電路由特徵，被組構成路由往來於IC封裝102的電信號。電路由特徵例如包括配置在電路板之一或多個表面上的走線，及/或內部路由特徵，諸如，例如經由其路由電信號的溝、貫通孔、或其它互連結構
電路板116可以是由電性絕緣材料(諸如環氧樹脂疊層)所組成的印刷電路板(PCB)。例如，電路板116包括的電性絕緣材料可由例如聚四氟乙烯；酚醛棉紙材料，諸如Flame Retardant 4(FR-4)、FR-1；棉紙與環氧樹脂材料，諸如CEM-1或CEM-3；使用環氧樹脂預浸材料疊壓在一起的玻璃織物材料等組成。在其它實施例中，電路板116也可由其它適合的材料組成。在某些實施例中，電路板116可以是母板(例如，圖8的母板802)。
圖2係說明性的積體電路(IC)封裝製造程序200，用於製造按照本發明之各不同實施例的說明性IC封裝 (例如，圖1之IC封裝102)。圖3-4提供所選擇之操作的橫斷面視圖，用來說明IC封裝製造程序200中的各階段。因此，圖2-4將彼此連同來描述。為有助於此描述，圖2中所實施的操作，將參考圖3及4中之箭頭從一操作到另一操作。此外，並非所有符號都會用於說明圖3與4中所描繪的每一項操作，以儘量使這些圖不會過於複雜。
IC製造程序200於方塊202開始，在此，第一晶粒302的活性側與載體306耦接。此可經由使用膠帶或黏著劑(例如，黏著劑308)而配置在載體306上。如圖所描繪，晶粒302的活性側內可配置有複數個晶粒級的互連結構(例如，晶粒級互連結構304)。在某些實施例中，複數個電路由特徵312a-312d(在後文中統稱為電路由特徵312)也與載體306耦接。在此等實施例中，如圖所描繪，複數個電路由特徵可以是由形成在電性絕緣材料310a與310b中之貫通孔所構成的貫通孔柱。此電性絕緣材料可包括任何適合的材料，包括但不限於矽、陶瓷、聚合物、玻璃、等。在某些實施例中，電路由特徵可具有配置在電路由特徵312a-d之兩側的複數個接合墊314a-h。在某些實施例中，至少接合墊314a-d具有配置於其上之可打線結合的表面飾層。此可打線結合的表面飾層可包括鎳、金、或任何其它適合的材料或這些材料的組合。在其它實施例中，電路由特徵可在形成了第一封裝層316之後以分開的程序來形成，以下參考方塊204來討論。電路由特徵可包括任何導電材料(例如，銅)。
在方塊204，可沉積封裝材料以形成第一封裝層316。在某些實施例中，此封裝材料可以是模製化合物(例如，環氧樹脂)。在這些實施例中，第一封裝層316例如可經由壓模製程來形成。如圖之描繪，第一封裝層316可封裝至少部分的第一晶粒302與電路由特徵312。
在某些實施例中，第一封裝層316也封裝接合墊314a-d。在這些實施例中，在方塊206，可去除形成在接合墊314a-d上的任何封裝材料而致使空洞318a-d。此可藉由鑽孔(例如，雷射鑽孔)、研磨、蝕刻等來完成。在實施例中係利用雷射鑽孔，雷射鑽孔會破碎或破壞施加於接合墊314a-d之可打線結合的表面飾層。在這些實施例中，表面飾層(例如，鎳、金、或任何其它適合的表面飾層)可於雷射鑽孔之後再行施加。此表面飾層例如可經由無電電鍍處理來施加。
在方塊208，載體306可從第一封裝層316去耦。在某些實施例中，以上所討論的程序可與後文所描繪的程序分開實施。在這些實施例中，該程序可藉由提供類似經由上述製程所製造的IC封裝總成開始。在這些實施例中，可在IC封裝總成上沉積鈍化層以防止任何外露的金屬特徵被氧化或污染，諸如接合墊314a-h及第一晶粒302的複數個晶粒級互連結構。此鈍化層例如可被疊層、印刷、或旋塗。被施加此鈍化層之處，可在鈍化層中形成空洞(例如經由光刻製程)，以供下述程序使用。
在方塊210，形成介電層320。在某些實施例中，此 介電層可以是前文參考方塊208所討論的鈍化層。此外可在介電層320上形成重佈層(RDL)322。RDL 322可提供來自晶粒級互連(例如，晶粒級互連304)與電路由特徵312的信號分支。雖然在此所描繪的是單層RDL，但可理解，視符合最終IC封裝之應用與設計所需而定，也可形成額外的RDL與對應的介電層。在方塊212，前進到圖4，可形成並圖案化阻焊層324。此阻焊層例如經由光刻製程來形成。
在方塊214，第二晶粒326的背側可與RDL 322對側之第一封裝層316的第二側耦接。此例如可經由使用膠帶或黏著劑(例如，黏著劑328)來完成。在實施例中，第二晶粒326可具有複數個晶粒級互連330a-330d配置於其上。如本文中所使用，晶粒之背側係其內未配置有晶粒級互連的側。
在方塊216，第二晶粒326的晶粒級互連330a-330d可經由接合線332a-332d分別與電路由特徵312打線結合。電路由特徵312可在第二晶粒326與RDL之間路由電信號。接合線332a-d可包括任何適合的材料，包括但不限於鋁、銅、銀、金、等，且也可以是多層接合線(例如，電鍍)。此打線結合可經由任何習用的打線結合製程來形成。在某些實施例中，可在第二晶粒326的頂上堆疊一或多個額外的晶粒。在這些實施例中，在每一個晶粒與前一個晶粒之間可置放一間隔件以允許接合線(例如，接合線332a-d)的逸出。此實施例將在下文中參考圖7進一 步詳細討論。在方塊218，在第二晶粒326與接合線332a-d之上沉積額外的封裝材料，以形成第二封裝層334並用以保護打線結合組構。圖5-7描繪可由上述程序而形成的IC封裝的各種實施例。
圖5概示說明按照本發明之各種實施例之例示積體電路(IC)封裝500的橫斷面側視圖，其具有封裝級互連結構。如圖所描繪，圖5可將按前文參考圖2-4所描述之製程而製造的IC封裝總成當成它的起點。不過，在圖5中，封裝級互連(例如，焊球502)可配置在RDL上。雖然在此所描繪的是焊球，但封裝級互連結構可包括焊柱，或其它適合取代或除了焊球以外的結構。這些封裝級互連結構可被組構成將IC封裝500與電路板電耦接(例如，圖1的電路板116)。
圖6概示說明按照本發明之各種實施例之例示積體電路(IC)封裝600的橫斷面側視圖，其具有封裝級互連結構(例如，焊球606)及結合於其內的第三晶粒602。如圖所描繪，圖6可將按前文參考圖2-4所描述之製程而製造的IC封裝總成當成它的起點。不過，在圖6中，封裝級互連(例如，焊球606)已配置在RDL上。另外的第三晶粒602已藉由互連結構604與IC封裝總成耦接。雖然在此所描繪的是焊球，但封裝級互連結構可包括焊柱，或其它適合取代或除了焊球以外的結構。這些封裝級互連可被組構成將IC封裝600與電路板(例如，圖1的電路板116)電耦接。如圖中所見，第三晶粒602與互連結構 604的組合厚度小於單個封裝級互連結構的厚度。此使得第三晶粒602可與複數個封裝級互連結構位於相同的平面。
圖7概示說明按照本發明之各種實施例之例示積體電路(IC)封裝700的橫斷面側視圖，其具有堆疊於晶粒326之頂上的附加晶粒702。如圖所描繪，IC封裝700包括第一晶粒702及至少部分嵌入在第一封裝層716中的複數個電路由特徵(例如，電路由特徵712)。第一封裝層716例如是模製化合物。在某些實施例中，如圖所描繪，電路由特徵可以是形成在電性絕緣材料710a和710b中的貫通孔柱。此電性絕緣材料可包括任何適合的材料，包括但不限於矽、陶瓷、聚合物等。在某些實施例中，電路由特徵可具有配置在各個電路由特徵之兩端的複數個接合墊(例如，接合墊714)。在某些實施例中，頂部接合墊(例如，接合墊714)具有配置於其上之可打線結合的表面飾層。此可打線結合的表面飾層可包括鎳、金、或任何其它適合的材料或這些材料的組合。電路由特徵可包括任何導電材料(例如，銅)。
IC封裝700包括包括重佈層(RDL)722。RDL可配置在介電層720上，且可提供來自晶粒級互連(例如，晶粒級互連704)與複數個電路由特徵(例如，電路由特徵712)的信號分支。雖然在此描繪的是單層RDL，但可理解，視符合最終IC封裝之應用與設計所需而定，也可形成額外的RDL與對應的介電層。在RDL上可配置阻焊層 724，且在阻焊層724的開口中可配置複數個封裝級互連(例如，封裝級互連744)。
IC封裝700也包括第二晶粒726，其與第一封裝層716的一側耦接。此可經由使用膠帶或黏著劑(例如，黏著劑728)完成。在實施例中，第二晶粒726具有配置於其上的複數個晶粒級互連(例如，晶粒級互連730)。如圖之描繪，第二晶粒726的晶粒級互連可經由接合線732a-732d，經由複數個接合墊的對應子集與電路由特徵的第一子集打線結合。電路由特徵可在第二晶粒726與RDL 722之間路由電信號。接合線732a-d可包括任何適合的材料，包括但不限於鋁、銅、銀、金、等。此打線結合可經由任何習用的打線結合製程來形成。在某些實施例中，在第二晶粒726上可堆疊一或多個額外的晶粒(例如，第三晶粒736)。在這些實施例中，間隔件(例如，間隔件740)可置於毗鄰晶粒之間，以允許接合線(例如，接合線732a-d)從下方的晶粒逸出。在實施例中，第三晶粒736上可配置有複數個晶粒級互連(例如，晶粒級互連742)。如圖之描繪，第二晶粒726的晶粒級互連可經由接合線738a-738d，經由複數個對應的接合墊第二子集與電路由特徵的第二子集打線結合。第二晶粒726、第三晶粒736、及接合線732a-d和738a-d可全部嵌入在第二封裝層734中。在某些實施例中，第四晶粒可按與圖6中晶粒602與RDL耦接相類似的組構與RDL 722耦接。
本發明的實施例可在使用任何適合的硬體及/或軟體 按需要所組構成的系統中實施。圖8概示說明包括如本文所描述之IC封裝的計算裝置，諸如圖1-8所描繪。計算裝置800可容納一電路板，諸如主機板802。主機板802可包括若干組件，包括但不限於處理器804及至少一個通訊晶片806。處理器804可與主機板802實體並電耦接。在某些實施例中，該至少一個通訊晶片806也與主機板802實體且電耦接。在另些實施中，通訊晶片806可以是處理器804的一部分。
視其應用而定，計算裝置800可包括其它組件，這些組件可以也可以不與主機板802實體及電耦接。這些其它組件包括但不限於揮發性記憶體(例如，DRAM)、非揮發記憶體(例如，ROM)、快閃記憶體、圖形處理器、數位信號處理器、密碼處理器、晶片組、天線、顯示器、觸控螢幕顯示器、觸控螢幕控制器、電池、音頻編碼解碼器、視頻編碼解碼器、功率放大器、全球定位系統(GPS)裝置、羅盤、蓋格計數器、加速儀、陀螺儀、喇叭、照相機、及大量儲存裝置(諸如硬式磁碟機、光碟機(CD)、數位多功能光碟機(DVD)、等)。
通訊晶片806使往來於計算裝置800的資料傳輸能夠無線通訊。名詞“無線”及其衍生可用來描述電路、裝置、系統、方法、技術、通訊頻道等，其可通過使用經調變的電磁輻射經由非固態媒體傳遞資料。該名詞並非暗示相關的裝置不包含任何導線，雖然在某些實施例中的確不包含。通訊晶片806可實施任何種類的無線標準或協定，包 括但不限於電子電機工程師學會(IEEE)標準，包括Wi-Fi(IEEE 802.11系列)、IEEE 802.16標準(例如，IEEE 802.16-2005修正)、長程演進(LTE)計畫連同它的任何修正、更新、及/或修訂(例如，先進LTE計畫、超行動寬頻(UMB)計畫(也稱為“3GPP2”等)。IEEE 802.16相容的BWA網路通稱為WiMAX(全球互通微波接取(Worldwide Interoperability for Microwave Access)的縮寫)網路，其為通過IEEE 802.16標準之一致性與互通性測試之產品的合格標記。通訊晶片806可依照全球行動通訊系統(GSM)、通用封包無線電服務(General Packet Radio Service；GPRS)、通用行動電信系統(Universal Mobile Telecommunications System；UMTS)、高速封包存取(High Speed Packet Access；HSPA)、演進HSPA(E-HSPA)、或LTE網路來操作。通訊晶片806可依照GSM增強數據率演進(Enhanced Data for GSM Evolution；EDGE)、GSM EDGE無線電接取網路(GERAN)、全球地面無線電接取網路(UTRAN)、或演進UTRAN(E-UTRAN)來操作。通訊晶片806之操作可依照分碼多工存取(Code Division Multiple Access；CDMA)、分時多工存取(Time Division Multiple Access；TDMA)、數位增強無線通訊(Digital Enhanced Cordless Telecommunications；DECT)、資料優化演進(Evolution-Data Optimized；EV-DO)、及以上的衍生，以及名為3G、4G、5G或以上之任何其它的無線協定。在 其它實施例中，通訊晶片806可依照其它的無線協定操作。
計算裝置800可包括複數個通訊晶片806。例如，第一通訊晶片806可專用於短程無線通訊，諸如Wi-Fi與藍牙，及第二通訊晶片806可專用於長程無線通訊，諸如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO、及其它。
計算裝置800的處理器804可以是結合到IC總成中的IC封裝(例如，圖1的IC封裝102)。例如，圖1的電路板116可以是主機板802，而處理器804可以是IC封裝102的晶粒，如本文之描述。處理器804與主機板802可以使用本文所描述的封裝級互連耦接在一起。名詞“處理器”意指任何裝置或裝置的一部分，其可處理來自暫存器及/或記憶體的電子資料，並將該電子資料轉換成可儲存在暫存器及/或記憶體中的其它電子資料。
通訊晶片806可以是結合到包括封裝基板之IC總成中的IC封裝(例如，IC封裝102)。在另些實施中，安裝在計算裝置800中的其它組件(例如，記憶體裝置或其它積體電路裝置)可以是結合到IC總成中的IC封裝(例如，IC封裝102)。
在各種實施中，計算裝置800可以是膝上型電腦、聯網小電腦、筆記型電腦、超輕薄筆電、智慧型手機、平板電腦、個人數位助理(PDA)、超行動個人電腦、行動電話、桌上型電腦、伺服器、印表機、掃瞄器、監視器、機 上盒、娛樂控制器、數位式照相機、隨身聽、或數位式錄影機。在另些實施中，計算裝置800可以是用來處理資料的任何其它電子裝置。
例
本揭示描述若干按照各種實施的例子。例1包括積體電路(IC)封裝，其包含：至少部分嵌入在第一封裝層中的第一晶粒，第一晶粒具有第一複數個晶粒級互連結構，其係配置在第一封裝層的第一側；至少部分嵌入在第一封裝層中的複數個電路由特徵，且被組構成在第一封裝層的第一側與第一封裝層的第二側之間路由電信號，第二側係配置在第一側的相對側；以及，配置在第一封裝層之第二側上的第二晶粒，且至少部分嵌入在第二封裝層內，第二晶粒具有第二複數個晶粒級互連結構，其中，第二複數個晶粒級的互連結構係藉由接合線與至少複數個電路由特徵的子集電耦接。
例2包括例1之主題，進一步包含：配置在第一封裝層的第一側上的一或多個重佈層(RDL)，其中，一或多個RDL係與第一晶粒電耦接，且其中，一或多個RDL係經由複數個電路由特徵與第二晶粒電耦接。
例3包括例2之主題，進一步包含配置在一或多個RDL上的複數個封裝級互連結構。
例4包括例2之主題，進一步包含配置在一或多個重佈層上的第三晶粒，且具有與一或多個RDL電耦接的第 三複數個晶粒級互連結構。
例5包括例4之主題，進一步包含配置在一或多個RDL上的複數個封裝級互連結構，其中，第三晶粒與第三複數個晶粒級互連結構的組合厚度，小於複數個封裝級互連之個別封裝級互連結構的厚度，以使第三晶粒之配置能夠與複數個封裝級互連結構在相同平面中。
例6包括例1之主題，其中，複數個電路由特徵的子集係第一子集，IC封裝進一步包含：至少部分嵌入在第二封裝層中的第三晶粒，且具有第三複數個晶粒級互連結構，藉由接合線與複數個電路由特徵的第二子集電耦接，其中，第三晶粒與第二晶粒係經由間隔件耦接在一起。
例7包括例1-6之任一例的主題，其中，複數個電路由特徵包含貫通孔柱。
例8包括例1-6之任一例的主題，其中，IC封裝係嵌入式晶圓級球柵陣列(eWLB)封裝。
例9包括形成積體電路(IC)封裝方法，包含：提供具有至少部分嵌入於其內的第一晶粒和複數個電路由特徵的第一封裝層，第一晶粒具有配置在第一封裝層之第一側的第一複數個晶粒級互連結構，其中，電路由特徵電耦接第一封裝層的第一側與第一封裝層的第二側，且其中，第一封裝層的第一側係配置在第一封裝層的第二側的相對側；耦接第二晶粒與第一封裝層的第二側，其中，第二晶粒包括第二複數個晶粒級的互連結構；藉由接合線來電耦接第二複數個晶粒級互連結構與至少複數個電路由特徵的 子集；以及，在第二晶粒與打線結合組構之上形成第二封裝層，以封裝第二封裝層中的至少部分第二晶粒與打線結合組構。
例10包括例9之主題，其中，提供第一封裝層包含：耦接第一晶粒與載體；耦接複數個電路由特徵與載體；以及，在第一晶粒與複數個電路由特徵之上沉積封裝材料，以形成第一封裝層。
例11包括例9之主題，其中，提供第一封裝層包含：耦接第一晶粒與載體；在第一晶粒之上沉積封裝材料，以形成第一封裝層；以及，在封裝材料中形成複數個電路由特徵。
例12包括例9之主題，進一步包含：在第一封裝層的第一側上形成一或多個重佈層(RDL)，其中，一或多個RDL係與第一晶粒電耦接，且其中，一或多個RDL係藉由複數個電路由特徵與第二晶粒電耦接。
例13包括例12之主題，進一步包含：在一或多個RDL上形成複數個封裝級互連。
例14包括例12之主題，進一步包含：經由沉積在第三晶粒上的第三複數個晶粒級互連結構將第三晶粒電耦接至一或多個RDL。
例15包括例14之主題，進一步包含在一或多個RDL上形成複數個封裝級互連結構，其中，第三晶粒與第三複數個晶粒級互連結構的組合厚度，小於複數個封裝級互連 之個別封裝級互連結構的厚度，以使第三晶粒的配置能夠與複數個封裝級互連結構在相同平面中。
例16包括例9之主題，其中，複數個電路由特徵之子集係第一子集，且接合線係第一接合線，IC封裝進一步包含：經由間隔件將具有第三複數個晶粒級互連結構的第三晶粒實體地耦接至第二晶粒的表面；以及，藉由第二接合線將第三複數個晶粒級互連結構與複數個電路由特徵的第二子集耦接，其中，形成第二封裝層以封裝第三晶粒。
例17包括例9-16之任一例的主題，其中，複數個電路由特徵包含貫通孔柱。
例18包括例9-16之任一例的主題，其中，IC封裝係嵌入式晶圓級球柵陣列(eWLB)封裝。
例19包括的積體電路(IC)總成，包含：IC封裝，包括：至少部分係嵌入在第一封裝層中的第一晶粒，第一晶粒具有第一複數個晶粒級的互連結構，其配置在第一封裝層的第一側；至少部分係嵌入在第一封裝層中的複數個電路由特徵，且被組構成在第一封裝層的第一側與第一封裝層的第二側之間路由電信號，第二側係配置在第一側的相對側；配置在第一封裝層之第二側上的第二晶粒，且至少部分嵌入在第二封裝層內，第二晶粒具有第二複數個晶粒級的互連結構，其中，第二複數個晶粒級的互連結構係藉由接合線與至少複數個電路由特徵的子集耦接；以及，配置在第一封裝層之第一側上的複數個封裝級互連，且經 由複數個電路由特徵與第二複數個晶粒級互連結構及第一複數個晶粒級互連結構電耦接；以及，電路板，具有配置於其內的複數個電路由特徵和配置其上的複數個接墊，其中，複數個接墊係與複數個封裝級互連結構電耦接。
例20包括例19的主題，其中，IC封裝包括處理器。
例21包括例20的主題，進一步包含天線、顯示器、觸控螢幕顯示器、觸控螢幕控制器、電池、音頻編碼解碼器、視頻編碼解碼器、功率放大器、全球定位系統(GPS)裝置、羅盤、蓋格計數器、加速儀、陀螺儀、喇叭、照相機的一或多個與電路板耦接。
例22包括例19-21之任一例的主題，其中，IC總成係膝上型電腦、聯網小電腦、筆記型電腦、超輕薄筆電、智慧型手機、平板電腦、個人數位助理(PDA)、超行動個人電腦、行動電話、桌上型電腦、伺服器、印表機、掃瞄器、監視器、機上盒、娛樂控制器、數位式照相機、隨身聽、或數位式錄影機。
各種實施例可包括上述實施例之任何適合的組合，包括前文以連結形式(及)所描述的那些實施例的替代(或)實施例(例如，"及"或許"及/或")。此外，某些實施例可包括製造的一或多個物件(例如，非暫時性電腦可讀取媒體)，其上儲存有指令，該等指令當被執行時，導致上述任何實施例的動作。此外，某些實施例可包括具有用以執行上述實施例之各種操作之任何適合機構的設備或 系統。
以上所描述的說明性實施，包括摘要中的描述，並無意窮舉本發明的實施例或將實施例限制在與揭示絲毫不差的形式。雖然為了說明之目的本文描述了特定的實施與例子，但如熟悉相關領域之技藝者所瞭解，在本發明的範圍內可有各種相等的修改。
由於上的詳細描述，可做到對本發明之實施例的這些修改。以下申請專利範圍中所使用的名詞不應被解釋成將本發明的各種實施例限制到說明書與申請專利範圍中所揭示的特定實施。反之，發明的範圍係完全由以下申請專利範圍所決定，其按照申請專利範圍詮釋所建立之文件來解釋。
100‧‧‧積體電路總成
102‧‧‧IC封裝
104‧‧‧第一封裝層
106‧‧‧第一晶粒
108‧‧‧晶粒級互連結構
110‧‧‧電路由部件
112‧‧‧重佈層
114‧‧‧焊球
116‧‧‧電路板
118‧‧‧電性絕緣材料
120‧‧‧第二封裝層
122‧‧‧第二晶粒
124‧‧‧晶粒級互連結構
126‧‧‧引線
128‧‧‧接墊

Claims (22)

  1. 一種積體電路(IC)封裝，包含：第一晶粒，至少部分嵌入在第一封裝層中，該第一晶粒具有第一複數個晶粒級的互連結構，其係配置在該第一封裝層的第一側；複數個電路由特徵，至少部分嵌入在該第一封裝層中，且被組構成在該第一封裝層的該第一側與該第一封裝層的第二側之間路由電信號，該第二側係配置在該第一側的相對側；以及第二晶粒，係配置在該第一封裝層之該第二側上，且至少部分嵌入在該第二封裝層內，該第二晶粒具有第二複數個晶粒級的互連結構，其中，該第二複數個晶粒級的互連結構係藉由接合線與至少該複數個電路由特徵的子集電耦接。
  2. 如申請專利範圍第1項的IC封裝，進一步包含：一或多個重佈層(RDL)，係配置在該第一封裝層的該第一側上，其中，該一或多個重佈層係與該第一晶粒電耦接，且其中，該一或多個重佈層係經由該複數個電路由特徵與該第二晶粒電耦接。
  3. 如申請專利範圍第2項的IC封裝，進一步包含配置在該一或多個重佈層上的複數個封裝級互連結構。
  4. 如申請專利範圍第2項的IC封裝，進一步包含第三晶粒，係配置在該一或多個重佈層上，且具有與該一或多個重佈層電耦接的第三複數個晶粒級互連結構。
  5. 如申請專利範圍第4項的IC封裝，進一步包含配置在該一或多個重佈層上的複數個封裝級互連結構，其中，該第三晶粒與該第三複數個晶粒級互連結構的組合厚度，小於該複數個封裝級互連之該個別封裝級互連結構的厚度，以使該第三晶粒之該配置能夠與該複數個封裝級互連結構在相同平面中。
  6. 如申請專利範圍第1項的IC封裝，其中，該複數個電路由特徵的該子集係第一子集，該IC封裝進一步包含：第三晶粒，至少部分嵌入在該第二封裝層中，且具有第三複數個晶粒級互連結構，藉由接合線與該複數個該電路由特徵的第二子集電耦接，其中，該第三晶粒與該第二晶粒係經由間隔件耦接在一起。
  7. 如申請專利範圍第1項的IC封裝，其中，該複數個電路由特徵包含貫通孔柱。
  8. 如申請專利範圍第1項的IC封裝，其中，該IC封裝係嵌入式晶圓級球柵陣列(eWLB)封裝。
  9. 一種形成積體電路(IC)封裝方法，包含：提供第一封裝層，該第一封裝層具有至少部分嵌入於其內的第一晶粒和複數個電路由特徵，該第一晶粒具有配置在該第一封裝層之第一側的第一複數個晶粒級互連結構，其中，該電路由特徵電耦接該第一封裝層的該第一側與該第一封裝層的該第二側，且其中，該第一封裝層的該第一側係配置在該第一封裝層的該第二側的相對側； 耦接第二晶粒與該第一封裝層的第二側，其中，該第二晶粒包括第二複數個晶粒級的互連結構；藉由接合線來電耦接該第二複數個晶粒級互連結構與至少該複數個電路由特徵的子集；以及在該第二晶粒與該打線結合組構之上形成第二封裝層，以封裝該第二封裝層中的至少部分該第二晶粒與該打線結合組構。
  10. 如申請專利範圍第9項的方法，其中，提供該第一封裝層包含：耦接該第一晶粒與載體；耦接該複數個電路由特徵與該載體；以及在該第一晶粒與該複數個電路由特徵之上沉積封裝材料，以形成該第一封裝層。
  11. 如申請專利範圍第9項的方法，其中，提供該第一封裝層包含：耦接該第一晶粒與載體；在該第一晶粒之上沉積封裝材料，以形成該第一封裝層；以及在該封裝材料中形成該複數個電路由特徵。
  12. 如申請專利範圍第9項的方法，進一步包含：在該第一封裝層的該第一側上形成一或多個重佈層(RDL)，其中，該一或多個重佈層係與該第一晶粒電耦接，且其中，該一或多個重佈層係藉由該複數個電路由特徵與該第二晶粒電耦接。
  13. 如申請專利範圍第12項的方法，進一步包含：在該一或多個重佈層上形成複數個封裝級互連。
  14. 如申請專利範圍第12項的方法，進一步包含：經由沉積在第三晶粒上的第三複數個晶粒級互連結構將該第三晶粒電耦接至該一或多個重佈層。
  15. 如申請專利範圍第14項的方法，進一步包含在該一或多個重佈層上形成複數個封裝級互連結構，其中，該第三晶粒與該第三複數個晶粒級互連結構的組合厚度，小於該複數個封裝級互連之該個別封裝級互連結構的厚度，以使該第三晶粒的該配置能夠與該複數個封裝級互連結構在相同平面中。
  16. 如申請專利範圍第9項的方法，其中，該複數個電路由特徵之該子集係第一子集，且該接合線係第一接合線，該IC封裝進一步包含：經由間隔件將具有第三複數個晶粒級互連結構的第三晶粒實體地耦接至該第二晶粒的表面；以及藉由第二接合線將該第三複數個晶粒級互連結構與該複數個電路由特徵的第二子集耦接，其中，形成該第二封裝層以封裝該第三晶粒。
  17. 如申請專利範圍第9項的方法，其中，該複數個電路由特徵包含貫通孔柱。
  18. 如申請專利範圍第9項的方法，其中，該IC封裝係嵌入式晶圓級球柵陣列(eWLB)封裝。
  19. 一種積體電路(IC)總成，包含： IC封裝，包括：第一晶粒，至少部分係嵌入在第一封裝層中，該第一晶粒具有第一複數個晶粒級的互連結構，其配置在該第一封裝層的第一側；複數個電路由特徵，至少部分係嵌入在該第一封裝層中，且被組構成在該第一封裝層的該第一側與該第一封裝層的第二側之間路由電信號，該第二側係配置在該第一側的相對側；第二晶粒，係配置在該第一封裝層的該第二側上，且至少部分係嵌入在該第二封裝層內，該第二晶粒具有第二複數個晶粒級的互連結構，其中，該第二複數個晶粒級的互連結構係藉由接合線與至少該複數個電路由特徵的子集耦接；以及複數個封裝級互連，係配置在該第一封裝層的該第一側上，且經由該複數個電路由特徵與該第二複數個晶粒級互連結構及該第一複數個晶粒級互連結構電耦接；以及電路板，具有配置於其內的複數個電路由特徵和配置其上的複數個接墊，其中，該複數個接墊係與該複數個封裝級互連結構電耦接。
  20. 如申請專利範圍第19項的IC總成，其中，該IC封裝包括處理器。
  21. 如申請專利範圍第20項的IC總成，進一步包含天線、顯示器、觸控螢幕顯示器、觸控螢幕控制器、電 池、音頻編碼解碼器、視頻編碼解碼器、功率放大器、全球定位系統(GPS)裝置、羅盤、蓋格計數器、加速儀、陀螺儀、喇叭、照相機的一或多個與該電路板耦接。
  22. 如申請專利範圍第19項的IC總成，其中，該IC總成係膝上型電腦、聯網小電腦、筆記型電腦、超輕薄筆電、智慧型手機、平板電腦、個人數位助理(PDA)、超行動個人電腦、行動電話、桌上型電腦、伺服器、印表機、掃瞄器、監視器、機上盒、娛樂控制器、數位式照相機、隨身聽、或數位式錄影機。
TW104127511A 2014-09-26 2015-08-24 具有打線結合的多晶粒堆疊的積體電路封裝 TWI657557B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
PCT/US2014/057781 WO2016048363A1 (en) 2014-09-26 2014-09-26 Integrated circuit package having wire-bonded multi-die stack
??PCT/US14/57781 2014-09-26

Publications (2)

Publication Number Publication Date
TW201620106A true TW201620106A (zh) 2016-06-01
TWI657557B TWI657557B (zh) 2019-04-21

Family

ID=55581679

Family Applications (2)

Application Number Title Priority Date Filing Date
TW104127511A TWI657557B (zh) 2014-09-26 2015-08-24 具有打線結合的多晶粒堆疊的積體電路封裝
TW107119364A TWI732123B (zh) 2014-09-26 2015-08-24 具有打線結合的多晶粒堆疊的積體電路封裝

Family Applications After (1)

Application Number Title Priority Date Filing Date
TW107119364A TWI732123B (zh) 2014-09-26 2015-08-24 具有打線結合的多晶粒堆疊的積體電路封裝

Country Status (9)

Country Link
US (4) US9972601B2 (zh)
EP (3) EP4510174A2 (zh)
JP (1) JP2016535462A (zh)
KR (2) KR20160047424A (zh)
CN (2) CN105659381A (zh)
MY (1) MY199192A (zh)
RU (1) RU2663688C1 (zh)
TW (2) TWI657557B (zh)
WO (1) WO2016048363A1 (zh)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI633635B (zh) * 2017-07-10 2018-08-21 台星科股份有限公司 可提升空間使用率的堆疊式晶片封裝結構及其封裝方法
US10340259B2 (en) 2015-05-14 2019-07-02 Mediatek Inc. Method for fabricating a semiconductor package
US10593568B2 (en) 2017-08-24 2020-03-17 Micron Technology, Inc. Thrumold post package with reverse build up hybrid additive structure
US10685943B2 (en) 2015-05-14 2020-06-16 Mediatek Inc. Semiconductor chip package with resilient conductive paste post and fabrication method thereof
TWI710079B (zh) * 2017-08-24 2020-11-11 美商美光科技公司 使用導線接合之混合式添加結構之可堆疊記憶體晶粒
US11037910B2 (en) 2017-08-24 2021-06-15 Micron Technology, Inc. Semiconductor device having laterally offset stacked semiconductor dies
TWI780876B (zh) * 2021-08-25 2022-10-11 旭德科技股份有限公司 封裝載板及封裝結構

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160083977A (ko) * 2015-01-02 2016-07-13 삼성전자주식회사 반도체 패키지
KR102065943B1 (ko) * 2015-04-17 2020-01-14 삼성전자주식회사 팬-아웃 반도체 패키지 및 그 제조 방법
WO2017111789A1 (en) * 2015-12-23 2017-06-29 Intel IP Corporation Eplb/ewlb based pop for hbm or customized package stack
US10204870B2 (en) * 2016-04-28 2019-02-12 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of manufacturing the same
KR101994748B1 (ko) * 2016-09-12 2019-07-01 삼성전기주식회사 팬-아웃 반도체 패키지
US20180090467A1 (en) * 2016-09-27 2018-03-29 Intel Corporation Package with thermal coupling
DE112016007561T5 (de) * 2016-12-31 2019-10-02 Intel Corporation Elektronisches bauelementgehäuse
US10541153B2 (en) * 2017-08-03 2020-01-21 General Electric Company Electronics package with integrated interconnect structure and method of manufacturing thereof
US10804115B2 (en) * 2017-08-03 2020-10-13 General Electric Company Electronics package with integrated interconnect structure and method of manufacturing thereof
US10541209B2 (en) * 2017-08-03 2020-01-21 General Electric Company Electronics package including integrated electromagnetic interference shield and method of manufacturing thereof
US10622270B2 (en) 2017-08-31 2020-04-14 Texas Instruments Incorporated Integrated circuit package with stress directing material
US10553573B2 (en) 2017-09-01 2020-02-04 Texas Instruments Incorporated Self-assembly of semiconductor die onto a leadframe using magnetic fields
US10833648B2 (en) 2017-10-24 2020-11-10 Texas Instruments Incorporated Acoustic management in integrated circuit using phononic bandgap structure
US10886187B2 (en) 2017-10-24 2021-01-05 Texas Instruments Incorporated Thermal management in integrated circuit using phononic bandgap structure
US10497651B2 (en) 2017-10-31 2019-12-03 Texas Instruments Incorporated Electromagnetic interference shield within integrated circuit encapsulation using photonic bandgap structure
US10444432B2 (en) 2017-10-31 2019-10-15 Texas Instruments Incorporated Galvanic signal path isolation in an encapsulated package using a photonic structure
US10557754B2 (en) 2017-10-31 2020-02-11 Texas Instruments Incorporated Spectrometry in integrated circuit using a photonic bandgap structure
US10371891B2 (en) 2017-10-31 2019-08-06 Texas Instruments Incorporated Integrated circuit with dielectric waveguide connector using photonic bandgap structure
US20190164948A1 (en) * 2017-11-27 2019-05-30 Powertech Technology Inc. Package structure and manufacturing method thereof
KR20190121560A (ko) 2018-04-18 2019-10-28 삼성전기주식회사 팬-아웃 반도체 패키지
US10790162B2 (en) * 2018-09-27 2020-09-29 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
DE102019117844A1 (de) 2018-09-27 2020-04-02 Taiwan Semiconductor Manufacturing Co., Ltd. Integrierte-schaltung-package und verfahren
KR102769623B1 (ko) 2018-11-27 2025-02-19 삼성전자주식회사 반도체 패키지
KR102735628B1 (ko) * 2018-12-19 2024-12-02 삼성전자주식회사 반도체 패키지의 제조방법
RU2705229C1 (ru) * 2019-03-05 2019-11-06 Федеральное государственное бюджетное образовательное учреждение высшего образования "Петрозаводский государственный университет" Способ трехмерного многокристального корпусирования интегральных микросхем памяти
KR20210026539A (ko) 2019-08-30 2021-03-10 삼성전자주식회사 디스플레이 모듈 패키지
SG10201908828WA (en) * 2019-09-23 2021-04-29 Apple Inc Embedded Packaging Concepts for Integration of ASICs and Optical Components
KR102573573B1 (ko) 2019-10-25 2023-09-01 삼성전자주식회사 반도체 패키지
US11855124B2 (en) * 2019-11-15 2023-12-26 Qualcomm Incorporated Vertically integrated device stack including system on chip and power management integrated circuit
KR102766435B1 (ko) 2020-02-17 2025-02-12 삼성전자주식회사 반도체 패키지
KR102765266B1 (ko) 2020-02-25 2025-02-07 삼성전자주식회사 반도체 패키지 및 반도체 패키지의 제조 방법
US11521959B2 (en) 2020-03-12 2022-12-06 Taiwan Semiconductor Manufacturing Co., Ltd. Die stacking structure and method forming same
DE102020119293A1 (de) 2020-03-12 2021-09-16 Taiwan Semiconductor Manufacturing Co., Ltd. Die-stapelstruktur und verfahren zum bilden derselben
KR20210137275A (ko) * 2020-05-07 2021-11-17 삼성전자주식회사 반도체 패키지 및 그의 제조 방법
US11222710B1 (en) 2020-08-10 2022-01-11 Micron Technology, Inc. Memory dice arrangement based on signal distribution
KR20220086917A (ko) * 2020-12-17 2022-06-24 엘지디스플레이 주식회사 발광 표시 장치와 이를 이용한 멀티 스크린 표시 장치
CN112366142A (zh) * 2021-01-14 2021-02-12 广东佛智芯微电子技术研究有限公司 一种降低打引线高度的芯片封装方法及其封装结构
US20230088170A1 (en) * 2021-09-21 2023-03-23 Intel Corporation Microelectronic assemblies including solder and non-solder interconnects

Family Cites Families (70)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002270762A (ja) * 2001-03-09 2002-09-20 Sony Corp 半導体装置
DE10224124A1 (de) * 2002-05-29 2003-12-18 Infineon Technologies Ag Elektronisches Bauteil mit äußeren Flächenkontakten und Verfahren zu seiner Herstellung
US6825064B2 (en) * 2002-09-30 2004-11-30 Ultratera Corporation Multi-chip semiconductor package and fabrication method thereof
DE102004022884B4 (de) * 2004-05-06 2007-07-19 Infineon Technologies Ag Halbleiterbauteil mit einem Umverdrahtungssubstrat und Verfahren zur Herstellung desselben
US8095073B2 (en) * 2004-06-22 2012-01-10 Sony Ericsson Mobile Communications Ab Method and apparatus for improved mobile station and hearing aid compatibility
US7279786B2 (en) * 2005-02-04 2007-10-09 Stats Chippac Ltd. Nested integrated circuit package on package system
US7163839B2 (en) * 2005-04-27 2007-01-16 Spansion Llc Multi-chip module and method of manufacture
US8586413B2 (en) * 2005-05-04 2013-11-19 Spansion Llc Multi-chip module having a support structure and method of manufacture
US8067831B2 (en) * 2005-09-16 2011-11-29 Stats Chippac Ltd. Integrated circuit package system with planar interconnects
US8810018B2 (en) * 2006-02-03 2014-08-19 Stats Chippac Ltd. Stacked integrated circuit package system with face to face stack configuration
TWI296148B (en) * 2006-04-28 2008-04-21 Advanced Semiconductor Eng Stackable semiconductor package and the method for making the same
JP2008166440A (ja) * 2006-12-27 2008-07-17 Spansion Llc 半導体装置
JP5075463B2 (ja) * 2007-04-19 2012-11-21 ルネサスエレクトロニクス株式会社 半導体装置
JP2007251197A (ja) 2007-05-15 2007-09-27 Hitachi Chem Co Ltd 半導体装置の製造方法
US7863088B2 (en) * 2007-05-16 2011-01-04 Infineon Technologies Ag Semiconductor device including covering a semiconductor with a molding compound and forming a through hole in the molding compound
US7741194B2 (en) * 2008-01-04 2010-06-22 Freescale Semiconductor, Inc. Removable layer manufacturing method
US9236319B2 (en) * 2008-02-29 2016-01-12 Stats Chippac Ltd. Stacked integrated circuit package system
US8039303B2 (en) 2008-06-11 2011-10-18 Stats Chippac, Ltd. Method of forming stress relief layer between die and interconnect structure
US7969009B2 (en) 2008-06-30 2011-06-28 Qualcomm Incorporated Through silicon via bridge interconnect
US7750455B2 (en) * 2008-08-08 2010-07-06 Stats Chippac Ltd. Triple tier package on package system
US7989950B2 (en) * 2008-08-14 2011-08-02 Stats Chippac Ltd. Integrated circuit packaging system having a cavity
US8043894B2 (en) * 2008-08-26 2011-10-25 Stats Chippac Ltd. Integrated circuit package system with redistribution layer
US7982305B1 (en) * 2008-10-20 2011-07-19 Maxim Integrated Products, Inc. Integrated circuit package including a three-dimensional fan-out / fan-in signal routing
US7838337B2 (en) * 2008-12-01 2010-11-23 Stats Chippac, Ltd. Semiconductor device and method of forming an interposer package with through silicon vias
US8354304B2 (en) * 2008-12-05 2013-01-15 Stats Chippac, Ltd. Semiconductor device and method of forming conductive posts embedded in photosensitive encapsulant
US9064936B2 (en) * 2008-12-12 2015-06-23 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
US8592992B2 (en) * 2011-12-14 2013-11-26 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect structure with conductive micro via array for 3-D Fo-WLCSP
TWI499024B (zh) * 2009-01-07 2015-09-01 Advanced Semiconductor Eng 堆疊式多封裝構造裝置、半導體封裝構造及其製造方法
JP5188426B2 (ja) 2009-03-13 2013-04-24 新光電気工業株式会社 半導体装置及びその製造方法、電子装置
JP2010245107A (ja) * 2009-04-01 2010-10-28 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
US8021930B2 (en) * 2009-08-12 2011-09-20 Stats Chippac, Ltd. Semiconductor device and method of forming dam material around periphery of die to reduce warpage
US9875911B2 (en) * 2009-09-23 2018-01-23 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming interposer with opening to contain semiconductor die
US8508954B2 (en) * 2009-12-17 2013-08-13 Samsung Electronics Co., Ltd. Systems employing a stacked semiconductor package
KR20110085481A (ko) * 2010-01-20 2011-07-27 삼성전자주식회사 적층 반도체 패키지
US8138014B2 (en) 2010-01-29 2012-03-20 Stats Chippac, Ltd. Method of forming thin profile WLCSP with vertical interconnect over package footprint
JP5437111B2 (ja) * 2010-03-01 2014-03-12 日東電工株式会社 ダイボンドフィルム、ダイシング・ダイボンドフィルム及び半導体装置
JP2011187668A (ja) 2010-03-08 2011-09-22 Toshiba Corp 半導体装置
US8264849B2 (en) * 2010-06-23 2012-09-11 Intel Corporation Mold compounds in improved embedded-die coreless substrates, and processes of forming same
KR20120007840A (ko) * 2010-07-15 2012-01-25 삼성전자주식회사 두 개의 패키지 기판 사이에 배치된 스페이서를 가진 ｐｏｐ 반도체 패키지
US8304900B2 (en) * 2010-08-11 2012-11-06 Stats Chippac Ltd. Integrated circuit packaging system with stacked lead and method of manufacture thereof
US8343810B2 (en) * 2010-08-16 2013-01-01 Stats Chippac, Ltd. Semiconductor device and method of forming Fo-WLCSP having conductive layers and conductive vias separated by polymer layers
US8466567B2 (en) * 2010-09-16 2013-06-18 Stats Chippac Ltd. Integrated circuit packaging system with stack interconnect and method of manufacture thereof
DE102010041129A1 (de) * 2010-09-21 2012-03-22 Robert Bosch Gmbh Multifunktionssensor als PoP-mWLP
KR101711045B1 (ko) * 2010-12-02 2017-03-02 삼성전자 주식회사 적층 패키지 구조물
KR20120062366A (ko) * 2010-12-06 2012-06-14 삼성전자주식회사 멀티칩 패키지의 제조 방법
KR101828386B1 (ko) * 2011-02-15 2018-02-13 삼성전자주식회사 스택 패키지 및 그의 제조 방법
JP2012248754A (ja) * 2011-05-30 2012-12-13 Lapis Semiconductor Co Ltd 半導体装置の製造方法、及び半導体装置
US8710668B2 (en) * 2011-06-17 2014-04-29 Stats Chippac Ltd. Integrated circuit packaging system with laser hole and method of manufacture thereof
KR20130015393A (ko) 2011-08-03 2013-02-14 하나 마이크론(주) 반도체 패키지 및 이의 제조 방법
JP5864180B2 (ja) * 2011-09-21 2016-02-17 新光電気工業株式会社 半導体パッケージ及びその製造方法
US8698297B2 (en) * 2011-09-23 2014-04-15 Stats Chippac Ltd. Integrated circuit packaging system with stack device
US9123763B2 (en) 2011-10-12 2015-09-01 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package (PoP) structure having at least one package comprising one die being disposed in a core material between first and second surfaces of the core material
KR101874803B1 (ko) * 2012-01-20 2018-08-03 삼성전자주식회사 패키지 온 패키지 구조체
KR101798571B1 (ko) 2012-02-16 2017-11-16 삼성전자주식회사 반도체 패키지
US9418947B2 (en) * 2012-02-27 2016-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming connectors with a molding compound for package on package
US9842798B2 (en) * 2012-03-23 2017-12-12 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a PoP device with embedded vertical interconnect units
US8810024B2 (en) * 2012-03-23 2014-08-19 Stats Chippac Ltd. Semiconductor method and device of forming a fan-out PoP device with PWB vertical interconnect units
DE112013002672T5 (de) * 2012-05-25 2015-03-19 Nepes Co., Ltd Halbleitergehäuse, Verfahren zum Herstellen desselben und Gehäuse auf Gehäuse
KR101362715B1 (ko) * 2012-05-25 2014-02-13 주식회사 네패스 반도체 패키지, 그 제조 방법 및 패키지 온 패키지
KR101947722B1 (ko) * 2012-06-07 2019-04-25 삼성전자주식회사 적층 반도체 패키지 및 이의 제조방법
US9281292B2 (en) * 2012-06-25 2016-03-08 Intel Corporation Single layer low cost wafer level packaging for SFF SiP
US20140035935A1 (en) * 2012-08-03 2014-02-06 Qualcomm Mems Technologies, Inc. Passives via bar
US9368438B2 (en) * 2012-12-28 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package (PoP) bonding structures
US8963318B2 (en) * 2013-02-28 2015-02-24 Freescale Semiconductor, Inc. Packaged semiconductor device
US9484327B2 (en) * 2013-03-15 2016-11-01 Qualcomm Incorporated Package-on-package structure with reduced height
US8669140B1 (en) * 2013-04-04 2014-03-11 Freescale Semiconductor, Inc. Method of forming stacked die package using redistributed chip packaging
JP6163363B2 (ja) * 2013-06-14 2017-07-12 日本発條株式会社 ディスク装置用サスペンション
US9472533B2 (en) * 2013-11-20 2016-10-18 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming wire bondable fan-out EWLB package
US9527723B2 (en) * 2014-03-13 2016-12-27 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming microelectromechanical systems (MEMS) package
US10153175B2 (en) * 2015-02-13 2018-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. Metal oxide layered structure and methods of forming the same

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10340259B2 (en) 2015-05-14 2019-07-02 Mediatek Inc. Method for fabricating a semiconductor package
US10685943B2 (en) 2015-05-14 2020-06-16 Mediatek Inc. Semiconductor chip package with resilient conductive paste post and fabrication method thereof
TWI633635B (zh) * 2017-07-10 2018-08-21 台星科股份有限公司 可提升空間使用率的堆疊式晶片封裝結構及其封裝方法
US10593568B2 (en) 2017-08-24 2020-03-17 Micron Technology, Inc. Thrumold post package with reverse build up hybrid additive structure
TWI710079B (zh) * 2017-08-24 2020-11-11 美商美光科技公司 使用導線接合之混合式添加結構之可堆疊記憶體晶粒
US11037910B2 (en) 2017-08-24 2021-06-15 Micron Technology, Inc. Semiconductor device having laterally offset stacked semiconductor dies
US11929349B2 (en) 2017-08-24 2024-03-12 Micron Technology, Inc. Semiconductor device having laterally offset stacked semiconductor dies
TWI780876B (zh) * 2021-08-25 2022-10-11 旭德科技股份有限公司 封裝載板及封裝結構

Also Published As

Publication number Publication date
RU2663688C1 (ru) 2018-08-08
US20230023328A1 (en) 2023-01-26
TW201843792A (zh) 2018-12-16
CN108807200A (zh) 2018-11-13
US10249598B2 (en) 2019-04-02
US9972601B2 (en) 2018-05-15
EP3198644A1 (en) 2017-08-02
US20180197840A1 (en) 2018-07-12
EP4163956A2 (en) 2023-04-12
CN105659381A (zh) 2016-06-08
KR102165024B1 (ko) 2020-10-13
WO2016048363A1 (en) 2016-03-31
MY199192A (en) 2023-10-19
US20180315737A1 (en) 2018-11-01
TWI657557B (zh) 2019-04-21
KR20170081706A (ko) 2017-07-12
EP4510174A2 (en) 2025-02-19
JP2016535462A (ja) 2016-11-10
TWI732123B (zh) 2021-07-01
US20160276311A1 (en) 2016-09-22
KR20160047424A (ko) 2016-05-02
EP4163956A3 (en) 2023-06-28
EP3198644A4 (en) 2018-05-23
US12237305B2 (en) 2025-02-25

Similar Documents

Publication Publication Date Title
US12237305B2 (en) Integrated circuit package having wirebonded multi-die stack
JP7282794B2 (ja) 小型電子アセンブリ
TWI673843B (zh) 具有後端被動元件的積體電路晶粒及相關方法
KR101938949B1 (ko) 패키지 온 패키지 아키텍처 및 그 제조 방법
CN107004668B (zh) 用于串扰缓解的接地过孔群集
TWI600114B (zh) 橋接互連、製造橋接互連的方法及封裝組合
US9202803B2 (en) Laser cavity formation for embedded dies or components in substrate build-up layers
US9455218B2 (en) Embedded die-down package-on-package device
TWI727947B (zh) 用於堆疊式封裝之帶有凹入式傳導接點的積體電路結構
US9159714B2 (en) Package on wide I/O silicon
TWI614847B (zh) 可縮放之封裝體架構與相關聯技術及組態
TWI585931B (zh) 用於多晶粒之封裝總成組態及相關技術
TW201705401A (zh) 多層封裝技術
US10879152B2 (en) Through mold via (TMV) using stacked modular mold rings
US20130313727A1 (en) Multi-stacked bbul package