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TW201606937A - 接觸結構及其形成方法 - Google Patents

接觸結構及其形成方法 Download PDF

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TW201606937A
TW201606937A TW104121440A TW104121440A TW201606937A TW 201606937 A TW201606937 A TW 201606937A TW 104121440 A TW104121440 A TW 104121440A TW 104121440 A TW104121440 A TW 104121440A TW 201606937 A TW201606937 A TW 201606937A
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layer
substrate
titanium
angstroms
opening
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TWI564998B (zh
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林瑀宏
傅美惠
林聖軒
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台灣積體電路製造股份有限公司
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Abstract

本揭露係關於一種接觸結構與接觸結構之形成方法。一接觸結構包括一介電層位於一基底上、一黏著層、一金屬矽化物、一阻障層以及一導電材料。介電層具有一開口至基底的一表面。黏著層沿著開口的側壁設置。金屬矽化物位於基底的表面上。阻障層位於黏著層、金屬矽化物上，以及阻障層直接鄰接金屬矽化物。導電材料位於開口中的阻障層上。

Description

接觸結構及其形成方法
本發明係有關於一種半導體裝置，特別有關於一種具有接觸結構的半導體裝置及其製造方法。
半導體裝置在各種不同的電子應用中被使用，例如個人電腦、手機、數位相機，以及其他的電子設備。半導體裝置通常藉由在一半導體基底上依序沉積絕緣或介電層、導電層以及半導體層材料，並使用微影製程圖案化不同的材料層以在其上形成電路組件及元件所製成。
一般通常期望半導體裝置在高速下操作。此外，一般通常期望減少半導體裝置的尺寸以增加裝置密度以及使電子裝置的功能增加。這兩種特徵在有時候是互相衝突的。在縮小尺寸時，可能造成一些半導體裝置一較低的速度。因此需要解決方案以同時達到高速以及減少尺寸的目的。
本揭露包括一種接觸結構，包括：一介電層位於一基底上、一黏著層、一金屬矽化物層、一阻障層以及一導電材料。介電層具有一開口至基底的一表面。黏著層沿著開口的側壁設置。金屬矽化物位於基底的表面上。阻障層位於黏著層、金屬矽化物上，以及阻障層直接鄰接金屬矽化物。導電材料位於開口中的阻障層上。
本揭露亦包括一種接觸結構，包括：一介電層形成於一基底上、一鈦層、一含鈦金屬矽化物、一氮化矽層以及一導電材料。一開口穿過該介電層至該基底。鈦層位於開口的介電層側壁上。含鈦金屬矽化物位於該基底上。氮化鈦層位於鈦層以及含鈦金屬矽化物上，鈦層沒有任何部分設置於氮化鈦層的至少一部分與含鈦金屬矽化物的至少一部分之間。導電材料位於開口中的氮化鈦層上。
本揭露亦包括一種接觸結構之形成方法，包括：形成一開口穿過一介電層至一基底，開口的一底表面係一半導體材料的一表面。沿著開口的側壁與半導體材料的表面上形成一黏著層。形成一阻障層於黏著層上。在形成阻障層後，將黏著層與半導體材料進行一反應以形成一金屬矽化物。形成一導電材料於開口中的黏著層。
20‧‧‧基底
22‧‧‧介電層
24‧‧‧開口
26‧‧‧黏著層
261‧‧‧第一部分
262‧‧‧第二部分
28‧‧‧阻障層
30‧‧‧金屬矽化物區域
32‧‧‧導電材料
34‧‧‧接觸
50‧‧‧隔離區域
52‧‧‧閘極介電
54‧‧‧閘極電極
56‧‧‧閘極間隔物
58‧‧‧源極/汲極磊晶區域
60、64‧‧‧蝕刻停止層
62‧‧‧層間介電層
66‧‧‧金屬間介電層
68‧‧‧導孔
70‧‧‧線路
第1-6圖係根據一些實施例的形成一接觸結構的中間階段。
第7圖係根據一些實施例的接觸結構以及接觸結構形成過程的一例示應用。
本說明書的揭露內容提供許多不同的實施例或範例，以實施本發明的不同特徵部件。而本說明書以下的揭露內容是敘述各個構件及其排列方式的特定範例，以求簡化發明的說明。當然，這些特定的範例並非用以限定本發明。例如，若 是本說明書以下的揭露內容敘述了將一第一特徵部件形成於一第二特徵部件之上或上方，即表示其包含了所形成的上述第一特徵部件與上述第二特徵部件是直接接觸的實施例，亦包含了尚可將附加的特徵形成於上述第一特徵部件與上述第二特徵部件之間，而使上述第一特徵部件與上述第二特徵部件可能未直接接觸的實施例。再者，本發明的說明中不同範例可能使用重複的參考符號及/或用字。這些重複符號或用字係為了簡化與清晰的目的，並非用以限定各個實施例及/或所述外觀結構之間的關係。
另外，在空間上的相關用語，例如“之下”、“以下”、“下方”、“之上”、“上方”等等係用以容易表達出本說明書中的部件或特徵部件與其他部件或特徵部件的關係。這些空間上的相關用語除了涵蓋了圖式所繪示的方位外，還涵蓋裝置於使用或操作中的不同方位。裝置可具有不同方位(旋轉90度或其他方位)，則在此使用的空間相關詞也可依此相同解釋。
本揭露根據一些實施例提供一種接觸結構及其形成方法。形成一接觸結構的中間階段被繪示。一些不同的實施例被討論。任何所屬領域中具通常知識者應了解在其他實施例的範疇中可考慮其他的修改方式。雖然在特定的情況中討論方法實施例，在任何合理的情況下可實施其他不同的方法實施例且可包括在此敘述的較少或較多的步驟。
第1-6圖係根據一些實施例的形成一接觸結構的中間階段。第1圖繪示一介電層22位於一基底20上並且一開口24 形成並穿過介電層22至基底20。基底20可為一塊狀半導體基底、一絕緣層上覆半導體(semiconductor-on-insulator，SOI)基底、一多層或梯度基底(gradient substrate)，或與其相似的基底，並且可以是摻雜的(例如，以一P型或N型摻雜物)或是未摻雜的。基底20可以是一晶圓，例如一矽晶圓。通常，一絕緣層上覆半導體基底包括一層半導體材料形成於一絕緣層上。絕緣層可為，例如，一埋藏氧化層(buried oxide，BOX)、一氧化矽層或與其相似的膜層。於一基底上提供絕緣層，基底可以是例如一矽或玻璃基底。在一些實施例中，基底20的半導體材料可包括一元素半導體材料，例如矽、鍺或與其相似的材料；一化合物半導體包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦和/或銻化銦；一合金半導體包括矽鍺(SiGe)、鎵砷磷(GaAsP)、鋁銦砷(AlInAs)、鋁鎵砷(AlGaAs)、鎵銦砷(GaInAs)、鎵銦磷(GaInP)和/或鎵銦砷磷(GaInAsP)；或其組合。此外，基底20可包括磊晶區域，其可增加穿過基底20中一裝置的一載子遷移率。舉例來說，一電晶體的一源極/極極區可包括一磊晶區域，其為與基底20不同的材料。磊晶區域可以是先前提及的基底20中任何材料。開口24可形成至一磊晶區域。
介電層22可包括一或多層介電層。舉例來說，介電層22可包括一蝕刻停止層於基底20上，以及一層間介電層(Inter-Layer Dielectric，ILD)於蝕刻停止層上。通常，蝕刻停止層在形成開口24時提供一停止蝕刻製程的機制。蝕刻停止層係由具有與相鄰膜層(例如，一蝕刻停止層位於其下的基底20與其上的層間介電層之間)不同的蝕刻選擇比的材料所形成。 在一實施例中，蝕刻停止層可由氮化矽(SiN)、氮碳化矽(SiCN)、氧碳化矽(SiCO)、碳化氮(CN)或其組合，或與其相似的材料所組成，且藉由適合的方法沉積，例如化學氣相沉積(chemical vapor deposition，CVD)製程、電漿輔助化學氣相沈積(plasma-enhanced CVD，PECVD)製程，或與其相似的方法。層間介電層可由一介電材料組成，例如磷矽酸鹽玻璃(Phospho-Silicate Glass，PSG)、硼矽酸玻璃(Boro-Silicate Glass，BSG)、硼摻雜磷矽酸鹽玻璃(Boro-Doped Phospho-Silicate Glass，BPSG)、未摻雜矽酸鹽玻璃(undoped Silicate Glass，USG)或與其相似的材料，且可藉由適合的方法沉積，例如化學氣相沉積製程、電漿輔助化學氣相沈積製程，或其相似的方法。介電層22可包括額外的膜層於層間介電層上，例如一硬罩幕層、一化學機械研磨(chemical mechanical polish，CMP)停止層，或與其相似的層膜。
開口24係使用可接受的光微影與蝕刻製程而形成並穿過介電層22。蝕刻製程可以是任何可接受的蝕刻製程，例如反應式離子蝕刻製程(reactive ion etching，RIE)、中性射束蝕刻製程(neutral beam etch，NBE)、或與其相似的蝕刻製程或其組合。蝕刻製程可以是非等向性的。蝕刻製程可形成具有實質上垂直側壁的一開口，雖然在一些實施例中也可考慮使用非垂直的側壁。
可實施一清潔製程以去除任何在開口24中基底20露出表面經自然氧化而形成的不需要的氧化物。在一些實施例中，清潔製程使用一氫氟酸成分(HF-based)的氣體或三氟化氮 成分(NF3-based)的氣體和/或氨氣成分(NH3-based)的氣體。在其他實施例中，實施一高溫烘烤。可在存在或不存在氯化氫(HCl)氣體的情形進行高溫烘烤。烘烤溫度可在大約700℃至大約900℃的範圍。烘烤的壓力可在大約10托(Torr)至大約200托的範圍。烘烤時間可在大約30秒至約4分鐘的範圍。
在第2圖中，一黏著層26沿著開口24的側壁形成。在一些實施例中，黏著層26係一金屬層，例如由鈦、鎳、鎢、鈷、一金屬合金，或與其相似的材料所組成。黏著層26可使用一可接受的沉積製程形成，例如物理氣相沉積(physical vapor deposition，PVD)製程、化學氣相沉積製程、原子層沉積製程(atomic layer deposition，ALD)，或與其相似的製程。在繪示的實施例中，黏著層26係藉由物理氣相沉積製程而沉積的鈦所組成。黏著層26的一第一部分261形成於基底20的一表面，以及黏著層26的第二部分262形成於開口24的側壁上。由於物理氣相沉積製程的關係，第一部分261的厚度(例如，於正交於基底20的表面的方向)可大於第二部分262的厚度(例如，於正交於介電層22的對應的側壁的方向)。舉例來說，在一些實施例中，形成的第一部分261的厚度大約為50埃(Å)至300埃，而形成的第二部分262的厚度大約為5埃至50埃。
在第3圖中，一阻障層28形成於黏著層26上。在一些實施例中，阻障層28係一金屬氮化物層，例如包括氮化鈦、氮化鉭、其組合或與其相似的材料。阻障層28可使用一可接受的沉積製程形成，例如化學氣相沉積製程、原子層沉積製程或與其相似的製程。阻障層28可順應性沉積而具有實質上均勻的 厚度，雖然實施例中也考慮厚度上的一些變化。舉例來說，在一些實施例中，形成在第一部分261上的阻障層28的厚度大約為15埃至50埃，而形成在第二部分262上的阻障層28的厚度大約為5埃至40埃。應注意的是雖然黏著層26與阻障層28討論如上，每一膜層可單獨或與彼此一起作為一黏著層和/或一阻障層作用。
在第4圖中，一金屬矽化物區域30形成於基底20上。金屬矽化物區域30包括於黏著層26的第一部分261與基底20的材料之間由一反應而形成的一反應後的材料。可使用一退火(anneal)製程形成金屬矽化物區域30。在一些實施例中，一退火製程可包括放置第3圖的結構在約400℃至約900℃溫度的環境下持續約20秒至約180秒。在一些實施例中，金屬矽化物區域30的厚度係從約40埃至約250埃。在一些實施例中，退火製程造成一反應於基底20與黏著層26的第一部分261之間使得一些或整個第一部分261在反應中被消耗。因此，在一些實施例中，阻障層28的底部部分直接鄰接金屬矽化物區域30，而在一些實施例中，黏著層26沒有設置於阻障層28的底部部分與金屬矽化物區域30之間。金屬矽化物區域30可包括黏著層26的材料以及基底20的材料。舉例來說，假設黏著層26係可為鈦而鄰接於黏著層26的基底20(例如，於反應前)可為矽，而金屬矽化物區域30可以是矽化鈦(TiSi)。此外，位於開口24的側壁上的黏著層26的材料(例如，金屬)與金屬矽化物區域30的材料(例如，金屬)相同。
在第5圖中，一導電材料32形成於開口24中。導電 材料32可以是一金屬，例如鎢、銅、鋁、鎳、金、銀、一金屬合金或與其他相似的材料。導電材料32可使用一可接受的沉積製程形成，例如化學氣相沉積製程、物理氣相沉積製程或與其相似的製程。在繪示的實施例中，導電材料32係藉由化學氣相沉積的鎢。如繪示所示，導電材料32填入開口24的留下的部分且形成於介電層22上。
在第6圖中，實施一平坦化製程(例如化學機械研磨製程)以移除導電材料32、阻障層28以及黏著層26的超出部分。平坦化製程形成一接觸34於開口24中，其中介電層22、黏著層26、阻障層28與接觸34共平面。
第7圖繪示第1-6圖討論的接觸結構與接觸結構的形成過程的一例示應用。第7圖繪示一電路組件，例如一場效電晶體(field effect transistor，FET)，其中已形成一接觸。電路組件可以是一P型場效電晶體(pFET)或N型場效電晶體(nFET)。在繪示的例子中，電路組件係一平面場效電晶體(planar FET)，雖然其他實施例中亦可為三維鰭狀電晶體(finFET)。在其他實施例中則可為其他不同的電路組件。
第7圖中的電路組件包括一基底20、隔離區域50、閘極介電質52、閘極電極54、閘極間隔物56、源極/汲極磊晶區域58、蝕刻停止層60、層間介電層62、金屬矽化物區域30、黏著層26、阻障層28、接觸34、蝕刻停止層64、金屬間介電層(Inter-Metal dielectric，IMD)66、導孔68以及線路70。電路組件可如以下所述而形成。
提供一基底20。基底20可以是如之前在第1圖所討 論的任何基底。隔離區域50接著形成於基底20中。隔離區域50可藉由蝕刻基底20中的凹部和/或溝槽以及用絕緣材料填入凹部或溝槽中而形成。蝕刻可以是任何可接受的蝕刻製程，例如一反應式離子蝕刻、中性射束蝕刻、與其相似的蝕刻製程或其組合。蝕刻製程可以是非等向性的。絕緣材料可以是氧化物(例如，氧化矽)、氮化物、與其相似的材料或其組合，且可以藉由一高密度電將化學氣相蝕刻(high density plasma chemical vapor deposition，HDP-CVD)製程、流動式化學氣相沉積(flowable CVD，FCVD)(例如，於一遙控電漿系統中沉積一以化學氣相沉積為主的材料，並且後固化(post curing)使之轉換成另一材料，例如氧化物)、與其相似的製程或其組合而形成。其他絕緣材料可藉由任何可接受的製程形成。一平坦化製程(例如，化學機械研磨製程)可移除任何超出的絕緣材料且形成共平面的隔離區域50的上表面以及基底20的上表面。隔離區域50可定義基底20中的主動區域，一電路組件將會在其形成。一井區可形成於主動區域中。舉例來說，可進行佈植濃度等於或少於1018cm-3的(例如介於約1017cm-3至1018cm-3)的摻雜物，以形成井區。P型不純物(例如，對於一N型電路組件的一井區)，包括硼、二氟化硼(BF2)或與其相似的材料，而N型不純物(例如，對於一P型電路組件的一井區)，包括磷、砷或與其相似的材料。可使用一退火製程以活化佈植的不純物。
接著，閘極介電質52與閘極電極54形成於基底20上。一閘極介電質材料層沉積於基底20上。在一些實施例中，閘極介電質材料包括氧化矽、氮化矽、一高介電常數介電材料、 多膜層或與其相似的材料。一高介電常數介電材料可具有大於7.0的介電常數數值，並且可包括一金屬氧化物或鉿、鋁、鋯、鑭、鎂、鋇、鈦、鉛的矽酸鹽及其組合。閘極介電材料層的形成方法可包括化學氣相沉積製程、分子束沉積(Molecular-Beam Deposition，MBD)製程、原子層沉積製程、電漿輔助化學氣相沉積製程或與相似的製程。一閘極電極材料層沉積於閘極介電材料層上。閘極電極材料可以是摻雜或未摻雜的多晶矽；一含金屬材料(例如，氮化鈦(TiN)、氮化鉭(TaN)、碳化鉭(TaC)、鈷、釕、鋁或其組合或是多膜層、或其他適合的材料。閘極電極材料層的形成方法可包括化學氣相沉積製程、原子層沉積製程、電漿輔助化學氣相沉積製程或與其相似的製程。一罩幕層可形成於閘極電極材料層上。罩幕層可包括氮化矽、氮化矽碳、氮化碳或與其相似的材料，且可藉由化學氣相沉積製程、電漿輔助化學氣相沉積製程或與其相似的製程而形成。罩幕層、閘極電極材料以及閘極介電材料接著可使用一可接受的光微影製程與蝕刻製程而圖案化以形成一罩幕(未繪示)、閘極電極54及閘極介電質52。蝕刻可以是任何可接受的蝕刻製程，例如反應性離子蝕刻、中性射束蝕刻、與其相似的製程或其組合。蝕刻製程可以是非等向性的。
接著，進行輕摻雜源極/汲極(lightly doped source/drain，LDD)區域的佈植製程。圖案化的罩幕、閘極電極54和/或閘極介電質52可做為佈植製程的自對準罩幕以在基底中形成輕摻雜源極/汲極區域。P型不純物(例如，對於一P型電路組件)，包括硼、二氟化硼或與其相似的材料，而N型不純 物(例如，對於一N型電路組件)，包括磷、砷或與其相似的材料。輕摻雜源極/汲極區域可具有一不純物濃度在約1015cm-3至約1016cm-3。可使用一退火製程以活化佈植的不純物。
閘極間隔物56接著沿著閘極介電層52與閘極電極54的側壁形成。一間隔物材料層順應性沉積於基底20上。間隔物材料可以是氮化矽、氮碳化矽、其組合或與其相似的材料，並且可藉由化學氣相沉積、電漿輔助化學氣相沉積或與其相似的製程而沉積。非等向性的蝕刻製程可移除間隔物材料層的水平部分，使得間隔物材料層位於閘極電極54與閘極介電質52的側壁上的部分留下作為閘極間隔物56。蝕刻製程可以是任何可接受的蝕刻製程，包括一反應式離子蝕刻製程、中性射束蝕刻製程、與其相似的製程或其組合。
接著，形成源極/汲極磊晶區域58。凹部可形成於基底20中。凹蝕可包括一蝕刻製程，其對於基底20的材料具有選擇性，其中例如閘極間隔物56、閘極電極電極54上的罩幕，以及隔離區域50通常不受蝕刻。因此，凹部可被定義在未被閘極間隔物56與閘極介電質52覆蓋以及隔離區域50外的基底的主動區域中。蝕刻製程可以是任何適合的蝕刻製程，例如乾式或濕式、及等向性或非等向性的蝕刻製程。源極/汲極磊晶區域58磊晶成長於凹部內，例如藉由金屬-有機物化學氣相沉積(metal-oganic CVD，MOCVD)製程、分子束磊晶(Molecular beam epitaxy，MBE)製程、液相磊晶(liquid phase epitaxy，LPE)製程、氣相磊晶(vapor phase epitaxy，VPE)製程、選擇性磊晶成長(selective epitaxy growth，SEG)製程、與其相似的製程或其 組合。源極/汲極磊晶區域58可包括任何可接受的材料。應注意是對於一N型電路組件的例示的材料可包括矽、碳化矽、磷碳化矽(SiCP)、磷化矽(SiP)或與其相似的材料。應注意是對於一P型電路組件的例示的材料可包括矽鍺(SiGe)、矽鍺硼(SiGeB)或與其相似的材料。源極/汲極磊晶區域58可具有自基底20的上表面高起的表面且具有刻面(facets)。
類似於之前討論的源極/汲極區域形成過程，源極/汲極磊晶區域58可以摻雜物佈植以形成輕摻雜源極/汲極區域，接著進行一退火製程。P型不純物(例如，對於一P型電路組件)，包括硼、二氟化硼(BF2)或與其相似的材料，而N型不純物(例如，對於一N型電路組件)，包括磷、砷或與其相似的材料。源極/汲極區域可具有介於約1019cm-3至約1021cm-3的一不純物濃度。在其他實施例中，源極/汲極磊晶區域58可在成長時進行原位摻雜(in situ doped)，或藉由原位摻雜與佈植的摻雜物結合進行摻雜。
如果存在罩幕的話，罩幕位於閘極電極54上，可接著移除閘極間隔物56的上部，藉由例如一非等向性的蝕刻製程。蝕刻製程可以是任何可接受的蝕刻製程，例如一反應式離子蝕刻製程、中性射束蝕刻製程、與其相似的製程或組成。於蝕刻製程後，可形成閘極間隔物56、閘極電極54，以及閘極介電質52，如第7圖所繪示。
蝕刻停止層60順應性形成於基底20、隔離區域、源極/汲極磊晶區域58、閘極間隔物56及閘極電極54上。在一實施例中，蝕刻停止層60可由氮化矽、氮碳化矽、氧碳化矽、 氮化碳、其組合或與其相似的材料所組成，且藉由任何適合的方法沉積，例如化學氣相沉積製程、電漿輔助化學氣相沉積製程或與其相似的製程。層間介電層62形成於蝕刻停止層60上。層間介電層62可由一介電材料組成，例如磷矽酸鹽玻璃、硼矽酸玻璃、硼摻雜磷矽酸鹽玻璃、未摻雜矽酸鹽玻璃或與其相似的材料，且可藉由適合的方法沉積，例如化學氣相沉積製程、電漿輔助化學氣相沈積製程，或其相似的方法。可平坦化層間介電層62，例如藉由化學機械研磨製程，使之具有平坦的上表面。
接著，接觸結構各自包括黏著層26、阻障層28、金屬矽化物區域30以及接觸34形成並穿過層間介電層62與蝕刻停止層60至對應的源極/汲極磊晶區域58。在其他實施例中，並未形成源極/汲極磊晶區域58，接觸結構形成至基底20。可以如之前在第1-6圖所討論的形成接觸結構。
蝕刻停止層64形成於層間介電層62及接觸結構上。在一實施例中，蝕刻停止層64可由氮化矽、碳氮化矽、碳氧化矽、氮化碳、其組合或與其相似的材料所組成，且藉由任何適合的方法沉積，例如化學氣相沉積製程、電漿輔助化學氣相沉積製程或與其相似的製程。金屬間介電層66形成於蝕刻停止層64上。金屬間介電層66可由一介電材料組成，例如磷矽酸鹽玻璃、硼矽酸玻璃、硼摻雜磷矽酸鹽玻璃、未摻雜矽酸鹽玻璃或與其相似的材料，且可藉由適合的方法沉積，例如化學氣相沉積製程、電漿輔助化學氣相沈積製程，或其相似的方法。
內連線結構(例如包括一線路70與一導孔68)形成 於金屬間介電層66中。內連線結構可藉由使用適合的光微影技術而形成。通常，可進行一光微影製程與蝕刻製程以移除對應於內連線結構的金屬間介電層66的一部分以定義金屬間介電層66中的凹部和/或開口。蝕刻製程後，以一導電材料(如一或多層的金屬、元素金屬、過渡金屬或與其相似的材料)填入凹部和/或開口。在一些實施例中，用來填入凹部和/或開口的導電材料係藉由電化學電鍍(electro-chemical plating，ECP)沉積的銅。也可使用其他導電材料及製程。
應注意的是內連線結構可包括由一或多層的導電材料形成的阻障/黏著層，例如鈦、氮化鈦、鉭、氮化鉭或與其相似的材料。在一實施例中，阻障/黏著層可包括依序形成的氮化鉭薄層與鉭薄層。氮化鉭及鉭層可藉由例如化學氣相沉積製程、物理氣相沉積製程或與其相似的製程而形成。可進行一平坦化製程，例如化學機械研磨製程，以移除超出的阻障層材料和/或導電材料。形成的內連線結構因此耦接至接觸結構。可形成額外的金屬間介電層及內連線結構。
雖然於第7圖中所討論的電路組件可形成於一製程稱之為前閘極(gate-first)製程，所屬技術領域中具有通常知識者應瞭解到可修改使得在此揭露的型態可應用於一後閘極(gate-last)或取代閘極(replacement gate)製程。在實施例中亦可應用至這些製程。
這些實施例可實現一些優點。第一，可簡化具有金屬矽化物區域之接觸結構的形成程序，因為清除了用於矽化製程中移除未反應的金屬的步驟。此外，可更容易控制金屬矽 化物區域的厚度，因為是由金屬的量來決定金屬矽化物區域的厚度而非由溫度或退火製程的時間。再者，沒有黏著層設置於阻障層與金屬矽化物區域之間，使得電阻可減少。藉由減少電阻，可減少電阻-電容(resistance-capacitance，RC)時間常數，其可甚至在減少尺寸的情形下，得到較快的裝置操作。除之以外，本實施例亦可實現其他的優點。
根據一些實施例，一種接觸結構包括一介電層位於一基底上、一黏著層、一金屬矽化物層、一阻障層以及一導電材料。介電層具有一開口至基底的一表面。黏著層沿著開口的側壁設置。金屬矽化物位於基底的表面上。阻障層位於黏著層、金屬矽化物上，以及阻障層直接鄰接金屬矽化物。導電材料位於開口中的阻障層上。
根據其他的實施例，一種接觸結構包括一介電層形成於一基底上、一鈦層、一含鈦金屬矽化物、一氮化矽層以及一導電材料。一開口穿過該介電層至該基底。鈦層位於開口的介電層側壁上。含鈦金屬矽化物位於該基底上。氮化鈦層位於鈦層以及含鈦金屬矽化物上，鈦層沒有任何部分設置於氮化鈦層的至少一部分與含鈦金屬矽化物的至少一部分之間。導電材料位於開口中的氮化鈦層上。
根據另一實施例，一種接觸結構之形成方法包括形成一開口穿過一介電層至一基底，開口的一底表面係一半導體材料的一表面。沿著開口的側壁與半導體材料的表面上形成一黏著層。形成一阻障層於黏著層上。在形成阻障層後，將黏著層與半導體材料進行一反應以形成一金屬矽化物。形成一導 電材料於開口中的黏著層。
以上概略說明了本揭露數個實施例的特徵部件，使所屬技術領域中具有通常知識者對於後續本揭露的詳細說明可更為容易理解。任何所屬技術領域中具有通常知識者應瞭解到本說明書可輕易作為其它結構或製程的變更或設計基礎，以進行相同於本揭露實施例的目的及/或獲得相同的優點。任何所屬技術領域中具有通常知識者也可理解與上述等同的結構或製程並未脫離本揭露之精神和保護範圍內，且可在不脫離本揭露之精神和範圍內，當可作更動、替代與潤飾。
20‧‧‧基底
22‧‧‧介電層
26‧‧‧黏著層
28‧‧‧阻障層
30‧‧‧金屬矽化物區域
34‧‧‧接觸

Claims (10)

  1. 一種接觸結構，包括：一介電層位於一基底上，該介電層具有一開口至該基底的一表面；一黏著層沿該開口的側壁設置；一金屬矽化物位於該基底上；一阻障層位於該黏著層以及該金屬矽化物上，該阻障層直接鄰接該金屬矽化物；以及一導電材料位於該開口中的該阻障層上。
  2. 如申請專利範圍第1項所述之接觸結構，其中該黏著層為鈦，該阻障層為氮化鈦，且該金屬矽化物包括鈦。
  3. 如申請專利範圍第1項所述之接觸結構，其中該黏著層的厚度介於5埃至50埃，該金屬矽化物的厚度介於40埃至250埃，且該阻障層的厚度介於5埃至50埃。
  4. 一種接觸結構，包括：一介電層位於一基底上，一開口穿過該介電層至該基底；一鈦層位於該開口的介電層側壁上；一含鈦金屬矽化物位於該基底上；一氮化鈦層位於該鈦層以及該含鈦金屬矽化物上，該鈦層沒有任何部分設置於該氮化鈦層的至少一部分與該含鈦金屬矽化物的至少一部分之間；以及一導電材料位於該開口中的該氮化鈦層上。
  5. 如申請專利範圍第4項所述之接觸結構，其中該鈦層的厚度介於5埃至50埃，該含鈦金屬矽化物的厚度介於40埃至250 埃，且該氮化鈦層的厚度介於5埃至50埃。
  6. 如申請專利範圍第4項所述之接觸結構，其中該氮化鈦層直接鄰接該含鈦金屬矽化物。
  7. 一種接觸結構之形成方法，包括：形成一開口穿過一介電層至一基底，該開口的一底表面係一半導體材料的一表面；沿著該開口的側壁與該半導體材料的該表面上形成一黏著層；形成一阻障層於該黏著層上；在形成該阻障層後，將該黏著層與該半導體材料進行一反應以形成一金屬矽化物；以及形成一導電材料於該開口中的該黏著層。
  8. 如申請專利範圍第7項所述之接觸結構之形成方法，其中該反應包括一退火製程。
  9. 如申請專利範圍第7項所述之接觸結構之形成方法，其中在該反應之後，該阻障層直接鄰接該金屬矽化物。
  10. 如申請專利範圍第7項所述之接觸結構之形成方法，其中形成於半導體材料的該表面上的該黏著層的厚度介於50埃至300埃，該金屬矽化物的厚度介於40埃至250埃，該阻障層的厚度介於5埃至50埃，該導電材料為鎢，該黏著層為鈦，該阻障層為氮化鈦，且該金屬矽化物包括鈦。
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US9831183B2 (en) 2017-11-28
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US10756017B2 (en) 2020-08-25
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