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TW200943521A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
TW200943521A
TW200943521A TW097141755A TW97141755A TW200943521A TW 200943521 A TW200943521 A TW 200943521A TW 097141755 A TW097141755 A TW 097141755A TW 97141755 A TW97141755 A TW 97141755A TW 200943521 A TW200943521 A TW 200943521A
Authority
TW
Taiwan
Prior art keywords
transistor
output signal
integrated circuit
semiconductor integrated
axis
Prior art date
Application number
TW097141755A
Other languages
English (en)
Inventor
Masanori Isoda
Original Assignee
Renesas Tech Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Tech Corp filed Critical Renesas Tech Corp
Publication of TW200943521A publication Critical patent/TW200943521A/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Amplifiers (AREA)
TW097141755A 2007-12-10 2008-10-30 Semiconductor integrated circuit TW200943521A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007317961A JP5126963B2 (ja) 2007-12-10 2007-12-10 半導体集積回路

Publications (1)

Publication Number Publication Date
TW200943521A true TW200943521A (en) 2009-10-16

Family

ID=40720963

Family Applications (1)

Application Number Title Priority Date Filing Date
TW097141755A TW200943521A (en) 2007-12-10 2008-10-30 Semiconductor integrated circuit

Country Status (4)

Country Link
US (2) US7843227B2 (zh)
JP (1) JP5126963B2 (zh)
CN (1) CN101459171B (zh)
TW (1) TW200943521A (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9373623B2 (en) 2013-12-20 2016-06-21 Taiwan Semiconductor Manufacturing Company Limited Multi-layer semiconductor structures for fabricating inverter chains
US9483600B2 (en) * 2014-03-14 2016-11-01 Qualcomm Incorporated Multi supply cell arrays for low power designs
JP6364271B2 (ja) * 2014-07-25 2018-07-25 ラピスセミコンダクタ株式会社 半導体集積回路および回路レイアウト方法
US10102327B2 (en) * 2014-12-31 2018-10-16 Stmicroelectronics, Inc. Integrated circuit layout wiring for multi-core chips
CN117765991A (zh) * 2022-09-26 2024-03-26 华为技术有限公司 一种环形反相器、锁存器、存储电路、存储器及电子设备
US20250031456A1 (en) * 2023-07-20 2025-01-23 Samsung Electronics Co., Ltd. Cell architecture of semiconductor device including semiconductor cells connected based on backside power distribution network

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3647323B2 (ja) * 1999-07-30 2005-05-11 富士通株式会社 半導体集積回路
JP3526450B2 (ja) * 2001-10-29 2004-05-17 株式会社東芝 半導体集積回路およびスタンダードセル配置設計方法
JP2003309178A (ja) * 2003-04-11 2003-10-31 Matsushita Electric Ind Co Ltd 半導体装置のレイアウト構造およびレイアウト設計方法
JP2004319855A (ja) 2003-04-17 2004-11-11 Seiko Epson Corp レイアウト設計方法、集積回路、及び電子機器
JP4778689B2 (ja) * 2004-06-16 2011-09-21 パナソニック株式会社 標準セル、標準セルライブラリおよび半導体集積回路
JP4633447B2 (ja) * 2004-11-17 2011-02-16 ルネサスエレクトロニクス株式会社 半導体装置及び半導体装置の製造方法
JP2007073709A (ja) * 2005-09-06 2007-03-22 Nec Electronics Corp 半導体装置
TWI370678B (en) * 2006-02-15 2012-08-11 Sony Corp Solid-state image-capturing device, driving method thereof, camera, electric charge transfer device, driving method and driving device for driving load, and electronic equipment
JP2008153435A (ja) * 2006-12-18 2008-07-03 Matsushita Electric Ind Co Ltd 半導体集積回路

Also Published As

Publication number Publication date
US20110043292A1 (en) 2011-02-24
JP5126963B2 (ja) 2013-01-23
US20090146693A1 (en) 2009-06-11
CN101459171B (zh) 2013-11-06
US8076957B2 (en) 2011-12-13
US7843227B2 (en) 2010-11-30
CN101459171A (zh) 2009-06-17
JP2009141238A (ja) 2009-06-25

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