SU877530A1 - Device for computing square root - Google Patents

Description

(54) DEVICE FOR EXTRACTING SQUARE ROOT

The invention relates to computing and measurement technology and is intended to extract the square root of a binary code number.

A device for extracting square root, containing counters, code comparisons, triggers, is known.

The drawback of the device is low accuracy, due to the fact that to it allows to obtain only integer values of the root, and low speed. The closest in technical essence to the present invention is a device zj for extracting a square root containing three integrator with sequential transfer and a reversible counter. In the known device, the code of the input signal N and the result code of the square root extraction n (t) are converted into

particular fj, and fyq (t), respectively, equal

 Js.

(one)

N

N

m

N

five

 n (t).

(2)

lilirt

where fg is the reference frequency;

% i capacity integrators with sequential transfer,

and correction of the number n (t) by pulses of the difference frequency Cf (sj - fj (t) 3 before the equality f "(t) is established. A disadvantage of this device is the low speed caused by (because the correction n (t) is produced by the difference frequency The aim of the invention is to increase the speed of the device. 38 The goal is achieved by the fact that the device for extracting the square root containing the integrators and the reversible counter, and the inputs of the first and second integrators The control input of the first integrator is connected to the information input of the device, the output of the second integrator is connected to the input of the third integrator, a register, two counters, a group of elements AND, elements of AND, OR and a correction unit, and the inputs of the first and second counters are entered connected to the first and third integrators of the first and third integrators, respectively, and the overflow outputs to the first and second inputs of the correction unit, the information outputs of the first counter, are connected to the first inputs of the AND group elements, the second inputs of which are connected to the outputs of the registry j connected to the control. the inputs of the second and third integrators, and the outputs of the AND elements are connected to the inputs of the OR element, the addition and subtraction inputs of the reversible counter are connected respectively to the outputs of the first and second AND elements, the first inputs of which are connected to the output of the OR element, the second to the first and the third the second and third outputs of the correction unit, the fourth output of which is connected to the reset inputs of the first and second counters, the first, second and third integrators and the control inputs of the register entry whose inputs are connected not with reversible, counter outputs. The correction block contains two flip-flops, three AND elements, an OR element, the first inputs of the first and second flip-flops being the first and second inputs of the correction block, the second inputs connected to the output of the first And element connected to the fourth output of the block, the inputs of the first And element connected to the first outputs of the first and second triggers respectively, connected to the first inputs of the second and third elements AND, respectively, and are the second and third outputs of the correction unit; the second outputs of the first and second triggers trench are connected to second inputs of respectively the second and third AND gates, whose outputs are connected to the inputs of the OR gate, the output of which is Ipervym output correction unit. 0 The drawing shows a block diagram of a device for extracting a square root. The device consists of integrators (with sequential transfer, counters 4 and 5, reversible counter 6, register 7, group of elements AND 8, elements AND 9, 10, and OR 1I of correction block 12, including triggers 13 and 14, elements AND 15 17 and OR 18. 4 and 5 are binary pulse counters, the inverse output of each trigger of which is connected to the trigger input of the next bit. Register 7 consists of D-triggers, the synchronization inputs of which are combined into a common transfer control bus, and D-INPUTS for triggers are register inputs. It operates as follows: Before the beginning of each extraction cycle, the square root integrators 1-3 with sequential transfer, the counters 4 and 5, the triggers 13 and 14 of the correction block 12 are reset to zero, and the result of the previous square root extraction is transferred from the reversible counter 6 to the register 7. The sequential transfer integrator generates a frequency-pulse sequence with a pulse frequency fj (expression 1) proportional to the input signal N, fed to the input of the counter 4. Last used It is cast as a frequency divider f | and, in addition, together with the elements of AND 8 and the element OR 11, forms an integrator with sequential transfer, at the output of which a frequency-pulse correction sequence with a pulse frequency f is formed. f bL К m where m is the numerical capacity of the counters 4 and 5. The integrators 2 and 3 with sequential transfer, connected in series, the input of the control code of which is supplied with the result code of the previous extraction of the square root n, form a frequency-pulse sequence with the frequency followed by the number capacity integrators 2 and 3. The clock time t from the start of the extraction cycle, the square root m, the subsequent trigger of counter 4, is set to one and the trigger 13 of correction unit 12 is set to one. After time ty from the beginning of the extraction cycle, the square root is set to one state, the last trigger of counter 5 and sets trigger to unit one. When the frequencies fij are equal, heres 13 and 14 are set to one at the same time. At the same time, at the output of the unequal circuit formed by elements 15 and 16 and element 18, there is a zero potential that prohibits the passage of correction pulses from the output of element 11 or 11 to the input of the reversible counter 6, where the result of the previous extraction of the square root P remains. taking into account expressions (7), (l)

Ni

Have

P

If the frequencies fj and fy are not equal, then one of the triggers 13 and 14 of the correction block 12 will work earlier. At the same time, at the output of the element OR I8, a single potential appears, allowing the passage of the pulses of the correction sequence f to one of the inputs of the subtracting counter 6 (with - to the addition input, with N y | to the input of the subtraction). When the unit I2 is triggered at one unit, zero potential appears at the output of the element OR 18 and the arrival of pulses of the sequence fj at the input of counter 6 stops, and at the output of the element AND 1 7 a reset pulse appears, producing a zero setting of integrators 1 -3, counters 4 and 5, triggers 13 and 14, and transfer of code from counter 6 to register 7. At the same time, between the settings in unit triggers 13 and 1 trig

Then the difference Af of the frequencies f, and f

35 can be represented as follows:

  | fN-fц | | T + dp) |. (13)

  m p

40

When condition 2n p is fulfilled from expression (13), it follows that

.- i. u.f. tk1

Ah

2f.n

and taking into account the expression (4) that

one

N vl

Af

Jn and

J fN

(14)

R

vi I,

which corresponds to the expression (lO).

The proposed device is different from the known, because it has a much higher speed. i.e., during the time interval of correction I, counter 6 receives the number of pulses an, equal to Lp а taking into account expressions (9), (5), (b) / 3) fM-n 1 1 1 Lp - m t I, ( 10) 6 sets the number and in the counter re ± n,. (Ii) proportional to the square root of the input number N. The validity of the last statement follows from the following considerations. The number N, from which the square root is extracted, can be represented as the square of the previous cure-corrected root result, multiplied by the coefficient N - t

If the frequencies f and fw (fc) are not equal (expressions 1 and 2), in a known device for extracting a square root, a transient occurs, which is defined by the equation fi Ti

 - J f (t) dt n (t). (15)

From (l5) taking into account (He (2) it follows that the duration of the transient process is Vf4 tb3),) the relative error Here Pf is actually the obtained square root value of the number N. For the proposed device, the cycle time of square root extraction tX) will be longer of time or t. At tw 7 t fvi, taking into account the expressions (1 (b) and (4), the ratio C2 / t is T2 nin l + dli ± (f) cf 6, (When, and the nominal value of P0; y 1000, which takes place in the real collector square root, 4. If the condition of 2n Y and n is not met, to accurately extract the square root In the proposed device, several cycles of extraction of the roots are required. When using the proposed device in real electrical systems, where the effective values of voltage and alternating current can vary within O, 5-1.5 from their nominal values, and therefore , n varies in the limit from 500 to 1500, the maximum extraction time of the square root is necessary when changing n from 500 to 150 or vice versa, and with an error of less than 0.001, as shown by the experiment

Experimental studies, no more than three cycles, i.e.

T. Sn.

Thus, even in this case, the proposed device gains in speed in comparison with the known, since

Claims (2)

1. USSR author's certificate number 694779, cl. G 06 F 7/38, 1970, 2.Hundh J, Digital techniqne for small computations, L. Bret. L.R.E., 1959, V. 19 (prototype).