SU781809A1 - Multiplier - Google Patents

Description

The invention relates to computing and can be used in analog-digital computing systems. Digital devices are known for multiplying the numbers entering the device by parallel code, consisting of digital blocks implementing memory, addition, shift operations, etc. 1. The disadvantage of these devices is the large hardware costs of organizing the start of communication between devices. The closest to the present invention is a multiplying device, which makes it possible to calculate single charge increments of the product when single-bit increments of factors are received at its input, which allows you to reduce the cost of equipment in comparison with digital devices to multiply the numbers entering the device by parallel code. organization of communication channels with other devices, i.e. simplify system communication devices. For example, a computational structure with a component of a known device allows one to parallelize the computation process and build sufficiently high-performance problem-oriented processors. In the known device, the multiplication process is based on the approximate differential calculus formula D (X.), while the exact differentiation formula also takes into account the term of the highest order of smallness (X.- a) U.-DCH- - -DX - --ЫХ -D However, due to the rejection of the value of DH-D, an accumulation of error occurs in it as it is computed. 2. The circuit of the invention is an increase in the accuracy of computations. The goal is achieved by the fact that the multiplier device containing the counter of the first factor, the counter of the second factor, the unit multiplying the factor for a unit increment and accumulating adder, the input cathoro is connected to the output of the unit multiplying factor for a unit increment,

the input of unit increments of the second multiplier of the multiplying device is connected to the input of the counter of the second factor, characterized in that a delay element, a switch, two OR elements, a high-order bit counter and a unit of incremental unit of products are inputted into it, and the input of the delay element is connected to the input of unit ones increments of the first multiplier of the multiplying device, the output of the delay element is connected to the input of the counter of the first multiplier and one of the inputs of the first OR element, the other input is It is connected to the input of the counter of the second multiplier, and the output is connected to the first input of the multiplier unit by a single increment, the inputs of the second commutator are connected to the outputs of the first and second multiplier counters, and the output is connected to the second input of the multiplier factor for a single increment, one input of the second the OR element is connected to the overflow output of the accumulating adder, another input is connected to the output of the product unit increment generator, and the output is connected to the input of the high order counter Neuve dressings, input of the product of the increment of unit connected to the output sign bit counter starschih bits Neuve dressing.

The drawing shows a block diagram of devices. The device consists of a counter 1 of the first multiplier, a counter 2 of the second multiplier, a switch 3, a unit 4 multiplying the multiplier by a unit increment, accumulating adder 5, a counter 6 higher bits

uninterrupted, shaper 7 unit increments of the product, the first element OR 8, the second element OR 9, the element 10 delay

The input element 10 of the delay is connected to the input 12 unit increments of the first

multiplier, and output - with the input of the counter 1 of the first multiplier and the input of the first element OR 8. The input 11 unit increments of the second factor is connected to the input of the counter of the second factor and another input of the first element OR 8. The output of the first element OR 8 is connected to the multiplication unit 4 multiplying by single increment. The outputs of the counters of the first and second multipliers are connected to the inputs of switch 3. The output of switch 3 is connected to the input of block 4 multiplying the multiplier by a unit increment. The output of the multiplier multiplier 4, per unit increment, is connected to the input of accumulating adder 5. The overflow output of adder 5 is connected to one of the inputs of the second element SH 9, the other input of the second terminal OR 9 is connected to the output of the former 7 unit increments

product. The VEIODE of the second element OR 9 is connected to the input of the counting of the 6 most significant bits. The input of the imager 7 unit increments of the product is connected to the significant digit of the counter 6 of the higher order bits.

The device multiplies according to the following system of equations

.-dL-Sc ne (K) g (K -.), (k -.) (KL.g (M

(K) (k-i) U)

h ..

g (.)

The device works as follows.

Before starting the calculation, the counters and the accumulating adder are set to the zero state. Thereafter, unit increments of the first and second factors are simultaneously input to the device and a unit increment of product is generated.

The preparation of the device and the issuance of a single increment of product is performed in one cycle, which is accomplished in two cycles. In the first cycle, formulas (1), (2), and (3) are realized. At the output of a unit increment generator 7, a unit increment of product Z appears, its sign opposite to the unresolved symbol of €. , arriving at the input of the imager 7 of the unit increment of the product with the output of the sign bit of the counter of the 6 most significant bit bits (calculated by the formula (1)). The unit increment of the product is fed to the input of the second element OR 9 and from its output to the input of the counter 6 high-order bits. In the counter 6 high-order bits of the fixture and the accumulating switch 5, the value

Ck -,) d (q)

The input of the multiplier factor by a single increment through the switch 3 gives the contents of the counter of the first multiplier. From the first element OR 8, a single increment of the second factor enters the input of the multiplier 4 multiplier per unit increment, and the value of HF is generated at the output of this circuit. In the accumulating adder 5 and the counter 6 of the upper bit gap, the value of

Claims (2)

r (KLe (K.;., (Ki.CK) (K) A single H increment is input to the input of counter 2 of the second factor and a value is generated. After the transient processes in the accumulator 5 and the counter of the 6th discharge times start, the second the clock at which formulas (4) and (5) are implemented. From the output of delay element 10, a single increment Da enters the input of counter 1 of the first factor, where the value of tuda is formed, through the first element OR 8 at the input of block 4 multiplying the factor a single increment. The value of X from the counter of the second factor switches through the switch 3 to the input of block 4 multiplying the multiplier per unit increment, and from the output of the block to the input the sum of the torus 5. In the accumulating adder 5 and the counter, the value of (kL (K) (K) (K) The product of two factors is found when the unit increments of the factors and the product after each cycle change sign, i.e., when the factors of the factors are equal to the specified numbers or less by a unit increment, and b after each cycle changes sign. The value of the product is not stored in the device, but is equal to the algebraic sum of the increments issued from the output of the unit of individual increments of the product in the process. The device makes it possible to obtain the product without accumulating the bounce as it is calculated. The use of the device is expedient for the construction of block computing structures by a longer time of continuous simulation of the process, where with a large number of iterations there should be no accumulation of error. The invention The multiplying device containing the counter of the first factor, the counter of the second factor, the multiplier multiplying unit for a unit increment and accumulating adder, the input of which is connected to the output of the multiplier factor unit for a single increment, the input of unit increments of the second multiplier of the multiplying device for the multiplier unit counter input of the second multiplier of the multiplier device for the unit increment of the second multiplier of the multiplier for the multiplier per unit increment characterized in that, in order to improve accuracy, a delay element, a switch, two OR elements, a high-order counter are entered into it uninterrupted and shaper unit increments of works, and the input delay element is connected to the input unit increments of the first multiplier multiplier device, the output of the delay element is connected to the input of the counter of the first multiplier and one of the inputs of the first element OR, the other input is connected to the input of the counter of the second factor, and the output is connected to the first input of the multiplier factor by a single increment, the switch inputs are connected to the outputs of the counters of the first and second factors, and the output connected to the second input of the multiplier unit by a single increment, one input of the second element OR is connected to the overflow output of the accumulating adder, the other input is connected to the output of the unit of product increments, and the output is connected to the input of the senior low-voltage counter, the input of the single increment generator The operation is connected with the output of the sign bit of the high bit counter. Sources of information taken into account during the examination 1. USSR author's certificate No. 608157, cl. G 06 F 7/39, 1975. 2.Neslukhovsky KS Digital differential analyzers. M., Mashchinostroenie, 1968, p. 90-91, fig. 23 (prototype). LlIIHij --ir cr: