SU790099A1 - Digital pulse repetition frequency multiplier - Google Patents

Description

(54) DIGITAL MULTIPLE OF FREQUENCY FOLLOWING PULSES

The invention relates to automation and instrumentation technology and may contribute, in particular, to an increase in the deviation in control systems. Known frequency multiplier, made on the basis of analog technology and consisting of a linear integrator, two zero-6rganov and element OR. The input sinusoidal signal is fed to the inputs of the first zero-organ and linear integrator. The input of the second zero-body signal comes from the output of the linear integrator with a phase of 9-1 × 1 relative to the BjcoOHoro signal. Null-organs form narrow impulses at the moment of passing signals through zero points, respectively. The outputs of the nup.-bodies connected to the element OR. The output signal of the logic element or has a frequency four times greater than the frequency of the input signal l7 The disadvantage of this device is the instability of operation and low accuracy. The closest in technical essence is a digital pulse frequency multiplier made on the basis of digital equipment and consisting of a generator of the first reference frequency connected in series with the first pulse counter, the first input of the code comparison unit, a buffer device and of the generator of the second reference frequency in series with the second pulse counter, the memory device and the second input of the code comparison circuit, the synchronization inputs of the second pulse counter and the memory device oedineny with an input bus and the output buffer unit is connected to a zero setting input of the first pulse counter IX. The disadvantage of this device is that the frequency of the output signal is generated with an error determined by the measurement resolution of the period of the input signal in the second pulse counter. The magnitude of this error is given

By the time pulses follow, there may be П periods of the frequency of the generator of the first reference frequency over the period of the frequency of the signal to be multiplied.

The aim of the invention is to improve the frequency multiplication accuracy.

The goal is achieved by the fact that a digital pulse frequency multiplier, comprising a reference frequency generator, the first output of which is connected to the input of the first pulse counter, a memory block, the input of which is connected to the output of the second pulse counter, and the output the input of which is connected to the output of the first pulse counter, with the input of the buffer device, a frequency divider is inputted, the input of which is connected to the second output of the reference frequency generator, and the output is connected to the input of the second counter ka pulses, two elements And, the third pulse counter, the input of which is connected to the output of the frequency divider, the counting input - with the output of the first element And and the installation input minus the unit of the first pulse counter, the input of which is set to zero which is connected to the output of the second element And and a decoder, the input of which is connected to the output of the third pulse counter, and the direct and inverse output to the first inputs of the first and second And elements, respectively, the second inputs of which are connected to the output of the buffer device.

The drawing shows schematically a digital frequency multiplier following them) pulses.,.

It consists of a reference frequency generator 1, first counter 2 HivraynbcOB

block 3 of code comparison, buffer device 4, second pulse counter 5, memory block 6, frequency divider 7, third pulse counter 8, decoder 9, first and second elements AND 1O, 11.

The reference frequency generator 1 is connected in series with the first pulse counter 2, the first input of the code comparison unit 3, the buffer device 4. The second pulse counter 5 is connected in series with the memory block Q with the second input of the code comparison unit 3. The synchronization inputs of the second counter 5 pulses, memory block 6, frequency divider 7 are connected to the input bus. The reference frequency generator 1 is also connected to a frequency divider 7, the first output

which is connected with the second counter 5 pulses, and the second with the third counter 8 pulses. The output of the third pulse counter 8 is connected to ceshifratoprom 9, the direct and inverse outputs of which are connected respectively to the first inputs of the elements I, X, 11. The output of the buffer device 4 is connected to the second inputs of the elements 10, 11, which outputs are connected to the input of the installation to zero and the installation input minus the single chips of the first counter is 2 pulses, respectively, 1 o. Input installation minus the unit of the first counter 2 pulses connected to the counting input of the third counter 8 pulses.

The operation of the proposed device is carried out as follows.

Signals are input to the device; in the form of narrow pulses, the second counter of 5 pulses, the healer 7 at the frequency, and also the code transfer occurs; contained in the second counter 5, before the arrival of this pulse, into memory block 6, and the code contained in frequency divider 7 has a third, third pulse counter 8. For this, frequency divider 7 should be performed on the basis of a digital overflow pulse counter. The code from memory block 6 is fed to one input of code comparison unit 3, the second input of which receives the code from the first counter 2 pulses, filled with reference frequency generator 1, which also goes to frequency divider 7. The signal passing through the frequency divider 7, from the reference frequency generator 1 to the second pulse counter 5, serves to form in the latter a code proportional to the input frequency period to be multiplied. Elok 3 code comparison generates a pulse signal & moment of equality of codes at its inputs. This signal is fed through the buffer device 4 to the inputs of the elements AND 10, 11. If there is a non-zero code proportional to the measurement error of the period by the second counter of 5 pulses, in the third counter there are 8 pulses from the decoder. 9, the resolving potential is fed to the input of element 11. At the same time, the output signal of the buffer device 4 is fed to the input of the installation of the first counter 2 impulses, sets the last to the minus one state and to the input of the third Counter 8 pulses, whose operation is organized into the subtraction. Thus, there is an increase in the period of the signal with

Claims (1)

Claim A digital pulse repetition rate multiplier comprising a reference frequency generator, the first output of which 79–99 6 is connected to the input of the first pulse counter, a memory unit, the input of which is connected to the output of the second pulse counter, and the output through the block is equal; code, the second input of which is connected to the output of the first pulse counter, with the passage of the buffer device, characterized in that, in order to increase the accuracy of frequency multiplication, 10 a frequency divider is introduced into it, the input of which is connected to the second output of the reference frequency generator, and the output with the input of the second pulse counter, two elements And, the third pulse counter15 ow, the input of which is connected to the output of the frequency divider, the counting input - with the output of the first element And and the input y with - minus one unit of the first pulse counter, the input is set zero, which is connected to the output of the second AND element, and a decoder whose input is connected to the output of the third pulse counter, and the direct and inverse outputs with the first inputs of the first and second AND elements, respectively, whose second inputs are connected to the buffer output devices.