SU560360A1 - Device for demodulating frequency-shifted signals - Google Patents

Description

one

The invention relates to radio engineering and can be used in frequency modulated receiving devices.

A device for demodulating frequency-manipulated signals is known, comprising a series-connected low-pass filter, a pulse shaper, a shift register and an inhibition element, as well as a clock pulse generator connected to the synchronization input of the shift register, the outputs of all bits of which, except the last, through the first the adder is connected to the prohibiting input of the prohibition element, and the output of the first bit of the shift register through the corresponding elements AND is connected to the inputs of two counters, the outputs of which and the output barring member connected to the second input of the adder whose output is connected to the reset inputs of counters 1.

However, the known device has a low room stability.

The purpose of the invention is to increase the noise immunity.

For this purpose, a device for demodulating frequency-manipulated signals, comprising a series-connected low-pass filter, a pulse shaper, a shift register and an inhibition element, and a clock pulse generator connected to the shift register synchronization input, outputs

all bits of which, except the last one, are connected via the first adder to the inhibit input of the inhibit element, and the output of the first bit of the shift register through the corresponding elements AND is connected to the inputs of two counters whose outputs and the output of the inhibit element are connected to the inputs of the second adder whose output is connected To the counter reset inputs, serially connected signal-to-noise ratio meter and a switch, the output of which is connected to the control inputs of the counters, are input, while the input of the signal ratio meter / the noise is connected to the input of the low-pass filter, and the outputs of the corresponding bits of the shift register are through the input elements OR are connected to the other inputs of elements I. The drawing shows a structural electrical circuit of the proposed device.

The device contains; and a serially connected low-pass filter (LPF) 1, driver 2 pulses, shift register 3 and prohibition element 4, as well as a generator of 5 clock pulses connected to the input

synchronization register 3 shift. The outputs of all bits of the shift register, except the last, through the first adder 6 are connected to the inhibit input of the prohibition element 4, and the output of the first bit of the register 3 shift through the corresponding elements And 7, 8 connect, respectively, to the inputs of two counters 9, 10, the outputs of which the output of the prohibition element 4 is connected to the inputs of the second adder 11, the output of which is connected to the reset inputs of counters 9, 10.

The device also contains serially connected signal-to-noise ratio meter 12 and switch 13, the output of which is connected to the control inputs of counters 9, 10. The signal-to-noise ratio meter input is connected to the low-pass filter input 1, and the outputs of the corresponding shift register bits through the entered elements OR 14, 15 are connected respectively to the other inputs of the elements And

7 Q /, b.

The device works as follows.

The incoming signal together with the noise simultaneously goes to the signal-to-noise ratio meter 12 and to the input of the low-pass filter 1. The output signal of the low-pass filter 1 is fed to the driver 2, which converts a sinusoidal signal into a sequence of pulses following the same repetition frequency the pulses are at least one hundred.

For each positive half-wave, a unit is recorded in shift register 3, and by the time the next unit arrives, the previous one is advanced by pulses of the clock pulse generator to a certain stage of the shift register. The number of stages is chosen so that for one period of the highest received frequency, the pulses simultaneously arrive at two inputs of the coincidence cascade 7, and at the lowest, only at the inputs of the coincidence cascade 8. Thus, the pulses enter counters 9, 10 depending on the received frequency. These counters are set to their original position by prohibiting element 4 and adders 6, I. Prohibiting element 4 outputs pulses if not a single unit is written after the pulse leaves the shift register 3, i.e. there is no signal at the output of the first adder 6. The second adder 11 receives pulses from prohibition element 4 and from the outputs of counters 9, 10. In the absence of a signal and the presence of a chuma, counters 9, 10 are reset once the duty cycle between pulses formed by noise exceeds the delay time of the shift register 3. When on Ichii reset pulse signal supplied after filling only one of the counters 9, 10. In order to receive the correspondent, in which the transmitter frequency differs from the receiver frequency

g% are combined l registry taps

For example, elements OR 14, 15. The division ratio of counters 9, 10 may vary depending on the signal-to-noise ratio in the channel. The signal-to-noise ratio meter 12 through the switch 13 changes the counting coefficient of the counters 9, 10. As the signal-to-noise ratio deteriorates, the counting coefficient of the counters 9, 10 increases.

The technical and economic efficiency of the invention is to increase the reliability of signal detection, especially with poor signal-to-noise ratio and large input signal detuning.

Claims (1)

1. Auth. St. No. 399999, cl. H 03 D 3/04, 1973 (prototype). Bbtxodz o