SU484517A1 - Number Comparison Device - Google Patents

Description

Let, for example, the number (fig. 2 d), and the number (fig. 2 d) in the five-dimensional system.

Before the start of operation, the triggers 4 and 5 are set to the zero state by a bus signal Reset 13. At this inverse output of the trigger 5, a single potential appears. The high-order signal from input 9 of number B (fig. 2 d) does not change the state of trigger 4, and the signal of number A (fig. 2e), coinciding with the sequence (fig. 26), flips trigger 4 into one state ( Fig. 2 g), the signal from the output 8 of the clock signal generator 6 through the element "I 2" sets the trigger 5 to one state (Fig. 2h). In this case, a signal is produced, which does not change in the future for any values of the lower bits.

Consider another case where (Fig. 2 and), and B 23. In this case, the signals of the higher bits A and B are the same, and since the signal at the input of the unit to the one state of the trigger 4 ends earlier, the trigger 4 remains in state "O and the signal output element" And 2 does not appear. The signal of the second digit of the number A flips trigger 4 into one state, according to

the signal of the number B will again return it to "O" and the state of the trigger 5 will not change, which corresponds to the value.

The described scheme can be used in devices with a phase-impulse principle of information representation.

Subject invention

A device for comparing numbers, comprising a clock signal generator, triggers and AND and OR elements, characterized in that, in order to simplify the device, there is a first input bus through an AND element, the other input of which is connected to the first

clock generator output, is connected to the trigger setup input in one state, and its zero setup input is connected to the output of the element IL Pi, whose inputs are connected to the second input bus and the reset bus, direct trigger output through another element "And, the second input of which is connected to the second output of the clock signal generator, is connected to the installation input in the unit

the state of another trigger, the input of the installation in the zero state of which is connected to the bus "Reset.

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Reset h 1J

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FIG. 2