SU1566339A1 - Device for presentation of graphic information - Google Patents

Abstract

The invention relates to data processing devices and can be used in devices for outputting information from a computer to a television receiver screen. The purpose of the invention is to increase the speed and accuracy of the device. This is achieved by the introduction of a converter 2 of codes, a decoder 14, a shift register 19, elements OR 8 and 9, an element 16 EXCLUSIVE OR, a multiplexer 17, a pulse counter 22, a driver 20 and a driver for filling the image contour pulses and the corresponding functional links . The invention allows the color or luminous body of a contour to be filled with any complex configuration without preliminary processing of information. 2 hp ff, 7 ill.

Description

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 The invention relates to devices for processing data and can be used in devices for outputting information from a computer to a television receiver screen.

The purpose of the invention is to increase the speed and accuracy of the device. : FIG. 1 shows a block diagram of the proposed device; 2 shows an i block diagram of a control unit; in fig. 3 shows the control pulse driver circuit; in fig. 4 is a diagram of a pulse imaging pulse generator; in fig. 5 and 6 - time diagrams of the device; in fig. 7 - examples of the combination of information on two television lines, defining the beginning and end of the filling of the contour (a), and examples of the contours with the addition (b, c, d) 0

The device contains a block of 1 RAM, a converter of 2 codes (coordinates X and Y to the address), first 3 and second 4 counters of coordinates (X, Y), elements OR 5-9, counters 10 and 11 addresses (X, Y), calculator 12, control unit 13, decoder 14, register 15, EXCLUSIVE OR 16 element, multiplexer 17, first 18 and second 19 shift registers, control pulse driver 20, image fill pulse pulse generator 21, video pulse counter 22, video monitoring unit 23 (television receiver).

The control unit 13 contains the triggers 24-32, the AND-OR element 33, the shift register 34, the AND elements 35-39, the OR elements 60-68. and the EXCLUSIVE OR element 69. The positions 70-95 denote the inputs and outputs of the block 1, respectively.

Shaper 20 control pulses contains elements OR 96-98, elements AND 99-105, triggers 106-108, element AND-OR 109, and element NO 110. The positions 111-127 denote the inputs and outputs of the driver

Shaper 21 pulses for filling the image contour contains an element NOT 128, elements AND 129-133, elements OR 134-136, and triggers 137-139. Positions 14-0 and 141 denote the corresponding outputs of the imager.

Each 1 circuit to be filled in parallel with the recording in the regeneration memory block (not shown) of the television device (block 23) is recorded in block 1, which is preceded by

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five

0

five

0

35

40

45

50

55

must be reset to zero. Then from block 1 it is sequentially read into registers 18 and 19 information at two addresses corresponding to parts of the television lines located one under the other. The presence of at least one unit in register 18 (upper row) is then analyzed. If there are no units, one is added to the address in counter 10 (addresses X) and the next two parts of two television lines, one under the other, are read. If units are present, a synchronous cyclic shift of information in registers 19 and 8 is performed with analysis after each shift of the three situations shown in FIG. 7a. The presence of a situation is remembered on trigger 137 of driver 21, which records the beginning or end of filling. The odd occurrence of the situation indicates the beginning of filling in the background information of the upper line read, even the one about the end.

From the moment of an odd occurrence of a situation, the writing of units in all bits begins by applying a single signal (single output of trigger 137) to the input of the shift of the upper line register 18 until an even situation occurs. The output signal 126 from the situation presence 126 is generated in the driver 20, in which the triggers 106 and 107 during cyclic shift, sequentially shifted bits from registers 18 and 19, respectively, are memorized. With the help of elements 103-105, the situations shown in fig. 7a. In order to eliminate errors when filling the contour for the cases shown in FIG. 76, the trigger (138) is used, which is set to 1 at the same time as the trigger 137 (Fig. 76). Then, if the third situation shown in FIG. 7a is fixed at the next shift, trigger 138 holds the trigger 137 (start / end) in its original state until the first mismatch of two units (no third situation in FIG. 7a). The bottom of the circuit shown in FIG. 7c, trigger 138 will hold trigger 137 in the terminate state.

If, after a full cyclic shift on registers 18 and 19, the end situation does not appear, then from block 1 the following ones are read into registers 18 and 19

parts of two television lines. In the absence of at least one unit in the newly read information and if the trigger 137 is in the unit (beginning through multiplexer 17, block 23 records the word with units in all bits at the address coming through the element OR 9 from counters 10 and 11.

This writing of words with units in all bits continues until the unit appears in register 18 after the next reading of information from block 1. Then the cyclic synchronous shift of information in registers 18 and 19 is again performed, while in register 18, units are shifted to even appearance situation (end). Operation in this mode continues until a signal appears at the output 90 of the overflow of counter 11 (address Y), which stops the device and enters the VM as a ready signal.

In addition, when recording a contour in block 1, one should not record vertical contour ejections of the thickness in one sample (Fig. 7d), since in this case there will be no end of filling. When recording such an outlier, information is written twice (two vectors) at the same addresses. When you re-write to the same address, the information is erased and the condition for erasure is the presence of an inflection (change of the Y sign), the absence of a change in X, and the presence of information in the given memory location.

The device works as follows.

The computer is prepared for operation under the control of the computer. After the device has been reset (the Setup Setup signal is not shown), the computer starts the recording of the contour recording with input to, 75, which sets 1 trigger 24, and OR 67 sets in 1, a trigger 30, which permits the passage of frequency (input 89) to the shift register 34, generating a sequence of signals from which a timing diagram of the modes of operation is formed. In Null mode (Fig. 5a), zeros are written sequentially at all addresses of block 1. Triggers 31 and 32 generate timeline signals.

0

recording information in block 1. After recording information in block 1, the seventh clock cycle, passed through the element I 35, and cleared the next address of block 1 (exit 70). In addition, by the seventh clock cycle through the AND-OR element 33, the thrush ger 30 (frequency prohibition) is reset and the device ready signal is sent to the VM.

In the Record mode, to the computer drive after receiving the Ready signal, the device provides information about the contour specified in the form of initial coordinates 5 and vectors, which the calculator 12 converts to increments in one discrete on axes X and Y. Coordinates that are associated with their control signals are received at counters 3 and 4 (X and Y). The signal 74, which enters the device at the beginning of each vector, resets the trigger 24 on the falling edge, sets the element OR 68, 1 trigger 29, passes through element 58, sets 1 trigger 27 and through element 67 67 sets the trigger 30 chart.

0

five

thirty

five

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five

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five

In addition, the same signal on two triggers 25 26 records the sign of the first vector, which is fed to input 76. When processing subsequent vectors, the sign Y of the previous vector is rewritten from trigger 25 to trigger 26, and the sign of the new vector is remembered in trigger 25. of these flip-flops, the element of the ECGLOCKING OR 69 generates an inflection signal. (change sign Y) This signal arrives at AND 57, the second input of which receives a signal at input 77 from calculator 12 - no change of X. The signal at output 92 of the element 57 enters the control input of multiplexer 17, the information inputs of which receive information from the element OR 8, if the current information needs to be added to the previously recorded (before each entry from block 1, the word is read to this address and the current point is added by OR to previously recorded information) from the EXCLUSIVE OR element, or if the current point needs to be erased. Thus, from block 1, the vertical contour ejections are erased. A time diagram of the operation of the device 715f.

The recording mode of the circuit is shown in FIG. 56 „

In the recording mode of the circuit, the device operates as follows. After the signal arrives at the input 74 accompanying the vector information, from block 1 to the address located on counters 3 and 4, information is read and received into register 18. Then the newly formed information described in this way goes through multiplexer 17 to input of block 1 and control signals generated on trigger 32 (enable signal) and trigger 31 (write / read signal) - are recorded in block 1. Next, the fourteenth clock cycle, passing through AND 48 and OR 67 elements, stops the generation of the timing diagram and in the lower order The shift register 34 through an AND-OR 33 writes 1. Simultaneously with the information recording unit 1 at the same address from the register 18 via the OR gate 7 (multiplexer) information is recorded in the RAM of the television device. The cycle of writing to the RAM of a television device is longer than the cycle of recording in block 1.

At the end of the recording, the television device's RAM from the television device receives a signal at input 78 (Answer), which flushes trigger 29 through AND 56, OR 66 and 67, flushes trigger 30, and also enters calculator 12 to allow generation and output of information about next current point. The signal that generates this information in the calculator also goes to the device input 73 and, through the elements AND 55 and OR 68, sets 1 trigger 29, and also through the elements AND 55, OR 66 and 67, starts the generation of the time diagram. In this mode, the device operates before the signal from input device is received at input 79 (End of loop recording). which sets the trigger 27 into О, the trigger 28 into 1, and through the element OR 67 it starts the generation of the time diagram (Fig. &).

At the zero address, block 1 reads a part of the first television line, is equal to the word width of block 1, and is written using a signal at input 83 to register 18 and then with a signal from output 86 added C98

1 to the address counter 11 (thereby moving to the next television line), a portion of the second television line is read.

line and is written using the output signal 84 to register 19.

The eleventh time passed and the element 42 (signal at output 72) enters the input of element 39 of the imaging unit 20, the second input of which receives a signal of at least one unit in register 185 produced by the element OR 96 „Ztot

the same signal from the output 119 is fed to the control input of the multiplexer 17 to allow passage in block 3 from the register 18. From the output of the element AND 99 the signal passed through the element OR 91,

 sets to 1 the trigger 108, which stores the presence of a unit in the register 18, and goes to the shaper 21 (output 125) for installation via the OR element 136 of the trigger

5 139 start of the shift counter, as well as through the AND-OR elements 109 and HE 110 (the signal from output 124) goes to the element AND 129 of the former 21 as a signal for analyzing the presence of a situation. A signal is received from the output 126 to the input of the element AND 129 The presence of the situation of the element OR 98 of the driver 20. When these signals coincide and if the trigger 138 is set to O, it is set to 1 trigger 137. From the single output of trigger 137, through the element OR 135, the output from 140 goes to the input of the shift of the register 18, to the second input of the element OR 135 a signal is received from the input 111 (the low-order bit of the register 18) for the organization of cyclic shift.

Next, the thirteenth cycle, pass through the element And 52 (the signal from the input

5 87) is fed to the input 1 of the counter 11 to return the address of the first television line of the two analyzed. The same signal from input 87 is fed to the inputs of the elements AND 100 and 101 of the driver 20 for analyzing the state of the trigger 108. If the trigger 108 is in position 1, the element AND 101 generates a signal at the input 71, which, having passed through the element OR 67, stops generation of the time diagram, since the synchronous shift of registers 18 and 19 has already begun and the count count) —the number of shifts of the counter 22, Trchtger 139 work5

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50

55

one

em in the counting mode and passes the clock frequency through the element AND 133 (signal at output 85) to the shift of registers 18, 19 and the trigger 22 or through the elements AND-OR 109 and NOT 110 (signal at input 124) to analyze the presence of the situation. The operation of the trigger 139 in this mode continues until the arrival of the signal from the overflow input 94 of the counter 22, which, having passed through the OR element 97, resets the trigger 108, and also starts in the control unit 13, where it sets the trigger 29 for the television device. Upon completion of the recording of information from block 23, a signal is received at input 78 (Response), which resets trigger 29, sets trigger 1 for frequency 30 to generate a timing diagram and, having passed through element 56, adds one to the memory address. If trigger 108 did not detect the presence of units in register 18, then the thirteenth cycle (signal at output 87) of block 13, passed through AND 102 (signal at output 122), goes to shaper 21 to analyze the state of trigger 137 if trigger 137 is in the position of the beginning of filling the circuit, then the signal from the output 122 passes through the element AND 131 enters the block 13 for installation through the element OR 68 of the trigger 29 and the block 23.

In such a situation, a word with units in all bits is recorded in the regeneration memory of a television device. If trigger 137 is at the end-of-loop position, then from output 122, passing through element 132, a signal (output 141) adds one to the block address 1 (counter 10) and the next parts of the two television lines begin to be read and analyzed. Operation in this mode continues until a signal is generated at the output 90 of the overflow of the counter 11, which, through the OR 67 element, resets trigger 30 (frequency prohibition) and enters Computer as a ready signal device.

Claims (3)

1. A device for displaying screening information containing first, second and third OR elements, first and second address counters, 39 ten five 5 ./ 0 5 0 Q with n five the main memory unit, the first and second coordinate counters, the computer, the first SLEDGE of which is connected to the control input of the register, the first shift register, the output of which is connected to the first input of the third OR element, the output of which is connected to the first information input of the video monitoring unit, and the control unit , different in that, in order to improve the speed and accuracy of the device, it contains a decoder, the input of which is connected to the output of the first coordinate counter, and the output - to the information input of the register, The op is connected to the second input of the third element OR, the second shift register, the fourth and fifth elements OR, the EXCLUSIVE OR element, a multiplexer, a code converter whose inputs are connected to the outputs of the coordinate counters, and the output to the first input of the fifth element OR whose output connected to the second information input of the video monitoring unit and the address input of the RAM, the first output of the address counters is connected to the second input of the fifth OR element, the second output of the first address counter is connected to the first input the house of the second OR element, the output of which is connected to the counting input of the second address counter, the first output of the calculator is connected to the installation inputs of the address counters, the reset input of the first shift register and the input signal of the initial installation of the control unit, the first input of the stop signal of which is connected to the second output of the second address counter which is the output of the device readiness signal, the pulse counter, the driver of the control pulses and the driver of the filling of the contour of the image, the first you the stroke of which is connected to the synchronous inputs of the control pulse generator and the control unit and the counting input of the pulse counter, the output of which is connected to the reset input of the control pulse former and the input start signal of the information of the control unit, the second input of the stop signal of which is connected to the first input control pulse generator, the second output of which is connected to the control input the pulse shaping pulse generator, and the third output - to the third input of the third OR element, the fourth input of which is connected to the first output of the control unit, the second output of which is connected to the control input of the video control unit, the output of which is connected to the input of the response signal of the control unit and the control input of the calculator, the third output of the control unit is connected to the first control input of the driver of the control pulses and the subtractive input of the second address counter, the fourth output - with the input of b the initial setting of the control pulse driver, the fifth output from the control input of the second shift register, the sixth output from the control input of the first shift register, the seventh output from the control input of a multiplexer, the eighth output from the second input of the second element OR, the child's output is with the first input of the first element OR, the control input of the control unit is connected to the second output of the calculator, the third output of which is connected to the clock inputs of the control unit and the driver of the control pulses which input is connected to the second output of the pulse filling pulse generator of the image, the third output of which is connected to the second input of the first OR element, the fourth output to the input of the control signal of the control unit, the fifth output to the first information input of the first shift register, second the swarm of whose information input, the information input of the first shift register and the input-output of the RAM block are connected to the output of the multiplexer, whose information inputs are connected to the outputs of the corresponding but the fourth OR element and the EXCLUSIVE OR element, the first inputs of which are connected to the register output, and the second inputs to the output of the first shift register connected to the information input of the imaging pulse generator and the first information input of the control pulse imager, second information input which is connected to the output of the second shift register, the information input of the control unit is the first information 5 0 5 0 s 0 5 0 five The device's input, the calculator's input-output is the device's output-input, the fourth calculator's output is connected to the counting inputs of the coordinate counters, whose information inputs are the second and third information inputs of the device, respectively, the tenth output of the control unit is connected to the write-read control input memory block „ 2. The device according to claim 1, wherein the driver of the control pulses contains the first OR element, whose inputs are the first information input of the driver, and the output is connected to the first input of the first element AND and is the third output of the driver, the control input of which is the second input of the AND element, the output of which is connected to the first input of the second OR element, the second input of which is the reset input of the driver, the first, second and third triggers, the output of the second OR element is connected to the R input the third trigger, the unit output of which is connected to the first inputs of the second and third elements AND, and the zero output with its D input and the first input of the fourth element AND, the output of the third element AND is the first output of the imaging unit, the clock input of which is the second input the second element And, and the inputs of the initial setup signal are the second inputs of the third and fourth elements AND, the outputs of the first and second elements AND are connected to one of the inputs of the element AND-OR, the other input of which is the synchronizer input of the driver, and the output connected to the input of the HE element, the R inputs of the first and second triggers are the second control input of the driver, the first input of the first OR element is connected to the D input of the first trigger and the first input of the fifth And element, the single output of the first trigger is connected to the first inputs of the sixth and the seventh And elements, the second inputs of the fifth and seventh And elements are connected to the single input of the second trigger, the D input of which is the second information input of the driver, which is connected to the second input of the sixth element And 13 the outputs of the fifth, sixth and seventh elements AND are connected to the inputs of a third of its element OR, the inputs of the second, fourth, first and seventh elements of AND, the third element OR, and the element are NOT the second output of the former. 3. The device according to claim 1, characterized in that the pulse shaper of the image contour contains five elements AND, the output of the first element AND is connected to the R input of the first trigger and the first input of the first element OR, the second input of which is connected to the output of the second element AND and the output is with the R-input of the second trigger, the zero output of which is connected to its D-input and the first input of the first element I, and the single output to the first input of the second element And, the second input of which is connected to the output of the element NO, the unit output of the first trigger is coupled to first inputs of the second OR gate and the third AND gate, whose output is the output of the fourth, zero output A6J3914 the first trigger is connected to its D input and the first input of the fourth AND element, the output of which is the third output of the driver, the fifth output of which is the output of the second OR element, the second input of which is the second information input of the driver, the third trigger, The JQ R input of which is connected to the output of the third GLI element, and the zero output is connected to its D input and is the second output of the former, the unit output of the third flip-flop 15 is connected to the first input of the fifth And element, the output of which is the first output of the former, the second inputs of the third and fourth And elements are the control input 20 of the former, which is connected to the second input of the first element AND, the third inputs of the first and second elements AND are combined and connected to the control input of the former, 25 which is connected to the first input of the third element OR, the inputs of the third element OR and the fifth element AND are combined and connected to the control input of the driver. thirty 7P "  ™  l JtggJlJ J JlJlJ JtlJlJ ruijTrLnrL  . 78 5 U S3 JirijirmjTJTriJiJTlnj 71 IT lies Wt No. isa Figb -and IT } FffftHI 2JЈ te7