JPS58137708A - Frequency distribution counter circuit - Google Patents

Abstract

PURPOSE:To enable long-term continuous measurement by forming a counter circuit into the two-stage constitution of the 1st counter circuit which operates at a high speed and the 2nd counter circuit consisting of plural sets of counter circuits to which the contents of the 1st counter circuit are transferred. CONSTITUTION:The 1st counter circuit 5 which can operate at a high speed counts the generation rates of input data. When the count content of the circuit 5 attain 2<n>, said content is accumulated in one of plural pieces of cumulation circuits 69 selected by an input distribution part 20. The other circuits 69 except the circuit 69 under cumulation output the frequency distributions 57 selected successively according to the sequence predetermined by an output change-over part 26. The circuits 69 are constituted of RAMs and counters.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frequency distribution counting circuit used when calculating the statistics of the frequency of occurrence of data values (hereinafter referred to as data) of various encoding devices continuously in real time for a long time. . Conventionally,
To count the frequency of data occurrence in real time, use %J1
The configuration was as shown in Figure 1. In other words, the input data was decoded by a decoder 1 and the number of stitches was calculated by each counter 2 corresponding to the data.
When the number of bits of data is large, such as when two counters 2 are required, a large number of constituent elements are required, so this is not a realistic configuration. Also, the expanded data is temporarily stored in the memory 3 with the configuration shown in Figure @2.

Thereafter, a method was used in which the contents were successively outputted and the successive contents were incremented by 1 in the addition processing circuit 4 to increase the frequency and then written into the memory 3 again. In order to lengthen the measurement time for both, in the example in Figure 111, increase the number of digits of counter 2, or increase the number of digits of counter 2.
In the WJ example, it is necessary to increase the word length representing each data in the memory 3, which leads to an increase in the scale of the device.

Furthermore, in either example, continuous measurement is not possible during high-speed operation because the reading time of the counting results is not guaranteed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a frequency distribution counting circuit that is high-speed, has a simple configuration, and is capable of continuous operation over a long period of time regardless of the measurement time length.

The present invention comprises a counting section that counts the number of occurrences of each value of input data, and a buffer memory section that transfers the value of this data when any value of this input data occurs a predetermined number of times. 1 counting circuit, the frequency of the value of the data transferred from the first counting circuit is counted, the counting unit of the Australian number set, and the value of the transferred data is calculated by the counting unit of the augend set. an input distribution section that selects one of the counting sections and supplies it to the selected counting section; and an output switching section that sequentially switches the unselected counting sections in accordance with a predetermined order and outputs the frequency of the accumulated data value; A frequency distribution counting circuit characterized by comprising a second counting circuit configured with a control section that controls selection in the input distribution section and switching in the output switching section. Explain. The first counting circuit is jl
Since it operates as an adapter for 12 counting circuits, high-speed operation is required, but the counting frequency may be relatively small. Transfer to the road. Therefore, the first counting circuit can equivalently reduce the transfer speed to 1/2n. The second counting circuit has a plurality of sets of counting sections that count the frequencies transferred from the first counting circuit, and one of them is used exclusively for counting, and the others are used exclusively for external output. A fixed time unit KI [
Next, performing input distribution and output switching allows continuous measurement at any length.

As described above, in the present invention, by using the first meter k circuit as a high-speed adapter, it is possible to respond to higher-speed data Kl' than K, and a random access memory (
By using RAM (hereinafter abbreviated as RAM), the increase in hardware due to changes in the number of input data is small, and by using multiple counting units for counting only and for outputting, alternating their roles at regular intervals. Continuous measurement possible for long periods of time
It is possible to obtain the effect of reducing

Embodiments of the present invention will be described in detail below with reference to the drawings.

Figure tIK3 shows a block diagram of the frequency distribution counting circuit of the present invention. Frequency distribution meter of the present invention! ! As shown in the figure, the circuit has a two-stage configuration including a first circuit & circuit 5 capable of high-speed operation and a second circuit 6 which does not necessarily require high-speed operation. Data 27 in the first stitch count circuit 5
2n times, and when that value is reached, the second tt
The data value is transferred to the number circuit 6. In this way, the second
The counting speed in the counting circuit 6 is equivalently reduced to 1/2 speed. The counting circuit 6 of fH2 has a plurality of sets of counting functions having the same configuration, and is used for counting only and for outputting. That is, the second meter k circuit 6
The data transferred from the counting circuit 5 of the input distribution unit 2
0, only one of the plurality of accumulation circuits 690 is selected to accumulate data. Further, the other accumulator circuits 69 except for the O accumulator circuit 69 are sequentially selected by the output switching section 26 in accordance with a predetermined order and output the frequency distribution 57. The accumulation circuit 69 is composed of a RAM and a counter, and at least two sets are used.

Next, a specific example of the first counting circuit 5 is shown in FIG.

As shown in the figure, the first total Ila path 5 is composed of a control section 59.8 mm, an M section 60, a counter section 611, and a buffer RAM section 62. The control unit 59 is composed of a '1'' L-IOL level converter 7, an internal clock generator 8, and a control circuit 10. In this example, the first counting circuit 5 is a 10L circuit for high-speed processing. The 8-bit input data 27 consisting of 0, the readout 28, the clear signal 29, and the start signal 30 indicating the counting execution section are '!'I'L-1.
The level is converted by 10L level conversion 1!7. The control circuit 10 uses the internal clock 31, output clock 28 and start signal 30 generated by the internal clock generator 8 to input a load signal 32 to the presettable counter 9 of the RAM 560, an enable signal 67, a clock 31,
A seed signal 34, an enable signal 35, and a 31% buffer for the counter 12 constituting the counter @61.
Write signal 6 to write signal generator 14 of system Mi 162
8. Write address counter 15% Read address counter 16° Glue to read counter controller 17 P vine 31
is supplied. These signals are valid only when the start signal 30 is high level, and when the level is Tatsu level, the RAM 5
60 and buffer RAM section 62. The RAM 1160 is a presettable counter 9. R.A.
It consists of MI1. Buri Nanatsuta Pull Counter 9
The input data 27 is temporarily held by the load signal 32 given from the tube control circuit 10, and sent to RAMI 1 as the address 33 in the buffer RAM M1 of the buffer RAM section 62.
8 bits are given to B as data 33. RAMI
1 reads the contents of the input address 33 and outputs it to the counter section 61. It is composed of a counter 12, and the data from the counter 12dRM M11 is taken into the counter 12 by the stomach signal 34, and the enable signal 35 is counted up by +1 by 1:Iy#31 and outputted to IIMI1 as 4 bits. R5Mll completes the operation of increasing the write frequency by 1 with the write signal 36 to the same address as the previous address.

2'==e l Count the frequency up to 5 states using 4 bits of 0 from the company M11. Buffer RAM Iku62Fi Buffer RAM13. Write signal generator 14. Write address counter 15, successive address counter 16, II! Output address counter control @17, comparison 1rF18.10
It is composed of an L-'I''I'L level converter 19.

The write signal generator 14 writes to the buffer M13 only when the carry signal 37 from the counter 12 and the write signal 68 from the control unit 10 match and the γ error signal 43 from the comparator 18 is at high level. It is output as a signal 38. At the same time, to the write address counter 1s,
It is output as an enable signal 38. Write address 3
90 15 counts up with the clocker 31 only when the enable signal 38 comes, and outputs the write address 39 in 4 bits to the buffer RM M13 and the comparator 18.

The read address counter 16 normally performs continuous count-up and compares the read address 40 with the 4-bit buffer M13 and outputs it to the 1) 18, but when an enable signal 42 is received from the read counter controller 17, I! stops counting when the second counting circuit 6 finishes writing. The outgoing address is kept as is. Buffer 7 RAM 1 B has data 33 at write address 390
8 pits are written by the write signal 38 and the data is stored. The transfer of 1112 to counting U path 6 is performed by providing read address 40. Buff 7R
The AM 13 has a memory capacity of 16 words in order to prevent data loss that may occur during the writing time of the 20th counting circuit 60.

The comparator 18 has a write address 39 and a read address 4.
Compare 0 and expand when both are equal, @2O counting circuit 6
It outputs the write control signal 41 to the read address counter control l117 to prohibit writing to the buffer M13, and to execute the write when both of them are out of order, and reads the contents of the buffer M13. In order for new data to be written during the request, an alarm signal 43 is generated and the write signal generation@140 operation is prohibited. When the read address counter controller 17d receives the write control signal 41, the tartar 31 starts operating.
#To the slight U path 6 O Kurotsuta a) 44, Tartuta (2) 45
occurs]! OL-'I"1' is output to the L level converter 19. In addition, the 20th needle setting circuit 6 outputs 1 to prevent the address counter 16 from counting up one after another in response to a write request.
Tatsuta α)44. Address counter 1 outputs a boolean signal 42.
I am trying to output to 6. MOL-"1"t"L level converter! 9 is data 46 (8 bits), tartuta Q
)44. Shooting e) 45% clear signal 29. Start Confucian No. 3゜'! ``!''' Next, a specific example of the second counter circuit 6 is shown in FIG. A case where there are two accumulation circuits 69 will be explained.As shown in the figure, the second counting circuit 6 includes an input distributor 20, a control section 21, a 140.1;
2, a counter (1) 24.1Ilj2, an accumulator circuit 69, a memory M(2) 23, a column yfi($) 25, and an output switching circuit 26.

The control unit 21 receives the information transferred from the gt counting circuit 5.
The input distributor 2 is activated by a clear signal 29 indicating the switching timing of the accumulator circuit 69, and a star F signal 30 indicating the counting execution period.
Memory select signal to 0 51.8 mm M(1) 22.8
Write signal 49°49' to the programm M body) 23, counter (
1) 24, Counter (2) 2 S Head OD signal 4
7.47' and enable signal 48°4811 clock (
2) 44, Output selection to output switch 26! ) signal (1
) 53, output select signal @) S4, output select signal (3) 55, output select signal (4) 5@ is generated and supplied to each part. Data 46 and external 8-bit read address 52 are switched by memory select signal 51 to RAM (1) 22 and 15M (2) 23.
Be sure to give them separately, such as one as a write address and the other as a solicitation address.

When the input address is the write address 46, the memory M(1) 22 reads the contents of that address and outputs 16 bits to the read counter (1) 24. Counter (1) 2
4 inputs the data from 21M (1) 22 into the counter (1) 24 using the read signal 47 and the click (2) 44, and increases the count by +1 using the enable signals 4 and 8 and the click (2) 44. Outputs 16 bits to wing M(1)2m. Rum) [(1) 22 writes the data 50 to the same address as the previous address using the write signal 49 to update the data. □Also, when the read address s2 is input to the RAM (1) 22, the contents of the address are read out from the RAM (1) 22 and sent to the 16-bit output switch 26, causing the counter (1) 24a to operate. I'm trying not to do that. Similarly, KRAM (2) 2B and counter (Q) 25 are operated according to the applied p-do signal 47', enable signal 48', write signal 49' and data 50' from counter (2) 25. 1) It operates exactly the same as 24.

, RAM (1) 22% RAM (2) 23 has a 16-bit configuration, so the read 16-bit data is sent to the output switching circuit 26 as output select signals (1), (2), (3), (4), 53
．． RAMC on the read mode side according to 54.55.56)
Is the content upper 8 bits and lower 8 bits? ) is divided into two times and sent as 8 pins (output 7 and 57).The above-mentioned operation is executed only when the start signal 30 is at a high level, and when it is at a low level, aRAMα) 22% RAM (2
) 23 is cleared by each signal. Further, the timing of the switching expansion clear signal 29 of the accumulation circuit 69 is such that it is switched each time it is input or when the frequency of occurrence within the interval of the clear signal 29 reaches 216 and 9.

Also, if the data speed is IMHs, an internal clock generator 58 is prepared in the second counting circuit 6 like allESll, and if the data speed is IMHs, for example,
The MIh level Q44 is generated and inputted to the spear multiplier 64, which is switched by the switch 65 to control s.
A total of $20 by supplying 21 Hetada Ivy 66'
If data is directly input to the Ik circuit 6, it can operate independently.

Furthermore, if the switch 65 is returned to its original state, it can be operated in a two-stage configuration, providing versatility.

In this way, according to the present invention, the two-stage configuration allows it to handle both low-speed events and high-speed events, so it can be used in a wide range of applications, and one circuit is simplified. By having multiple frequency distributions, the frequency counting of the input data is not interrupted even during the output time of the counting results to the outside, making it possible to operate continuously for a long time and making it possible to analyze the input data accurately without missing data. A counting circuit can be provided.

[Brief explanation of drawings]

Figure 1 shows the conventional method (1), and Figure 2111 shows the conventional method (
2) Fig. 3 is a principle diagram of the present invention, Fig. 4 is a detailed 1141kf vs. ivy diagram of an embodiment of the IjIO fourth counting circuit of the present invention, and Fig. 5) is a diagram of the second counting circuit of the present invention. 68 is a detailed diagram of the embodiment, and No. 68 is a diagram of a modified portion of the second embodiment. In the figure, 1... decoder, 2-'' counter, 3-'' page 9.4
- addition processing circuit, 5... first counting circuit, 6 - second counting circuit, 59... control section, 60° - RAM section, 6
1... Counter section, 62... Buffer RAM1l,
69″′ - Shows the accumulation circuit. Figure 1

Claims (1)

[Claims] A first comprising a counting section that counts the number of occurrences of each slight occurrence of input data, and a buffer memory section that transfers the value of this data when either the value of this person or the data occurs a predetermined number of times. a counting circuit, a plurality of counting units capable of counting the frequency of the data value transferred from the first counting circuit; an input distribution section that selects one of the counting sections and supplies it to the selected counting section, and an output switching section that sequentially switches the counting sections that are not selected in a predetermined order and outputs the frequency of the accumulated data value. A frequency distribution counting circuit comprising: a second counting circuit configured with a control section that controls selection in the input distribution section and switching in the output switching section.