SU1682997A1 - Data display unit - Google Patents

Abstract

The invention relates to automation and computing and can be used to build graphic information display devices, such as digital oscilloscopes. The purpose of the invention is to increase the speed of the device, which is achieved by introducing a counter of the X coordinate, a second register of the Y coordinate and the corresponding functional connections. The invention allows to display the form of the signal under study, to make marks at characteristic points of the graph and to change information on the screen at high speed, i.e. to produce displays in dynamics. 2 Il.

Description

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The invention relates to automation and computing and can be used to build graphic information display devices, such as digital oscilloscopes.

The purpose of the invention is to increase the speed of the device.

FIG. 1 shows a block diagram of the device; in fig. 2 - examples of the block diagram of the converter codes.

The device contains a control unit 1, a counter 2 coordinates X, the first 3 and second 4 registers of the Y coordinate, a multiplexer 5, a memory block 6, a converter of 7 codes, a shift register 8, an output register 9, an input register 10, a bus driver 11, a block 12 synchronization, frame and line sweep generator 13, video amplifier 14, cathode ray tube (CRT) 15. FIG. 1, position 16 is the microprocessor unit, position 17 is the microprogram control unit, position 18 is the control register of the microprogram control unit, and positions 19–22 are the clock generator, point counter, row counter, synchronization unit driver.

The device works as follows.

The firmware control block 17, which is a 16-clock signal distributor, continuously generates control signals that determine the operation cycle of memory block 6, which consists of two intervals: a constant occurring during the forward run of the horizontal and vertical scan of the training interval display information to perform image regeneration (during the reverse stroke there is no preparation interval) and the time interval for

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information is processed in memory block 6 by microprocessor block 16 as it is accessed.

In the preparation interval of the displayed information for regeneration, synchronization unit 12 determines the address of the displayed word in memory block 6 and accesses it via multiplexer 5 to read the next word (two bytes) of data, which is displayed on the CRT 15 in the next cycle. ZUR information is entered into shift register 8, with the help of which it is converted into a sequence of video signals input to video amplifier 14. By the time when register information 8 is sequentially converted into ide signals, the synchronization unit 12 together with the firmware control unit 17, prepares the next two bytes of information and enters the register 8, thus forming a continuous sequence of video signals during the forward sweep run. At the inputs of the generator 13 of the frame and line scan from the synchronization unit 12, the synchronizing signals of the frame and line scan are received.

The conversion time of a data word to a sequence of video signals is much longer than the time required to prepare the next word, and therefore the rest of the display cycle time is allotted for processing information by the microprocessor unit 16 in memory block 6, which is determined by specifying the operation code to the program control unit 17. The following operations are possible: writing a byte to memory block 6; reading data byte of memory block 6; setting any bit in a byte located in memory block 6, allowing display of one element on a CRT screen; clearing the specified bit in the byte of memory block 6, erasing one display element; clearing-setting the specified information bits that are in the SAM memory storage block, as a result of which in one display cycle, one bit of information is cleared and another is set.

The microprocessor, in addition to the specified operations, processes the input information according to the algorithms of the device operation, presented and formatted as software, located in the permanent memory block of the microprocessor unit 16. It is assumed that the presented display device is used in multi-module

- a system, for example, a windbreak where the microprocessor, along with the task of supporting the operation of the display device, performs the same actions

in relation to other modules, coordinates their work, if necessary, performed a certain sequence of actions during the launch, collection, processing of information, i.e. the microprocessor is

0, the central control element of the multi-module system, and the actions performed on the display device are only a fragment in the overall system operation algorithm.

5 To write a byte of information to memory block 6, the microprocessor performs the following operations: write the address of the data byte to counter 2, the X coordinate, and the first register 3, the Y coordinate by

0 microprocessor data bus (information input-output of control unit 1); loading the recorded data in the register 10 input through the data bus; setting the operation byte code to the control

5 register 18 of the firmware control unit.

After receiving the code of the specified operation, the block 17 of the firmware control in the current or next cycle

The display 0 generates the control signals that provide the recording of the data byte located in the input register 10, the comms of which is transmitted to the information input of the memory block 6. Address

The 5 cells into which the byte is written is determined by the contents of register 3 and the upper bits of counter 2. The data byte is written to memory block 6 in the time interval intended for

0 microprocessor information processing. At the end of the indicated interval, the control register 18 is reset. The execution time of a write byte operation is usually equal to half

5 times a single display cycle.

To perform the reading of the byte from memory block 6, the following actions are performed by software: loading the data byte address into counter 2 and register 3; installation code

0 byte read to control register 18; reading the received data byte from the register 9 of the output to the microprocessor;

After receiving the byte read operation code, the firmware control block 17 in the current or next display cycle generates control signals that read the data byte from memory block 6, transfer it to the inputs and write to the output register 9. With

accessing the output register 9 for the purpose of reading data, its contents are transmitted via the bus driver 11 to the data bus for subsequent reading into the microprocessor. At the end of the operation, as in the case of other operations, the control register 18 returns to its original state, byte read or write operations are used for operational data: up to the data byte in 6 memory, for example, when performing diagnostics.

To perform the bit-setting operation by the microprocessor, the following actions are performed: write the address of the bit defined by the X and Y coordinates of the display element to the counter 2 and the register 3; installation in the control register 18 of the bit set operation code.

After receiving the specified code, the firmware control block 17 in the current or next cycle generates control signals that read the data byte from memory block 6, in which the specified bit is located, transfer and write to the output register 9, the contents of which go to the input Converter 7 of the code, conversion by converter of 7 bytes, which implies setting the bit to one, determined by the lower bits of the X coordinate (the remaining bits of the data byte are transmitted without change), and the transmission to the input of the block 6 pa minute and then writing to the address provided. In this case, a read-modify-write loop is performed, at which the data byte is read at a specific address, its change is set by bit or cleared, and the resulting data byte is written at the previous address. In this case, the byte address is defined as the concatenation of the contents of register 3 and the high bits of counter 2. The lower part of the X coordinate determines the number of bits in the byte. After the operation is completed, the initial state of the control register 18 is set.

To perform a bit-clearing operation, microprocessor-like actions are performed similar to a bit-setting operation, except that the bit-clearing operation code is entered into control register 18, then the same actions are performed as with the bit-setting. The difference is that the code converter 7 clears the bit in the byte (set to zero) determined by the state of the least significant bits of the counter 2. Thus, the read-modify-write cycle is performed.

Converter 7 of codes operates in one of the following modes: transferring the contents of register 9 to the input of block 5 of memory with installation of a definite bit 5 of the contents of register 9 of output; transferring the contents of register 9 to the input of memory block 6 with clearing a certain bit of the contents of register 9 of the output.

0The setting and bit clearing modes are used to perform actions to display certain graphic elements, such as markers on the displayed signal, when the position changes.

5 of which you need to perform operations for cleaning and installing several display elements.

Six cycles are displayed in the display cycle to execute the bit setting mode to zero or one, three clock cycles for the write or read data byte mode, and three clock cycles are also used to prepare the data for regeneration.

For cleaning-setting bits

5, the microprocessor performs the following actions: writing the Y-coordinate of the bit to be cleared into register 3 (the X-value of the ordinate remains the same); loading the Y-coordinate of the bit to be set into register 4; installation in the control register 18 of the operation code indicating the execution of the clear-set bit mode.

After receiving the specified code block

5 17 firmware controls the signals necessary to perform the bit clearing mode (set to zero), determined by the contents of register 3 and counter 2, and then in the same display cycle

0 sets the bit to the unit with the coordinates determined by the contents of register 4 and counter 2. Thus, this mode is a mode for clearing and setting the bits, performed 5 consecutively in one display cycle and occupying 12 clock cycles. At the end of this operation, an increase in the unit value of the counter 2 occurs, thereby ensuring

It is possible to perform the above actions on display elements with a different X-coordinate. This mode is most effective for changing display information.

5 Thus, the introduction of counter 2 and register 4 allows simultaneously loading into registers 3 and 4 for one display cycle the Y-coordinates of the elements to be erased and installed (the X-coordinate of the elements is formed in hardware with

using counter 2). This increases the speed of the device.

Claims (1)

The device for displaying information on a cathode-ray tube (CRT) screen containing a control unit, the first Y coordinate register, a multiplexer, a memory block, a code converter, an output register, an input register, a bus driver, a shift register, a frame generator, and line scan, synchronization unit, video amplifier, the information input of which is connected to the output of the shift register, the information inputs of which are connected to the outputs of the memory block, the address inputs of which are connected to the outputs of the cartoon An iplexer, the first information inputs of which are connected to the first and second outputs of the synchronization unit, the third and fourth outputs of which are connected to the synchronous inputs of personnel and line sweeps, the outputs of which are connected to the deflection system of a CRT, the modulator of which is connected to the output of the video amplifier, the second information inputs of the multiplexer connected to the output of the first register of the Y coordinate; the output of the code converter is connected to the information input of the memory block connected to the output of the input register, information The input of which is connected to the information input of the first register of the Y coordinate is connected to the information input / output of the control unit, whose information input is the information input of the device, the information input of the code converter is connected to the output of the output register connected to the information input of the bus driver, the output of which is connected to the informational inputs-outputs of the device, the informational inputs of the output register are connected to the outputs of the memory unit, the controllers of the second control unit are connected to the outputs of the control unit group, clock, address, and the first and second control inputs of type i connected to the fifth, i / ec, and seventh outputs of the sync-output and the multipexor, the control input of which is connected to the first output of the second control unit and the third outputs of which are connected to the first and second control inputs of the first register of the Y coordinate, the first and second control inputs of the code converter are connected to the fourth and fifth the outputs of the control unit, the sixth output of which is connected to the first control input of the output register, the second control input of which is connected to the output of the multiplexer, the seventh output of the control unit is connected to the control input of the shift register, the clock input of which is connected to the fifth output of the synchronization unit, control The bus driver's input is connected to the eighth output of the control unit, the ninth and tenth descendants of which are connected to the first and second control inputs of the register, which are different in that Vyshen performance, it contains the X coordinate counter and the second register of the Y coordinate, whose outputs are connected to the second multi-mountain / mountain information inputs, the X-coordinate counter outputs are connected to the code converter address inputs, the X coordinate coordinate information inputs, and the second Y coordinate register are connected to the block information input-output the control, the eleventh and twelfth outputs of which are connected to the control and clock inputs of the counter, the X coordinate, the first and second control inputs of the second register of the Y coordinate are connected to the thirteenth and the third output of the control unit. - -Cd-1§ msh1t- - -,one f hhЈ .. k 4 -8 s § I I four B Cfr 1l Ni /.662891