SU1688280A1 - Character generator for the matrix data display units - Google Patents

Abstract

The invention relates to automation and computing and can be used in the construction of alphanumeric and graphic displays on matrix screens. The purpose of the invention is to expand the field of application of the driver by allowing arbitrary changes in the configuration of the displayed characters. This is achieved by the fact that a frequency divider entered in the driver, a command register, a data input register, a control unit, a data output register, an address register, a second permanent memory unit, provide hardware generation of a dot matrix of symbols and program control of information transfer between blocks. Operatively change the configuration of the displayed symbols of 1 З.п f-ly. 2 Il.

Description

cl

with

The invention relates to automation and computing and can be used in the construction of alphanumeric and graphic displays using matrix screens:

The purpose of the invention is to expand the field of application of the driver by allowing arbitrary changes in the configuration of the displayed characters.

The control unit contains a single-chip 16-bit microprocessor on a K1801 BM1 type microcircuit. At its conclusions, an exchange protocol is emulated, corresponding to the protocol of the MPI type trunk (inter-module parallel interface) according to OST 11 305. 903-80. The trunk uses the synchronous method of transmitting the address and the asynchronous method of exchanging information. All microprograms are executed asynchronously, external clocks synchronize the exchange of information in the external highway.

The microprocessor uses a software mode without radial and vector interrupts. For the accumulation and processing of information, internal registers are used, and the input and output of information is implemented through external radially selectable expansion registers (buffer data input / output registers, command and state registers).

An introduction to the device of the control unit and a number of blocks made the symbol-shaper hardware-software, namely: a dot matrix of symbols is formed by hardware, which is written into the input buffer register, and the transfer of information between the buffer input-output registers and the control unit registers structure

about

00 00

go

00

about

increases the efficiency, flexibility of the symbol maker, allows rotations of the characters displayed on the screen, randomly changing the configuration of the displayed characters, allowing you to get additional characters of character selection, and this expands the scope of the information display device,

Figure 1 shows the flowchart of the symbol former; FIG. 2 is a block diagram of a software I / O algorithm.

The symbol generator contains 1 pulse generator, the first 2 and second 3 pulse shapers, the first element PI 4, the first permanent memory unit 5, the counter 6 lines, the column counter 7, the frequency divider 8, the control unit 9, the sign-10, decoder 11, register 12 command, register of data input 13, register of data output 14, register of 15 addresses, the ETH block of permanent memory 16.

The control unit 9 contains an AND-NE element 17, the second OR element 18, the first 19, the second 20, the third 2 I, the fourth 22 AND elements, the delay element 23, the fifth Element AND 24, the node 25 of the firmware update.

The character shaper works as follows.

Pulse generator 1 generates clock pulses TI I, which are fed to the synchronization input of microprogram control node 25, to the counting input of frequency divider 8 and to the strobe input of register 13 of the data gadget.

The address of the command from the external device is written to the high byte of the register of 12 commands (and states).

Firmware control node 25 generates a signal of the first I / O sample and the read signal, which are fed to the inputs of the And 19 element. At the output of the last, a signal of the sample of the register of 12 commands is generated. Firmware control node 25 reads the content at 1777168 (address of command register 12), and the information through the multiplexed AD bus enters the input of control unit 9 and is interpreted as follows. The low byte is set to zero and the high byte is read from the AD bus. . The word composed of the low and high bytes is entered into the internal register R7 (instruction counter) and is the address of the first command to be executed.

The second block 16 of the permanent memory stores the work programs and constants, which is necessary for the implementation of the algorithm of the functioning of the control block 9

Signal appearance Exchange at the output

node 25 means that the address is located at the bus input of the AD, Signal Exchange via element 22, when there is no register sampling signal at the output of element AND – E 17, it goes to the second sample input of the second permanent memory block 16 and to the gate input the register of the 15th address; the latter records the address set on the AD bus, from the output of which the address goes to

5, the address input of the second block of 16 constant memory. If there is a signal Reading at the output of the element 21, when there is no signal of sampling the register at the output of the element IS-NOT 17, information is sampled from the second permanent memory block 16, called by the address on the input that goes to the bus of the control unit 9 . The signal from the output element And 21 is fed to the input of the element 23 of the delay,

5 at the output of which a Response signal is generated, which arrives at node 25 and indicates that the data is set at the information inputs of the bus HELL of the control unit 9. Upon receipt of the mark code from

0 external device to the lower bits of the address of the first block 5 of the permanent memory and to the input of the first element OR 4 at the output of the first element OR 4 a signal is generated indicating that the external device is ready to enter data writing, for example, in the seventh bit of the low byte register 12 teams.

Control unit 9 programmatically determines the readiness of the external device.

About (figure 2, blocks 2, 3). If readiness has appeared, node 25 generates a signal of the Installation (FIG. 2, block 4), which, through the OR 18 element, sets the frequency divider 8 to its initial state, counter 7

5 columns, a counter of 6 rows, prohibits sampling of the block 5 of the permanent memory, as well as the first signal. The installation clears the data output register 14. For the lower bits, the addresses of the first block 5 are constant.

0 of the memory receives the character code from the external device, and the older bits of the address receive the code of the familiarity string from the counter b of the lines. For example, in the first block 5 of the permanent memory, the program 63 is sewn

5 characters with a dot matrix of 8x7 dots. Information is selected from the first block 5 of the permanent memory with the corresponding address containing at the lower bits of the address input the sign code from the external device and nz the higher bits

address input code of the familiarity line coming from the information outputs of the counter of 6 lines in the presence of a selection clock signal at the sample input of the first block

5 permanent memory.5

The first block 5 of the permanent memory forms a multi-digit code for the location of points, the number of which is equal to the horizontal size of the matrix of points (FIG. 3, where the HoX are columns, Vou / are the dot matrix rows of 10 characters).

The multi-bit code is converted into a binary code using the character generator 10. Each bit of the eight-bit code strictly corresponds to a binary code.

From the pulse generator 1, the pulses TI 1 arrive at the counting input of the frequency divider 8, the output of which pulses go to the counting input of a 7-column counter, generating 20-hundred sign column codes, which are decoded by the decoder 11, generating signals of familiarity columns at the outputs. Signals of familiarity columns from the outputs of the decoder 11 are fed to the corresponding inputs of the first 25 groups of the character generator 10, the inputs of the second group of which receive a multi-bit code for the location of points in the dot matrix from the outputs of the first permanent memory unit 5. At the outputs of character generator 30 10, an information code of the familiarity columns is generated, carrying information about the configuration of the symbol.

The information codes of the familiarity column, which carry information about the configuration of the characters in the familiarity, come from the outputs of the character generator 10 to the fourth information inputs of the input-data register 13, the fifth inputs of which receive the familiarity line codes from the counter outputs. 40

6 lines, to the sixth inputs-codes of familiarity columns from the counter outputs of 7 columns, to the second and third ones from the outputs of the first driver 2 or the second driver 3.45

When the counter is filled with 6 lines, the highest bit of the line code is formed at its output, which starts the first driver 2 or the second driver 3 on the falling edge. The first driver 2 50 generates a signal at the output when there is a signal Adding mode from an external device. The second driver 3 generates a signal at the output in the presence of a signal. Subtract mode, from an external device.

The signals at the information inputs when pulses are received from the pulse generator 1 at the gating input are written to the data input register.

Node 25 generates a signal Sampling the second PBB and the signal Read, which is fed to the inputs of the element 20. And the output of the element 20 produces a sample signal of register 13. The control unit 9 reads the contents at address 1777148 (register address 13), and information via the multiplexed bus The blood pressure is fed to the input of control block 9 (FIG. 2, block 6), which is recorded in the register of block 25. Then data is processed (FIG. 2, block 7), after which block 25 produces a signal. that come in to the inputs of the And 24 element. At the output of the And 24 element, a strobe signal is generated, which arrives at the gate input of the register 14, according to which the data set on the AD bus at 1777148 (register address 13) are written to the register 14 (FIG. 2, block 8) .

At the outputs of the data output register 14, a column code and a dot matrix row code of a new symbol are set, as well as bits indicating whether or not the pattern is formed in addition mode or in subtraction mode. Information from the output of register 14 is fed to the input of an external device.

After the data is recorded in the register 14, the control unit 9 generates signals for generating information from the register 13, and so on. (Fig. 2), this cycle continues until a character is formed.

Horizontal sync pulses and frame sync pulses from an external device are fed to the inputs of the element OR 18, the output of which produces a signal to the reset inputs of the frequency divider 8, the counter of 7 columns, the counter of 6 rows and the sample input of the first block 5 of the permanent memory resetting counters 7 rows 6 and columns 7, frequency divider 8 and prohibiting the retrieval of information from the first block of 5 permanent memory.

By software erasing the weight of a symbol point, you can form a symbol with a modified configuration.

Thus, the proposed shaper allows for the introduction of a control unit and a number of other blocks to promptly change the configuration of symbols as a result of information processing and promptly change the algorithm of the operation of the control unit, and the presence of a system bus allows you to connect external devices, which expands and modernizes characters.

Claims (2)

Claim 1, A shaper for displaying information on matrix screens, comprising a pulse generator, first and second pulse shapers, the first block of permanent memory, row and column counters, character generator, decoder, first OR element, first control inputs of the first and the second pulse formers are connected to the output of the row counter, and the second control inputs are respectively the control inputs Addition mode and the subtract mode of the imager, characterized in that When expanding the field of application of the generator by providing -1 and the ability to change the configuration of displayed characters, a frequency divider, command register, data input register, control unit, data output register, address register 1, permanent memory unit, pulse generator output are connected to clock inputs of the data input register, control unit and frequency divider, the output of which is connected to the clock input of the column counter, the outputs of which are connected to the information inputs of the decoder, pyhoda c Uppa and the output of which are connected respectively to the address inputs of the first group of the character generator and to a clock row counter, the outputs of which are connected to the address inputs of the first group of the permanent memory unit, the address1 inputs of the second group are the information input of the device and connected to the inputs of the first OR element, the output of which is connected to the information input of the command register, the information inputs of the group and the recording control input of which are respectively the address input and the recording control input service The outputs, the outputs of the first block of the permanent memory are connected to the address inputs of the second group of the character generator, the outputs of the first meter of the second pulse shaper, character generator, line counters, and from the columns are connected to the information register of the data register, the outputs of the command register, the data input register, the second block constant the memory is connected to the information inputs, the outputs of the control unit and to the information inputs of the output register and the address register, the control inputs of the command register selection and the data register respectively, to the first and second outputs of the control unit, the jack inputs of the data output register and the reshra address connected to the third and fourth outputs of the control unit, the first and second sampling control inputs of the second permanent memory unit are connected respectively to the fifth output of the control unit and to the clock input of the address register, the outputs of which are connected to the address inputs of the second permanent memory unit, register setup input the data output is connected to the sixth output of the control unit, the installation inputs of the row and column counters, the frequency divider and the sampling control input of the first permanent memory unit are connected to The seventh output of the control unit, the first and second control inputs of which are, respectively, the horizontal and personnel sync rotations of the device. 2. A shaper according to claim 1, stating that the control unit contains an AND-NOT, five AND elements, a delay element, a second OR element and a firmware control node, information inputs and outputs which are the information inputs / outputs of the block, the installation output of the firmware control node is the sixth output of the block and is connected to the first input the second OR element, the second and third inputs of which are the first and second control inputs of the block respectively, and the output of the second OR input is the seventh output of the block, the output of the firmware control node is connected to the first inputs of the first, second and third elements AND, whose outputs are accordingly first. the second and fifth outputs of the unit, the second the input of the first element AND is connected to the first input of the NAND element and to the first output of the sample of the firmware control node, the second output of which is connected to the first input of the fifth AND element and to the second inputs of the second element L and the NAND element, the output of which is connected to the second inputs of the third and fourth elements AND, the second input of the fifth element AND connected to the output Record of the microprogram control node, and the output is the third output of the block, the first input of the fourth element And is connected to the output Exchange of the node of the firmware control, and the output is the fourth output the block, the input of the delay element is connected to the output of the third element I, and the output to the input of the Response of the firmware control node whose clock input is the clock input of the block. Team address figure 1 I F at I not An (End j