SU1534750A1 - Clock synchronization device - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automation and computing devices. The purpose of the invention — improving reliability — is achieved by introducing AND-HE elements 5-7 and new electrical connections between the functional elements into the clock synchronization device. The device also contains the element OR 1, the inverter 2, the D-trigger 3 and the element And 4. 2 Il.

Description

1

The invention relates to a pulse technique and can be used in automation and computing devices.

The purpose of the invention is to increase reliability.

FIG. 1 shows an electrical functional diagram of the device J in FIG. 2 - time diagrams that show his work.

 The device contains an element OR 1 inverter 2, D-flip-flop З, element И 4, the first, second, third elements И-ИЕЕ 5-7, the output of the first of which is connected to the D-input D-flip-flops Z and p by the first input of the second element AND -NON 6, the output of which is connected to the first input of the first element AND-NOT 5, -the second input of which is connected to the output of the third element AND-NOT 7, the first input of which is connected to the output bus 8 and to the output of the element 4, the first input of which is connected with inverse output of D-flip-flop Z, the second input with the first input of the element OR 1, with the bus 9 clock pulses-cofc and black Without inverter 2 with the C-input D-tpnrrepa 3, the S-input of which is connected to the second inputs of the second and third elements IS-NE 6 and 7, and to the output of the element OR 1, the second input of which is connected to the bus 10 of the control.

The clock synchronization device operates as follows.

In the initial state on bus 10, there is no signal (Figure 2b). The trigger 3 is held in a single state by pulses from the output of the element OR 1 (Fig. 2d). At the inverse output, the trigger is a low level (Fig. 2e). On the output bus - low signal level (fig.2z).

When a high voltage is established on the bus 10, the flip-flop of the trigger to the zero state is permitted by the decay of the clock pulses (Fig. 2b), since the D-input of the trigger 3 -,

low level (Fig. 2g) from the output of element 5, since a high level acts on its two inputs (Fig. 2). The pulse following the transfer trigger 3 (Fig. 2a) passes through element 4 and a clock sync pulse is formed on bus 8. Since at this moment the inputs of element 7 are high, then its output (Fig. 2e) is low and the output of element 5 is high. Consequently, the next pulse at the C input of the trigger 3 is transferred to the unit state and element 4 is closed low with inverted trigger output 3.

When exposed to short noises on bus 10 on bus 8, a clock pulse is not generated due to digital interference filtering by elements 1, inverter 2, and D-trigger Z.

Claims (1)

Invention Formula A clock synchronization device containing an element AND whose output is connected to an output bus, a first input with a D-flip-flop inverse, and a second input with a clock bus, an inverter input and the first input of an OR element, the second input of which is connected to the control bus, and the output With the S-input of the trigger, the C-input of which is connected to the output of the inverter, characterized in that, in order to increase the reliability, three AND-NOT elements are introduced into it, the output of the first of which is connected to the D-input of the D-trigger and the first the input of the second element AND NOT, the output to orogo connected to the first input of the first AND-NO element, a second input coupled to an output of the third AND-NO element, whose first input is connected to the output line and the second input - to a second input of the second AND-NO element and OR element output. a b b t de g Srig.G.