SU1309303A1 - Synchronous pulse repetition frequency divider with 5:1 countdown - Google Patents

Abstract

The invention is intended to reduce the frequency of the input signal by 5 times with a duty cycle of the output signal of two and 2.5 times and can be used in frequency synthesizers. The purpose of the invention is to expand the functionality of the divider. The divider contains triggers 1, 2 and 4, bus 3 and 5 of the direct and inverse input signal and bus 7 output signal. The introduction of the element AND-OR 6 and the output signal bus 8 allows an additional division factor of 2.5 to be obtained. 2 Il. J; S (L with about; about with about with

Description

The impli- cation refers to the pulsed T (x-iniKo, designed for smart). The input signal frequency is 5 times with the output signal bore equal to two, and 2.5 times H can be used in frequency synthesizers.

The purpose of the invention is to expand the functionality by obtaining an additional | -o division factor, equal to 2.5 o.

FIG. 1 shows the electrical structural diagram of the device; in fig. 2 - time diagrams, but those that work on it.

The device contains the first 1 and second 2 triggers, bus 3 direct input signal, the third trigger 4, bus 5 inverse input signal, the element AND-OR 6, bus 7 output signal and additional HjHHy 8 output signal, and her trip D D -type The C inputs of the first 1 and 2 of the three 1111s are connected to the buses (3 direct input signal, C input of the third trigger 4 is connected to the bus 5 of the inverse input. The first D input of the first trigger 1 is connected to its inverse output and input ner-Boii structure AND element AND - OR bis first D- and R-inputs of the third trigger 4, the direct output of which is connected to its second D-input, H1 to 7 output- Hd O signal and to the second input of the first structure AND element AND -ORI 6, the output of which is connected to the additional bus 8 output signal. The inverse output of the second trigger 2 is connected to its first D-input, to the second D-input of the first trigger 1 and to the second R-input of the third trigger 4. The first input of the second structure AND element AND -OR 6 is connected to the second D- input of the second trigger 2 and with the inverse output the third trigger 4, the second R input is connected to the second input of the second structure AND of the AND-OR 6 element, the third input of which is connected to the bus 5 of the inverse input signal.

The synchronous pulse frequency divider for the five operates as follows.

My input signal from HJHHBI 3 with a period T and a duty cycle of two is fed to the C inputs of the flip-flops 1 and 2, the inverse input signal from the bus 5 goes to the C input of the flip-flop 4.

Assume that in the initial state the triggers 1, 2 and 4 are zeroed (Fig. 2). Then, under the action of two drug impulses from tires 3 (Fig. 2a) and 5 (Fig. 26), the pa S inputs of the flip-flops 1, 2, and 4 last pass through the following states successively (Fig. 2c, d, d, s, g, 3 - signals at the direct and inverse outputs of the trigger I, 2 and 4): QIQ2Q4

0OO

11O About I .0

At the same time, at the output of element 6 (according to the second structure I), taking into account the initial state of the flip-flops 2 and 4 (Fig. 2e, g) and the signal of the bus 5 (Fig. 26), a pulse of duration T / 2 is formed, which is fed bus 8 (Fig. 2k).

The third pulse from the bus 5 sets the trigger 4 to the one state. At the same time, at the output of element 6 (according to the first structure I), taking into account the state of the flip-flops 1 and 4 (Fig. 2d, g), a pulse of duration T / 2 is formed, which also enters the signal bus 8 (Fig. 2k).

Then, under the action of three pulses from the bus 3 and two pulses from the bus 5, the trigger 5, 1, 2 and 4 successively pass through the following states:

QIQ2Q4

011

10 11

0000

After the triggers 1 and 2 are set to the zero state, the high potentials of their inverse outputs set the trigger 4 by its R inputs to the zero state.

As a result, a signal with a period of 5T and a duty cycle of two is formed at the output of trigger 4 and on bus 7, and a CHI-with a period of 2.5 T is formed at the output of element 6 and bus 8 with a period of 2.5 T. Q Then, the device repeats.

Claims (1)

Invention Formula Synchronous frequency divider following five pulses, containing three r flip-flops, each of which is D-type, the C-inputs of the first and second of which are connected to the direct input signal bus, the C-input of the third trigger connected to the inverse input signal bus, and its first D-R inputs are connected to the inverse output 0 and the first D-input of the first trigger, the second D-input of which has an inverse output and the first D input of the second trigger and the second R-input of the third triple, d and inverse) whose 1st outputs are connected we match the output bus and the second C-input of the second trigger, characterized in that, in order to expand the functionality, an additional output signal bus and an AND-OR element, the output of which is connected, are introduced into it to additional HJHHC output signal, the first input of the first AND-OR structure to the inverse output of the first trigger, the second input to the direct output and the second D-input of the third trigger, the first input of the second structure and the AND-OR element to the inverse output the third-trigger, the second input - to the inverse output of the second trigger, and the third input - to the bus of the inverse input signal. .2