SU1471190A1 - Microprogram control unit - Google Patents

Abstract

Usage: in the electronics industry, in particular in computers. Summary of the Invention: a group of triggers, first and second groups of elements AND, first and second groups of elements AND — NOT, one-vibrator group, synchronization unit containing start trigger and clock generator are entered into the device, the command code register and micro-operation register are entered into the pipeline control unit .

Description

one

fan control, the output of which logical conditions are connected to the multiplexer input logical conditions j-no of the pipeline control unit, the output of which is connected to the first input of the OR j-ro element of the conveyor control unit whose output is connected to the Kth input of the first group of information inputs the switch of the j-ro address of the pipeline control unit (where K is the width of the address of the micro-instructions), the output of the field of the modified bit of the address of the memory block of the micro-commands of the j-ro block of the conveyor column is connected to the second input the element OR j-ro of the conveyor control unit, from the first to (K-1), and the field outputs of the unmodifiable bits of the address of the memory block of the microcommands j-ro of the conveyor control unit are connected to the first (K-1) -th input of the first group of information inputs of the j-ro address switch of the conveyor control unit and with information inputs of the j-ro command code of the conveyor control unit, the output of the microoperations microoperations field, j-ro of the conveyor control unit is connected to the informational input of the microoperations register of the j-ro conveyor control outputs, the output of the command end flag and micro-operations of which are connected respectively to the control inputs of the j-ro address conveyor control unit and to the micro-operation output of the j-ro conveyor control block, the output field of the permission sign for recording the memory block of the j-ro microcommand of the conveyor control block connected to the enable input of the register entry of the j-ro command code of the pipeline control unit, whose code is connected to the output of the j-ro command code of the pipeline control unit, input of the j-ro command code of the end block eyernogo control is connected to a second group of information inputs of switch addresses j-ro conveyor control unit, the output unit floor instruction address microinstruction memory connected to the input of the first command code block conveyor control group, the second output clock generator im0

pulses of the sync block are connected to the first direct input of the second element And and the first inputs of the element II of the second group, Bbixojt of the element And the second group of which is connected to the synchronization input of the command code register of the j-ro block of the pipeline control of the group and the micro-operation register j-ro the group's pipeline control unit, the output of the sign of the end of operation of which is connected to the input of setting the j-ro of the group to zero, the output of the feature of the operation code of the first conveyor control unit is connected to the inverse second input And element I, the output of the i-ro command code of the pipeline control unit (, N-1) is connected to the input of the command code (i + O-ro of the conveyor control unit, the device start input is connected to the installation input of the first trigger of the group in the unit, output j- ro of the GRZTP1PY trigger is connected to the second inputs of the j-ro element of the first and second groups, the output of the code attribute of the i-ro command of the conveyor control unit is connected to the i-th inputs of the AND-N element of the first group, the first input of the i-ro element AND-NOT the second group and the i-th one-vibrator group, the output of which is connected to the input of the unit and in unit (i + 1) -ro of the group trigger, the output of the sign of the end of the N-g command of the conveyor control unit of the group is connected to the NM input of each AND-N element of the first group A with the first input of the N-ro element of the second group, the output of the j-ro element The NAND of the first group is connected to the second input of the j-ro element of the N-II of the second group, the output of which is connected to the third inputs of the JX elements AND of the first and second groups, the output of the sign of the end of the N-ro operation of the group's conveyor control unit is connected to the installation input to zero trigger starts block synchronization, the output of the first element And it is connected to the second direct input of the second element I, whose code is connected to the synchronization input of the address register, the output of the sign of the end of the command of the microcommand memory block is connected to the control inputs of the address switch ..

The invention relates to computing and can npiiMeHHTbCH in data processing devices with pipeline firmware execution.

The purpose of the invention is to increase the speed of the microprogram control device.

FIG. 1 shows a functional diagram of the proposed microprogram JQ multi control device; in fig. 2 is a functional diagram of a pipeline control unit; in fig. 3 - synchronization unit; in fig. 4 is a timing diagram of the function of the firmware; in fig. 5 and 6 are time diagrams of the operation of the firmware of the control unit.

The microprogram control unit contains a micro-command memory block 1, (ROM), address register 2, address switch 3, multiplexer 4 logic conditions, element OR 5, 25 second element And 6, synchronization unit 7, first element 8, block group 9.1, 9.2, ..., 9N pipeline control, trigger group 10.1, 10.2, ..., 10.N, the first, the group of elements AND-NE 11.1, 11.2, ..., 11.N, the second group AND-NO elements 12.1, 12.2, ..., 12.N, first 13.1-, 13.2, ..., 13. My second 14.1, 14.2, ..., 14. N groups of elements I, the group of single-oscillators 15.1, .., 15. N, the inputs of the command code 16, logical conditions 17 and uska 18 device, the second 19 and the first 20 outputs of the synchronization unit.

 40

In addition, positions 21.1,

21.2, ..., 21.N denote the groups of inputs of logical conditions, 22.1, 22.2, ..., 22.N and 23.1., 23.2, ..., 23. (K-1) denote the groups of microopedchschonal and command code outputs BKU, respectively, positions 24.1,

24.2, ..., 24.N and 25.1., 25.2,

25.N denotes the outputs of the micro-operations End of Work and End of the Team, respectively, and position 26 indicates the output of the And 8 element.

FIG. 2 the following elements are represented: block 27.R of the memory of the microcoand, register of the 28.R address, switch of the 29.R address, multiplexer 30.R of the logical conditions, element 31.R, register 32.R of the micro-operations, register 3.R of the command code .

50

Q 5

5 o

0

g

0

FIG. 3, a start trigger 34 and a clock pulse generator 35 are indicated, respectively.

FIG. 4 the following notation is used: A. - commands executed by J-M. BCD. (where j is the BKU number, i is the number of the command being executed); G - tact of the BUD (where k - the number of teams in the implemented program).

The device works as follows.

The proposed device can be divided into two levels of control; the first one contains the ROM1: the address register 2, the address switchboard 3, the multiplexer 4 and the element And 5, and the second containing the control unit 9.1-9.N and the elements that control the operation.

In the initial state, all the memory elements are zeroed, except for the triggers of the end of the command registers 32 blocks 9.1-9.N, which form single signals at the outputs 25.1-25.N. As a result, at the output of element 26 and 8 there is a single signal. At the output of the end of the command of block 1 there is a zero signal (the zero code is written in ROM 1, the zero code is written), which opens switch 3 on input 16 -.

According to the trigger signal received at the input 18 of the device, the synchronization unit 7 begins to generate a sequence of pulses.

The first control level functions only if in the second level all the BUDs have completed execution of commands, as evidenced by the microcommands End of the command at their outputs 25.1, 25.2, ..., 25.N. In this case, the first clock pulse from the output 19 of the synchronization unit 7, which arrives at the synchronous input of the address 2 register through the AND 6 element, registers the address of the next command that is selected from the ROM 1 to the address register 2.

The address of the next command is received from the address output of ROM 1 to the first information input of the address switch 3, to the control input of which a single signal is received. Switch 3 in the next cycle skips to. register input 2 addresses the address of the next command, recorded in the format of ROM 1, or the operation code from input 16.

Verification of logical conditions is as follows.

At the input 17 of multiplexer 4, a code of values of logical conditions is found. The code number of the checked logical condition is output to the other input of the multiplexer from the output of the logical 5С of conditions of the ROM 1. At the output of multiplexer 4, a signal appears corresponding to the value of the checked logical condition. This signal arrives at the input element OR 5, the second input of which receives the signal O modified bit a, zipeca microcommands recorded in the format of microcommand branching. At the output of the element OR 5, a signal is generated corresponding to the value of the logical conditions, post-spacing as the low-order bit of the address to the input of the switch 3 of the address. At this point, the work of the first level is completed.

The trigger trigger trigger 10, 1 is transferred to position 1 and unlocks the elements I13.1 and 14.1, Yo to the second clock pulse coming from the output 20 of the synchronization device through the element 13.1 to the synchronization input of the register 28.1 of the first BKU to register 28 through the address switch 29.1, the command code is read from the output of the command code of the ROM 1 of the first control level. The read command code is the address of the first micro-command implemented by the first BUD. Its operational part is entered into register 30.1 of microoperations by the first clock pulse, the address of the next microcom through the switch 29.1 is entered into the register 28.1 and by the next clock pulse The work of the WCT continues as described. :

Verification of logical conditions in the BUD is no different from a similar operation at the first control level,

The BKU micro-command format containing the End-of-Command micro-operation contains an Ml label, which records the address part of the micro-command in buffer register 32, K, This address is the operation code A ,, the command control command which is being executed.

The micro-operation signal. The end of the command from output 25 unlocks the second input of the address switch 29, is fed to the input of a one-shot 15.1 that generates a write pulse of the second

0

five

0

five

0

five

0

five

0

The BUD, as well as the input element And 8 and blocks the passage of the second clock pulse element And 6. At the same time the element And 8 performs the function F t, t,,.

m

 m ,,

- t .. 1,

m | y, and the investigator

one

but, F 1, This signal unlocks the AND 6 element, thereby permitting the operation of the first control level on the next first clock pulse. This completes the first cycle of operation. By the start pulse from the output of the one-shot 15.1, the trigger 10.2 is set to one state, allowing the second LPC to work. Thus, the second cycle of operation begins. In this case, the operation code Aj is read in the per-jBOM BKU and in the second BKU A,

The operation of the device continues according to the described algorithm.

At the same time in each cycle of the K th BKU

works by operation code q

Kt1-i

where K is the BKU number;

j is the number of the work cycle,

The operation of the system is terminated by micro-operation signals. End of operation, which triggers triggers 10.1, 10.2, ..., 10, N sequentially in cycles of operation. The End of Work signal from output 24.1 also blocks element 6, and from output 24.N zeroes the trigger trigger 36, thereby stopping the generation of pulses by generator 37. On a trigger pulse, it goes to input 18, the device resumes

The functioning of the MCDS can be divided into three stages: the first stage is the stage of drawing in, when sequentially (FIG. 5) the BUD diagrams are put into operation. Moreover, in each subsequent clock cycle, the number of operating BUDs is increased by one. This shows that the stage of retraction lasts exactly N-1 clock for the case when the number of commands in the device program exceeds the number of channels it serves, t, e, the number of the BUD

55

w g

 Y-1 (tact), if K N,

where K - the number of commands in the run -

program; N - the number of BUD.

: iS

Phil

Claims (1)

USSR copyright certificate No. 905818, cl. G 06 F 9/22, 1982.. FIRMWARE CONTROL DEVICE, containing a micro-memory block, address register, address switch, logical condition multiplexer, first and second AND elements, an OR element, a group of pipelined control blocks, each of which contains a micro-memory block, address register, address switch, logical condition multiplexer , OR element, and the input of the logical conditions of the device and the output of the field of logical conditions of the memory block of the microcommands are connected respectively to the information and control inputs of the multiplexer logical conditions, the output of which is connected to the first input of the OR element, from the first to (M-1) th, the outputs of the field of non-modifiable bits of the address of the memory block of microcommands (where M is the bit width of the address of microcommands) are connected from the first to (M-1) -th input of the first group of information inputs of the address switch, the output of the field of the modifiable bit of the address of the micro-memory block is connected to the second input of the OR element, the output of which is connected to the Mm input of the first group of information inputs of the address switch, the group of inputs of the device command code is connected respectively, with the inputs of the second group of information inputs of the address switch, the output of which is connected to the information input of the address register, the output of which is connected to the address input of the micro-memory memory block, the group of inputs of the logical conditions of the device is connected. with the inputs of the logical conditions of the conveyor control units of the group, the microoperation outputs of which are connected with the outputs of the microoperations of the device, the outputs of the sign of the end of the command of the conveyor control blocks of the group are connected to the group of inputs of the first element And, distinguishes the fact that, in order to improve performance, a group of triggers, the first and second groups of AND elements, the first and second groups of AND elements, a group of single vibrators, a synchronization block containing a start trigger and a clock pulse generator are introduced into the block · The conveyor control is entered the command code register and the register of microoperations, and the start input of the device is connected to the installation input in the start trigger unit, the synchronization block of which is connected to the start input of the clock pulse generator of the synchronization block, p The first output of which is connected to the first inputs of AND elements of the first group, the outputs of which are connected to the synchronization inputs of the corresponding address registers of the conveyor control units of the group, the output of the address register j-ro of the conveyor control unit is connected to the address input of the memory block of the microcommands j-ro of the conveyor unit control, the output of the logical conditions field of which is connected to the control input of the logic conditions multiplexer j-no of the conveyor control unit, the output of which is connected to the first input of the OR element j-ro block and the conveyor control, the output of which is connected to the Kth input of the first group of information inputs of the j-ro address of the conveyor control unit (where K is the bit width of the address of the microcommands), the output of the field of the modified bit of the address of the memory block of the microcommands j-ro of the conveyor control unit is connected to the second the input of the OR element j-ro of the conveyor control unit, from the first to (K-1) -th outputs of the field of non-modifiable bits of the address of the memory block of microcommands j-ro of the conveyor control unit are connected from the first to (K-1) -th input of the first group of info the input inputs of the j-ro block of the conveyor control unit and with the information inputs of the register code of the command code j-ro of the unit of conveyor control, the output of the microoperation field of the memory block of microcommands, j-ro of the unit of conveyor control is connected to the information input of the register of microoperations of j-ro of the unit of conveyor control, outputs of the sign of the end of the command and microoperations of which are connected respectively to the control inputs of the address switch j-ro of the conveyor control unit and with the output of micro-operations j-ro of the conveyor unit the alarm, the output of the recording permission flag field of the j-ro microcommand block memory of the conveyor control unit is connected to the write permission register input of the j-ro instruction code block of the conveyor control unit, the output of which is connected to the j-ro command code output of the conveyor control unit, the input of the j- command code conveyor control unit ro 'is connected to the second group of information inputs of the j-ro address of the conveyor control unit, the output of the command address field of the micro-command memory unit is connected to the input of the command code of the first conveyor unit control group, the second output of the clock pulse generator of the synchronization unit is connected to the first direct input of the second element And the first inputs of the element And the second group, the output of the j-ro element And the second group of which is connected to the synchronization input of the j-ro command code register of the conveyor control unit of the group and with the input will synchronize the register of microoperations j-ro of the conveyor control unit of the group, the output of the end of operation sign of which is connected to the input of the setting of the j-ro of the group trigger to zero, the output of the operation code sign of the first block and the group conveyor control is connected to the inverse input of the second element AND, the command code output of the ΐ-th conveyor control unit (i = 1, N-1) is connected to the command code input (i + 1) -ro of the conveyor control unit, the device start input is connected with the installation input in the unit of the first trigger of the group, the output of the j-ro of the trigger of the group is connected. with the second inputs of the j-ro of the And element of the first and second groups, the output of the command code attribute of the i-th conveyor control unit is connected to the i-inputs of the AND-NOT elements the first group, the first input of the i-ro element AND NOT the second group and the ith single-vibrator of the group, the output of which is connected to the unit input to the unit (i + 1) -ro of the group trigger, the output of the end sign of the command N-gr of the group conveyor control unit is connected to the Nth input of each AND-NOT element of the first group the first input of the N-ro element of the second group, the output of the j-ro element of the NAND element of the first group is connected to the second input of the j-ro element of the NAND number of the second group, the output of which is connected to the third inputs of the jx elements of the First and second groups, the output of the end sign the N-ro operation of the group conveyor control unit is connected to the installation input zero trigger start synchronization unit, an output of the first AND element is connected to the second direct input of the second AND gate, whose output Cpd · nen to an input address register timing output feature memory block end command 'microinstructions connected to the control inputs of the switch address ..