SU1087999A1 - Device for checking microinstruction sequence - Google Patents

Abstract

DEVICE FOR MONITORING THE SEQUENCE SHKROKOMAND, containing decoders, the inputs of which are the inputs of the device, element 11Ш-1, different from the fact that, in order to expand the field of application of the device, it contains two groups of K + G PLI elements (where K - the number of controlled microinstructions); the encoder, the adder, the adder, two delay elements and the comparison unit with. zero, and the outputs of the first and second decoders are connected respectively to the inputs of the elements OR of the first and second 4 U U.S-EH swarm groups, the outputs of the elements OR of the first group through the first encoder are connected to the first information input of the accumulating adder, the second information input of which through the first element the delays are connected to the output of the second cipher Topo, whose inputs are connected to the outputs K of the elements OR of the second group, the input of the termination in the coupling of the device is connected to the trigger input of the comparison unit. zero and through the second delay element controlling the input of the accumulating summator, / the information output of which is connected to the corresponding comparison block with zero, and you (/) C the sign bit course - to the first input of the OR element, the second input of which is connected to the output the comparison block with zero, and the third and even fourth inputs correspond with the outputs of the (K-I) elements OR of the first and second groups, element input 00 OR is the output of device interrupt. F f co

Description

The invention relates to qi (computer technology and automation and can be used in the construction of hardware of microprocessor control computers, microprocessor control and simple 1x computers. A device is known for controlling the execution of the sequence of | | kr commands containing AND elements OR associated with control tires, and the ClZ error trigger. The disadvantages of such a device are limiting the functionality of the processor, due to the need to produce only one control signal and only one bus. and the need for a hard alternation of reading and writing, which, given the known speed limits for the processor, creates additional difficulties, as well as the need to increase the dimension of the control bus and the complexity of the control device associated with the introduction of control codes and their management. the technical entity is a firmware control device containing a pulse clock generator, a memory unit, a micro-command counter, decoders, the outputs of which are connected a convolution node connected to the comparison circuit, a clock counter connected to the 11PI element, and a register are connected1V 1st to the decoders and the hMK rokomand counter, the NO element, the clock generator connected to the comparison circuit, the memory and the OR t2 element. The disadvantages of the known device are the limited scope of the application only by processors that do not use and at the same time read signals and write down various register and possibility of the appearance of a spurious signal while simultaneously disappearing the actual one. The aim of the invention is to exploit the field of application of the device, in particular by providing the possibility of using in one workflow process processes K write operations and m read operations for different registers, and the parameters K and m can be varied by changing the corresponding input elements without fundamental changes the algorithm of the device. The goal is achieved by the fact that the device for controlling the sequence of microinstructions, containing degasters, whose inputs are the inputs of the device, the OR element, has two groups of KI elements 1II (where K is the number of ijOHTproducers 1 "crocs) the accumulating adder, two delay elements and a comparison block with zero, with the outputs of the first and second drives 115) connected to the inputs of the first and second groups respectively, and the inputs of the first IT elements of the first group are connected to the first and The information input of the accumulating adder, the second information input of which through the first delay element is connected to the output of the second encoder, the inputs of which are connected to the outputs K of the elements OR the second group of the micro-operation end input of the device is connected to the trigger input of the comparison unit with zero and through the second - the delay element from the control the input is the accumulator of the dego adder, the information output of which is connected to the corresponding input of the comparison block with zero, and the output of the sign bit with the first input is an element OR, a second input coupled to the comparison unit nlhodom, with zero, and the third and chetvertgy inputs respectively to the outputs (K + 1) th elements IL11 first and second groups, an output of OR is the output of an interrupt apparatus. The drawing shows the functional diagram of the device. The device contains the first decoder 1 (write microcommands), the second decal 1 (read microcommands), the first group 3 of the K + G elements OR, the second group 4 of the K + l elements 1ShI, 1SH1fritors 5 and 6, accumulating adder 7, the first element 8 delays, block 9 comparison with zero, second delay element 10, element II and II, inputs 12 and 13 of the device (read and write microcommands, respectively), input 14 of the end of the microoperation, output 15 of the interrupt, elements OR 16 and 17 of the first and second groups. The device works the following way | 3 The execution of the microprogram in the processor is carried out by transferring information between registers under the action of the write and read control signals generated by the microprogram control unit. In the course of the transfer, the information transmitted can also be changed, such as during arithmetic operations. At the same time, for modern microprocessors, the number of registers n can reach sixty four, and the control unit at the same time is able to generate K recording signals and n read signals

for different reps. In this case, the microprograms are compiled in such a way that if a recording is made in the regasTr, then regardless of the microprogram beat, the information from it must be read, and therefore by the time the microprogram runs out, the total number of write signals and read signals must be be the same.

The execution of the microprogram starts after the next command is entered into the control register and decrypted. Therefore, the entry signal to the command register should be

to consider as the moment of the beginning of the execution of the next g-program and the end of the previous one. When a signal arrives at input 14, the cyNiMaTopa 7 content is compared with zero according to the results of the previous firmware, and after the delay on delay element 10 has elapsed, the accumulative accumulator 7 is set to zero.

During normal operation of the firmware control unit, the combination of the write signals at inputs 13 and the read signals at inputs 12 is perceived by the corresponding decoders 1 and 2. The first output of the deifferator 1, formed from the input signals by the Boolean function, is connected directly to the input of the encoder 5 and corresponds to the absence of the FIDO1 signals in this microprogram cycle. The subsequent outputs of the decoder 1, the frames of the Ipye in their Boolean functions and corresponding to the allowed combinations of control recording signals, are combined on K elements of the IPI 16 groups of elements 1 or 3 in K groups, each of which represent the corresponding signals to the negative signals combinations combined on. The (K + 1) -th element of RSHI 16 is characterized by a combination of recording signals. Removed from one of the (K + 1) outputs of the group of elements OR 3 one of (K + 1) possible output signals, corresponding to the number of output. In this cycle, the recording signals are sent to the encoder 5 that the output of the latter does not appear as a positive binary number in the apr 1 "code (the sign bit is equal) is supplied

Similarly, the processing of read signals is performed, and from one of the (K + 1) outputs of the group of elements OR 4 in the same firmware cycle, it supplies 35 seconds to the encoder6. From the last output, the corresponding binary number in the opposite code is the sign bit equal to one) through delay element 8, the

40 KN1CHCH time code on the part of the machine to ensure the work of the accumulator accumulator, is fed to the second information input of the accumulating cyt-iMaTOpa 7. In the 5 adder, the received binary numbers in the forward and reverse code are sequentially algebraically added, and the digit digit of the FG should always be equal zero because the signal

The 5Q write must always precede the read signal and the total number of signals must, therefore, J be less than or equal to the number of write signals.

5S The moment of the microprocessor's execution is fixed by the signal at input 14, which initiates the operation of block 9, carried out a comparison of the year 99, which is the disjunction of the decoder outputs, in the Boolean function of which the sum of the signals is 1.2, ..., (K-1 ), K, respectively. The allowed i-th record (read) signal combination is the combination of control signals at the write inputs; (read) required to execute the i-th micro-command. The number of such combinations corresponds to the number of micro-instructions. In addition to the allowed class, the absence of write control signals (read /) is assigned. All other outputs of the decoder. Formation is based on Boolean functions. Nakapivanadium adder 7.

$ 10879996

zero of the contents of the adder 7. Privododat code combination in the class

: fulfillment of the conditions mentioned below, banned (simultaneous disappearance through the ISh 11 element from block 9 not Bb aeTCR-jia output 15 in the circuit for routine interruption of the control unit, which indicates proper operation of the microprogram control unit. During the processor's operation The control unit and the registers controlled by it may experience errors in the loss of the necessary control signals (writing or reading) or in the appearance of false signals, as well as in violation of the sequence of formation of the signals (i.e. reading before writing. If the error you make by inserting a false signal or losing a valid output results in a combination of read or write control signals to the prohibition class, then the signal appears on that decoder output, respectively, 2 or 1, which is connected to the input, respectively ( K + 1) -7 or (K +) -th 16 element from the last. An output signal is outputted via the HJDi element to the output 15. A malfunction signal is output to output 15. If the error is not valid and the appearance of spurious signals is not likely), then firmware b Block 9 fixes a non-zero number in the adder or even before the end (the curriculum in cy a4 auto 7 forms a negative number and a sign appears in the significant bit. In both cases, a malfunction signal is output to output 15. Similarly, if the signal generation sequence in the microprogram is violated in adder 7, a negative amount is obtained at the iM step, indicating that the read signals are greater than the records. In this In the case of a character output of the adder, a logical unit is output through the element OR 11, indicating the presence of an error. Thus, the field of application of the control device for microprocessor modules, which have a large number of registers and require their pa- raction in time, has been expanded. speed bots.

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Claims (1)

DEVICE FOR MONITORING THE SEQUENCE OF MICROCOMMANDS, containing decoders whose inputs are inputs of the device, element · OR, with the fact that, in order to expand the scope of the device, it contains two groups of K + 1 elements OR (where K is the number of controlled microcommands), two encoders, an accumulating adder, two delay elements and comparison block c. zero, and the outputs of the first and second decoders are connected respectively to the inputs of the OR elements of the first and second groups, the outputs of the K elements of the first group through the first encoder are connected to the first information input of the accumulating adder, the second information input of which is connected through the first delay element to the output of the second encoder whose inputs are connected to outputs of the second OR elements K grupgy entrance closure device is connected to the micro-operation _zapuskayu-: conductive input to the comparator. zero and through the second delay element with the control input of the accumulating adder, / the information output of which is connected to the corresponding input of the comparison unit with zero, and the output of the sign discharge is connected to the first input of the OR element, the second input of which is connected to the output of the comparison unit with zero, and the third and even ·, the fourth inputs are, respectively, with the outputs of the (K + 1) -x elements of the first and second groups, the output of the OR element is the interrupt output of the device. ^ SU, .. 1087999