SU1136160A1 - Nanoprogram control unit - Google Patents

Abstract

NANOPROGRAM CONTROL DEVICE containing two storage blocks, address register, buffer register, nanoprogram number register, counter, address driver, address switch, two address decryptors, trigger trigger, clock generator, block of elements And, seven elements And, and the input of the operation code device is connected to the first information input of the address switch, the output of which is connected to the information input of the address register, the first output of the address register is connected to the input of the first address decoder, output D which is connected to the address input of the first storage unit, the output of which is connected to the information input of the buffer register, the output of the address of which is connected to the second information input of the address switch, the output of the modified bit of the buffer register, is connected to the control input of the address switch. connected to the control input of the address generator, the first information input of which is the input of the logical conditions of the device, the output of the code of the logical conditions The second buffer register is connected to the second information input of the address generator, the output of which is connected to the second information input of the address switch, the output of the end of the microcommand of the buffer register is connected to the control input of the address switch, the output of the register of the nanoprograms number is connected to the input of the second address decryptor, the output of which is connected to the address input of the second storage unit, the device input is connected to the single input of the start trigger, the single output of which is connected to the generator input so For example, to increase speed, it contains a control trigger, two delay elements, the first output of the clock generator is connected to the first input of the first And element, the output of which is connected to the synchronous input address register, the second output of which is connected to the information the input of the nanoprogram number register, the second you (L the clock pulse generator is connected to the first inputs of the second and third elements AND, the output of the second element AND is connected to the synchronous input of the buffer register tra first clock pulse generator output is connected to a direct input of the fourth AND gate and the control input of the trigger unit, the output unit kotoroOQ On th coupled to a second input of the third AND gate, whose output is connected to the clock terminal. the register of nanopo5 grams number and the counter, the output of which is connected to the second input of the second address resolver zero, the output of the control trigger is connected to the second input of the second And element and the input of the first delay element, the output of which is connected to the second input of the first And element and the inverse of the fourth And element whose output is connected to the first inputs of the fifth, sixth, seventh And elements and the first input of the And block, the output of the nanoprogram's end of the second storage unit is connected to the second input of the fifth e The element And the inverse input of the seventh element And, the output of which is connected to the counting input

Description

of the counter, the output of the fifth element And through the second delay element — with the installation inputs in the “About register number of nanoprograms, the counter and the control trigger zero input, the output of the microprogram ending of the second storage unit — with the second input of the sixth And element, the output of which is connected to the installation input

In the "About address register, the installation input in" About the buffer register and the zero input of the start trigger, the information output of the second storage unit is connected to the second input of the AND block whose output is connected to the input of the nano-operation register whose output is the device output.

The invention relates to automation and computer technology and can be used as a multi-cycle device for microprogram control in the construction of computing machines and systems, as well as automated control systems for technological processes. A device comprising a memory unit, an output signal shaping unit, a memory excitation signal generating unit, a time interval code generating unit, a pulse generator 1 is known. The disadvantage of the device is a slow response time. The closest to the invention in its technical essence and positive effect is a nano-program control device containing two storage blocks, an address register, a buffer register, a nanoprogram number register, a counter, an address generator, an address switch, two address decryptors, a trigger trigger, a clock generator, a block of elements And, seven elements And, with the first input of the device connected to the first information input of the address switch, the output of which is connected to the information input of the address register ca, the output of the address register is connected to the input of the first address descriptor, the output of the first address resolver is connected to the input of the first storage unit, the output of which is connected to the information input of the buffer register, the output address of the buffer register is connected to the second information input of the address switch, the output of the modified buffer the register is connected to the control input of the address generator, the first information input of which is the second input of the device, the output of the buffer register logical conditions A is connected to the second information input of the address generator, the output of which is connected to the second information input of the address switch, the output of the end label of the microcommand of the buffer register is connected to the control input of the address switch, the output of the register of the number of nanoprograms is connected to the input of the second address descriptor, the output of which is connected to the input of the second the storage unit, the third input of the device is connected to a single trigger start input, the single output of which is connected to the clock pulse generator 2 input. Wells of the known device are due to the fact that there are no means of controlling the duration of the micro-tact and there is no possibility of issuing micro-operations, the duration of which is longer than the duration of the micro-cycle. Therefore, if the time of the micro-tact is taken to be equal to the largest micro-operation, which will lower the speed of the control device and the system as a whole. In addition, the device lacks the possibility of issuing the same micro-operations in this micro-tact, which also reduces the speed of the control device, reduces the flexibility and complicates the microprogramming process. The purpose of the invention is to increase speed. The goal is achieved by the fact that the device contains two storage blocks, an address register, a buffer register, a nanoprogram number register, a counter, an address generator, an address switch, two address decryptors, a trigger trigger, a clock generator, a block of elements And, seven elements And, moreover, the input of the operation code of the device is connected to the first information input of the address switch, the output of which is connected to the information input of the address register, the first output of the address register is connected to the input of the first decoder address The output of which is connected to the address input of the first storage unit, the output of which is connected to the information input of the buffer register, the output of the address of which is connected to the second information input of the address switch, the output of the modified register buffer is connected to the control input of the address former, the first information l. the input of which is the input of the logical conditions of the device, the output of the code of the logical conditions of the buffer register is connected to the second information input of the address generator, the output of which Connected to the second information input of the address switch, the output label of the end of the micro-command of the buffer register is connected to the control input of the address switch, the output of the register of the nanoprograms number is connected to the input of the second address decoder, the output of which is connected to the address input of the second storage unit, the device input is connected to the single trigger input the start, the unit output of which is connected to the input of the clock pulse generator, further comprises a control trigger, two delay elements, the first output being The clock pulse generator is connected to the first input of the first element I, the output of which is connected to the synchronous input of the address register, the second output of which is connected to the information input of the register of the nanoprograms number, the second output of the clock generator connected to the first inputs of the second and third elements And the output of the second element I connected with the synchronous input of the buffer register, the first output of the clock generator is connected to the direct input of the fourth element AND and the single input of the control trigger, the single output of which The second is connected to the second input of the third element And whose output is connected to the sync inputs of the nanoprogram number register and the counter, the output of the counter is connected to the second input of the second address decoder, the zero output of the control trigger is connected to the second input of the second And element and the input of the first delay element whose output is connected with the second input of the first element And the inverse input of the fourth element And, the output of which is connected to the first inputs of the fifth, sixth, seventh elements And and the first input of the block of elements And, the output of the nanoprograms of the second storage unit are connected to the second input of the fifth element And and the inverse input of the seventh element And whose output is connected to the counter input of the counter, the output of the fifth element And through, the second delay element to the installation inputs in the “About register of nanoprograms number, counter and the zero input of the control trigger, the output of the end of the microprogram and the second storage unit - with the second input of the sixth element I, the output of which is connected to the input of the installation in the "About address register, input of the installation in the" About the buffer re the start and zero trigger trigger inputs, the information output of the second storage unit is connected to the second API input of the AND block whose output is connected to the input of the nano-operation register whose output is the output of the device. In the proposed device, the following nanoprogramming disciplines are implemented: the formation of micro-operations in nano-tacts fixed for all micro-commands, the duration of micro-operations signals is a multiple of the magnitude of the nano-tact; the formation of signals of micro-operations with an arbitrary duration (the end of the issuance of a co-operation can be in an arbitrary nano-tact of an arbitrary micro-tact). We introduce a series of concepts. The set of microinstructions consists of single-cycle and multi-tact microcommand. A single-cycle micro-command is a micro-command whose micro-operations are performed in one nano-tact. An arbitrary, but fixed, sequence of nanotacks forms a microtakt. A microtactic micro-command is a micro-command, the microoperations of which are carried out for several nano-tacts in a micro-tact, while the beginning and the end of the micro-operation can be in any m-nano-tact of this micro-tact. Separate multi-tact microcommands can have an end to the issuance of micro-operations in an arbitrary, but known, nanotact of subsequent micro-tacts. A single-shot micro-command is a frequent case of a multi-cycle micro-command. The sequence of nano-operations performed in a single nanotact is formed by a nano-team. A sequence of nano-commands executed in one micro-tact forms a nanoprogram. Thus, a multi-microcommand forms a nanoprogram. The introduction of the register of nano-operations is due to the need to issue micro-operations, the duration of which is longer than the duration of the micro-tact. The introduction of a control trigger is necessary to synchronize the reading of control information from the first and second storage units. The introduction of the first delay element is caused by the need to issue a stable pulse when accessing the first storage unit, and the second delay element is necessary to reliably issue the last nano-command of the nanoprogram. FIG. a functional diagram of the nanoprogramming control device is presented; in fig. 2 - functional diagram of the formation of the address; in fig. 3 - coding of the second storage block for three multi-tact microcommands with a length of n 6 and the number of nano-tacts in the micro-cycle w 8; in fig. 4 - time diagram for issuing multi-cycle micro-operations

microinstructions (nanoprograms), encoded as shown in FIG. 3

The nanoprogramming control unit (Fig. 1) contains the first storage unit 1, the second storage unit 2, the address register 3, the buffer register 4, the register number 5 register, the nano-operation register 6, the counter 7, the address driver 8, the address switch 9, the first decoder 10 addresses, second address descrambler 11, start trigger 12, control trigger 13, 14 clock pulse generator, AND 15.1 - 15.p block, first And 16 element, second And 17 element, third And 18 element, fourth And 19 element, the fifth element And 20, the generous element And 21, the seventh element And 22, he first delay element 23, a second delay element 24, input devices 25-27 and the outlet 28 of the device.

The address generator (Fig. 2) contains a multiplexer 29 and the element OR 30.

Consider the operation of the proposed nanoprogrammed control device.

In the initial state, the memory elements of the device are in the zero state. The output signal from the end of the buffer register command received at the control input of the address switch 9 allows the operation code from the device 25 to pass through the address switch 9 to the address register 3.

When recording the operation code defining the start address of the firmware, the Nanoprogramming Control Device is ready to start.

The device starts to execute the firmware according to the signal coming from the device input 27 to the single input of the trigger trigger 12, which allows the formation of two clock pulse sequences from the generator outputs 14 clock pulses.

In the proposed nano-program control unit, the synchronization of the operation of the device with two sequences of clock pulses is used.

The first pulse of the first pulse sequence from the first generator output 14 clock pulses is fed to the single input of the control trigger 13 and translates it into a single state. Simultaneously with this data, the pulse arrives at the first input of the first element I 16 and through it to the synchronizing input of the register 3 addresses. The first pulse of the first clock sequence passes through the first input of the first element AND 16 to the synchronizing input of the register 3 of the address, since at the other input of the first element 16 there is a signal "log." 1 due to the first delay element 23 at the zero output of the control trigger 13.

A clock pulse arriving at the synchronization input of the register 3 of the address reads information from the first storage unit 1 into the buffer register 4 at the address written in the first field of the address register 3. In addition, this synchronization pulse overwrites the information from the second half of the register of the 3 address into the register 5 of the number of nanoprograms.

Information on the address of the next multi-cycle micro-instruction is entered into the buffer register 4. In this case, the first field of the buffer register 4 contains the code of the unmodifiable address, in the second field

contains a modifiable bit, in the third field is the code of the logical force being checked, if the multi-cycle microcommand being executed is a branch microcommand, in the fourth field is the control bit of the end of the command.

In register 5 of the nanoprogram number, information about the address of an operating multi-cycle microcommand was rewritten. Since the operational multi-tact microinstruction represents a nanoprogram,. then it is

address of the selected nanoprogram.

The nano-team address consists of two parts: from the number of the nanoprogram and the number of the nano-command in this nanoprogram. At the same time, the number of the nanoprogram in the nanoprogram varies within the limits of O-t, where m is the number of nano-tacts in a micro-tact. The nanoprogram number is specified by register 5 of the nanoprogram number, and the nano-command number is specified by counter 7.

Since, on the leading edge of the first clock pulse of the first sequence from the first generator output of the 14 clock pulses, the control trigger is set to one, there is a log signal at its zero output. O. The signal from the zero output of the control trigger 13 through the first delay element 23 arrives at the inverse input of the fourth element 19 and thus permits the passage of pulses from the first output of the clock generator 14 through the direct input of the second memory block 2 through the block elements And 15.1 - 15.P on the counting inputs of the trigger register 6 nano-operations and from its single outputs to the outputs of the device.

In addition, the pulses of the first sequence through the fourth element And 19 and the seventh element And 22 enter the counting input of the counter 7 and increase its state by one, thereby forming the next address of the nano command.

Thus, the first pulse of the first sequence from the first generator output 14 clock pulses through the fourth element AND 19 and the seventh element AND 22 enters the counting input of the counter 7 and increases its state by one. In counter 7, the code of the first nanocand of the nanoprogram is recorded, whose address is in register 5 of the nanoprogram number. The clock pulse of the first sequence also comes from the output of the fourth element AND 19 to the first inputs of the block of elements AND 15, but in this case information is not received in register 6 of nano-operations, since there is no access to the second storage unit 2. The first pulse of the second pulse sequence from the second output generator 14 clock pulses through the third element And 18 on the sync inputs of the register 5 of the number of nanoprograms and counter 7, thereby making a call to the second storage unit 2 at the address of the first nano-command in Selected nanoprograms {FIG. 3). Upon the arrival of the next (in this case, the second) pulse of the first sequence from the first generator output 14 clock pulses through the fourth element And 19 organized to issue information from the second storage unit 2 through the block of elements 15 to the counting inputs of T-flip-flops register 6 nano-operations. For the considered example, information is received only on the first bit bus and the T-flip-flop of the register 6 of nano-operations is set to one and the output of the device 28 is signaled to start the execution of the first nano-operations (Fig. 4). In addition to sampling the control information, from the second storage unit, the second pulse of the first sequence through the fourth element AND 19 and the seventh element And 22 enters the counting input of the counter o and increases its contents by one (The address of the second nano-command is thereby formed). The second pulse of the second sequence from the second generator output 14 clock pulses through the third element I 18 enters the synchronous input register 5 of the nanoprogram number, the synchronized input of counter 7 and thereby accesses the second nano command (Fig. 3). The next impulse of the first sequence selects information from the second storage unit 2 and forms the address of the next nano command. For this example, at the output of the device 28, third and six nano-operations are issued (Fig. 3 and 4). When accessing the corresponding nano-command on certain bit buses, micro-operation end signals appear, which, arriving at the counting inputs of the T-flip-flops of the nano-operations register, switch them to the zero state. This ends the issuance of a certain multi-micromano micro-operation. In a similar way, a nanoprogramming control device functions before calling on the last nano-command of the nanoprogram. When accessing the last nano-command of a nano-program, simultaneously with the issuance of control information, a label is read — a sign of the end of the execution of a nanoprogram with field 2.2. second storage unit 2. Tag - a sign of the end of the nanoprogram execution (multi-tact microcommand) is fed to the inverse input of the seventh element 22 and thus prohibits the passage of pulses of the first sequence to the counting input of the counter. 7. The clock pulse of the first sequence, issuing information about the last nano-command of the nanoprograms Fifth And 20 and the second delay element 24, arrives at the installation input into “About register 5 nanoprogram numbers, the installation input at” About counter 7 and zero control trigger input 13 The control trigger 13 goes to the zero state and the signal "Log O from the single output prohibits the passage of the next clock pulse of the second sequence through the third element 18 to the synchronous input of register 5 of the nanoprogram number and the synchronous input counter 7. Signal «Jlor. 1 and the zero output of the control trigger 13 arrives at the second input of the second element 17 and allows the passage of the next clock pulse of the second sequence from the second generator output 14 clock pulses to the synchronous input of the buffer register 4. Information about the address of the next multi-cycle buffer register 4 through the driver 8 and the switch 9 addresses is supplied to the information input of the register 3 addresses. . The address of the next multi-instruction microcommand (nanoprogram) is formed as follows. If the next multi-instruction micro-command is a micro-command of a linear sequence, then its address is determined unambiguously by the code of the unmodified part of the address removed from the field of buffer register 4, and through the switch 9 the address is entered into register 3 of the address. Further, the operation of the nanoprogramming control device proceeds as described. If the next multi-instruction microcommand follows the branch microcommand, its address is determined by the code of the unmodified address part removed from field 4.1 of buffer register 4, modified by bit (a) 4.2 of buffer register 4, and code of checked logical condition (xj) removed from field 4.3 buffer register 4 and the input to the control input of the multiplexer 29 (Fig. 2) The information input of the multiplexer 29 from the second input 26 of the device receives the code of the executed logical condition, If the code of the logical condition being checked and xi 1, then the Log signal appears at the output of the multiplexer 29 of the address generator 8. 1, which through the element OR 30 supplements the unmodifiable portion of the code (Aq) with a unit. If the code of the checked logical condition xi О, then the unmodifiable part of the address (En) is added to zero, for example, to the left, i.e. depending on the performance of the checked logical one, the xi modifiable condition it finally defines the address of the next multi-cycle micro-command after the micro-command of the branch. The address of the next micro-command is entered into the address register 3 and when the next pulse of the first sequence arrives from the first generator output of 14 clocks, the device continues to work as described.

In addition to the implementation of a micro-tact of fixed duration, the "floating micro-tact" mode can be implemented in the proposed nanoprogramming control device. This is achieved by the fact that the indication of the completion mark of the nanoprogram is entered into the nano-team, in which the last nano-operation is activated. The micro-tact end signal is generated in the i 1, m micro-tact nano-tact (Figs. 3 and 4), for the third nanoprogram).

When reading the last nano-operation of the last nanoprogram}. - Amma microprograms from the outputs of the second storage unit 2., Mark the end of the microcommand and the microprogram. Tag - a sign from the output of the second storage unit 2 through the fifth element And 20 and the second delay element 24 is fed to the input of the setting in the register number 5 of the nanoprogram, the input of the installation at the counter of the counter 7 and the zero input of the control trigger 13. The mark is a sign of the end of the firmware execution from the output of the second storage unit 2 through the sixth element 21 and is fed to the input of the setting in "About the register 3 addresses, the input of the setting in" About the buffer register 4 and zero input of the start trigger 12. The nanoprogramming control unit returns to the initial state and is ready to receive a new operation code at the first input 25 of the device for the execution of the next microprogram.

Thus, in the proposed nano-program device, the implementation of the control of the duration of the microcode has been implemented, as well as the issuance of micro-operations, the duration of which is longer than the duration of the micro-tact. In addition, it is possible to issue the same micro-operation in one micro-tact several times. The implementation of the primordial disciplines of nanoprogramming allows to expand the functionality of the device and increase its speed.

The increase in the speed of the proposed device as compared to the known one can be estimated by the total time of decreasing the execution of the microprogram of N, single-ended and NH multi-tact dT micro-commands when implementing a device with variable (varying) micro-tact:

AT TI-T, (u) ii}.

It is obvious that the speed of the device being offered is the greater, the greater the number of multi-tact micro-instructions available in the microprogram, and the greater the number of micro-operations performed in the first micro-tact nano-tacts.

Then for an example (Fig. 4) speed (execution time of the presented micro-instructions)

TI K-m-To 3-8 -To 24To, where m is the number of nano-tacts in a micro-tact;

That is the duration of the nanotact; K is the number of microstates for which the firmware is executed.

For the proposed nanoprogramming control device, Tg 2tTo + 5To 21T ". Then 8Т - 100 ° /, 13 ° / о.

In addition, the field of application of the proposed device is expanded by realizing the possibility of issuing the next microcommand until the end of the issuance of the most long microoperation of the previous microcommand, realizing the issuance of one microoperation several times in one microtack, as well as the time diversity of incompatible microoperations and their implementations in the same microtack.

)

-thirty

FIG, g

Phi.1

Claims (1)

NANOPROGRAM CONTROL DEVICE, containing two memory blocks, address register, buffer register, nano-program number register, counter, address shaper, address switch, two address decoders, start trigger, clock pulse generator, block of AND elements, seven AND elements, and an operation code input the device is connected to the first information input of the address switch, the output of which is connected to the information input of the address register, the first output of the address register is connected to the input of the first address decoder, the output of which the second is connected to the address input of the first storage unit, the output of which is connected to the information input of the buffer register, the output of which is connected to the second information input of the address switch, the output of the modified discharge of the buffer register is connected to the control input of the address switch, the output of the modified discharge of the buffer register is connected to the control input address generator, the first information input of which is the input of the logical conditions of the device, the output of the code of logical conditions of the buffer p the register is connected to the second information input of the address generator, the output of which is connected to the second information input of the address switch, the output label of the end of the microcommand of the buffer register is connected to the control input of the address switch, the output of the register of the number of nanoprograms is connected to the input of the second address decoder, the output of which is connected to the address input of the second storage unit, the input of the device is connected to a single input of a start trigger, a single output of which is connected to the input of a clock generator, characterized in that, in order to improve performance, it contains a control trigger, two delay elements, the first output of the clock being connected to the first input of the first AND element, the output of which is connected to the sync input of the address register, the second output of which is connected to the information the input of the register of the number of nanoprograms, the second output of the clock generator is connected to the first inputs of the second and third elements And, the output of the second element And is connected to the clock input of the buffer register g ra, the first output of the generator ora clock is coupled to a direct input of the fourth AND gate and a single trigger control input, a single output of which is coupled to a second input of the third AND gate, whose output is connected to the clock terminal. register of the number of nanoprograms and a counter whose output is connected to the second input of the second address decoder zero. control trigger output is connected. with the second input of the second element And and the input of the first delay element, the output of which is connected to the second input of the first element And and the inverse input of the fourth element And, the output of which is connected to the first inputs of the fifth, sixth, seventh elements And and the first input of the block of elements And, output the end of the nanoprogram of the second storage unit is connected to the second input of the fifth element And and the inverse input of the seventh element And, the output of which is connected to the counting input of the counter, the output of the fifth element And through the second delay element to the input by setting the register number of the nanoprograms, the counter and the zero input of the control trigger to “0”, the output of the end of the microprogram of the second storage unit is to the second input of the sixth AND element, the output of which is connected to the installation input in “O” of the address register, the installation input in “0” buffer register and the zero input of the start trigger, the information output of the second storage unit is connected to the second input of the AND block, the output of which is connected to the input of the nanooperation register, the output of which is the output of the device.