SU995091A1 - Multi-program control device - Google Patents

Description

The invention relates to computing and can be used in firmware control devices.

A micro-command memory is known, which contains a micro-command accumulator, switches, a phase decoder for operations, an address driver, an operation phase counter and a phase 1 protection drive for operations.

The drawback of the device is that the speed of its operation is also determined by the time it takes for the drive to select microcommands for the operation to be performed, which makes it impossible to use it as part of fast-response digital computers.

The closest in technical essence to the present invention is a micro-command device that contains a drive whose address buses are connected via the operation decoder and the operation register of the address former with the first inputs. microinstructions memory, the first drive outputs are connected to the corresponding inputs of switch k-groups, the second outputs are connected via a phase decoder to the control inputs of the k-groups

The simulators are the outputs of which are the outputs of the memory of the micro-command device 2.

The speed of operation of this device is limited by the time it takes for the drive to select all the microcommands for the operation to be performed sequentially, which makes it impossible to use it in high-speed operation;

There are 10 topics in which the speed is determined by the time of transmission of information through the basic logical elements AND, OR, and NOT.

The purpose of the invention is to increase fast

15 roteystn work device. ,:

This goal is achieved by the fact that a microprogram control device containing a microinstructions memory block, an operation decoder, an operation register, K-groups of AND elements (k is the maximum number of phases in an operation) and a phase decoder, and a; The microcontroller’s memory input is connected via an operation decoder.

25 by the output of the operation register, the information input of which is connected to the code input of the following operation of the device, the first inputs of the elements And to the groups are connected to the output of the phase decoder

30, respectively, and the outputs with the information output of the device, additionally contains two switches, two registers of operation microcommands and a trigger, the second inputs of the AND elements to the groups are connected respectively to the outputs of the first switch, the control input of which is connected to the inverse output of the trigger, the direct output of which is connected to the control input of the second switch, the first and second information inputs are connected c to the first and second outputs of the microcommand memory block, the first second outputs of the second comm The first and second registers of the microcode of operations are connected to the first and second information inputs of the first switch, the counting input of the trigger is connected to the control input of the operation register and connected to the input of the device clock pulses; the input of the phase decoder is connected to the information input of the device properties. The drawing shows the functional diagram of the proposed device. The device contains a block of 1 micro-commands, a decoder 2 operations and a register 3 operations of the imaging unit 4 addresses, input 5 of the code of the next operation of the device, K-groups of elements Ib {k is the maximum number of phases in the operation), decoder 7 phases, information output 8 devices, switch 9, registers 10 and 11 microinstructions. operations, commutator 12, trigger 13, input 14 clock pulses of the device, information input 15. The proposed device operates in the following way. Suppose that in the initial state, the counting trigger 13 connects the information outputs of block 1 through switch 9 to the information inputs of the first register 10 microcommands of the operation, and the information outputs of the second register 11 microcommands of the operation connects through switch 12 to the inputs of the k-groups of elements And b. Then in the register of 10 microcommands of the operation information about all microinstructions distributed strictly on phases is recorded. Kotor should be used only when performing followups on the order of the operation, In register 11 microcommands of the operation, information on all microinstructions is recorded, which is also strictly in phase was used when performing the current operation. When each pulse arrives from an external control device and input 14 into register 3 of operation from input 5, the code for the next order of operations that is generated in the external etching device is recorded, and the counting trigger 13 is set in the following order by order. the pulse to the input 14 (relative to the initial state given above) of the counting trigger 13 is set to the next in order. In this case, the trigger trigger 13 connects the information outputs of the block I through the switch 9 to the information inputs of the second register 11 microcommands of the operation, generates information about all the microcommands for the next order of operations, and connects the informational outputs of the first register ilO of the microcommands of the operation, which contains information about all microcommands for the current operation, through switch 12 to the inputs of k-groups of elements AND 6. When performing each of the phases of the operation, information from the output of switch 12 passes through only one of the k-groups elements and 6 (i.e., a part of information, but which corresponds to a micro-command) to the outputs 8 of a micro-command storage device. The order of connection of the AND 6 groups is controlled from an external control device via a 7 phase decoder. Each time the next pulse arrives at input 14, switch 9 and switch 12 are set to the opposite position, while registers 10 and II of the microcommand operations change roles (write 10 and read 11 or vice versa read 10, and write 11). Positive technical effect from the use of the proposed device; consists in increasing the operation speed of the device by selecting from block 1 by one call to it (10-0.1 µs) all micro commands necessary for performing the operation without increasing the length of the word selected from the accumulator, which is achieved by grouping all control signals are strictly in phases, and then this word is written into the microcommand register of the operation and decrypted in phases (i.e. converted into microcommands) at the output of the device without referring to block 1., i.e. after a time equal to the reading of the register 0.10, 05 μs; combining in time the slow process of recording all micro-instructions from block 1 into one of the registers of micro-commands for the next order of operations (10-0.1 µs) with the fast process of forming micro-commands (the number of which can reach 8-10 by the number of phases) for performing the current operation (0.1-0.5 µs) by reading it from another register of micro-commands of the operation strictly in phases (i.e. in micro-commands) to the outputs of the device without referring to slow operation in block 1.

Claims (1)

1. Author's certificate of the USSR 635512, cl. G 11 C 11/00, 1976. 2, USSR author's certificate  490179, cl. G 11 C 11/00, 1973 (prototype).