SU135106A1 - Pulse Generator - Google Patents

Description

Burst generators using shift registers as memory elements of the number of pulses in a burst are known. Also known are devices in which feedback is used to increase the capacity of the ring counting circuits. In such devices, the clock pulse generator operates continuously. This leads to unreasonable loss of power in the pauses between bursts of pulses.

In the described generator of pulse bursts in the pause between the bursts, the clock pulse generator does not work, since the latter is triggered from transfer pulses in the register through a delay element.

The drawing shows a skeletal diagram of the pulse burst generator.

The device contains a shift register consisting of five cells (for example, seven). The cells / -7 are connected in series, with the cells b p 7 connected to the feedback cell 8. This cell provides a recalculation of 2, where n is the number of cells in the register. The input signal acting through the clamp 9 on the first cell simultaneously enters the delay element 10, and then to the input of the clock pulse generator //. The clock pulse will move the recorded information from the cell / cell 2.

At the moment of transferring information to the delay element U along the circuit 12, they are given an 1 pulse, which again makes the clock pulse operate. In one of the combinations, the signal in circuit 12 does not appear, and the generator // stops. In this case, when the memory register contains seven cells, this will happen 127 cycles after the start of operation. By changing the number of cells in the memory register, as well as the order of entering information from the triggering input signal, it is possible to obtain a different number of pulses in a packet, which is removed from the clamp 13.

- 2 L 135106 The subject invention

The generator of packs of pulses using a shift register covered by logical feedback, characterized in that, in order to reduce energy consumption, the outputs of register bits through the OR circuit and the delay element are connected to the input of the clock generator.