SU556495A1 - Memory device - Google Patents

Description

An interchangeable address, to two cells of a frame, o “o, has a higher response rate.

However, the field of application of this storage device is limited due to the impossibility of adjusting the cycle time without changing the clock frequency.

The purpose of the invention is to expand the field of application of devices a.

This is achieved in that the proposed device is inserted in series with a task block. pulses of various durations and a unit of comparison, as well as additional elements AND, one of the inputs of which are connected with the outputs of the distributor. The inputs of the additional elements And are connected to the control input of the distributor and the output of the comparison unit, the inputs of which are connected to other outputs of the distributor. The outputs of the additional elements And are connected to another input of the neipBoro register.

The drawing shows the functional diagram of the device.

The storage device contains a drive 1, made on the registers, a valve, a block 3 for setting pulses of various duration, a block 4, the main elements AND 5 and additional elements AND 6. Before starting, the memory of drive 1 and the valve 2 are set to zero and a delay cycle time code is recorded in a pulses setting unit of various durations.

When the memory is operating, the information inputs of the cells. 1 of the drive 1 receive information words, and the input of the distributor 2 receives clock pulses. The impulse from the output of the distributor 2 is fed to the first control input of the corresponding memory cell of the packer 1 and to the second control input of the next memory cell of this drive. In this case, the next information word is written into the corresponding memory cell and the delayed information word is read (in the second and subsequent cycles) from the next cell. The signals from the outputs of the distributor 2 are fed to the second inputs of the comparison block 4, to the first inputs of which signals are output from the outputs of the pulses setting block of various duration. When the codes arriving at the inputs of the comparator unit coincide, a signal is generated at its output, which is fed to the second inputs of the AND 6 elements and to the control input of the distributor 2. The AND 5 element, at the first input of which this

The moment the signal from the output of the distributor 2 acts, transmits this signal to the second control input of the first memory cell of acolit 1. In this case, the next information word is written into the corresponding memory cell, and the information is read from the next and first memory cells of accumulator 1. Simultaneously, the distributor 2 is a signal from the output of the

4 is reset, and when the next clock pulse arrives, it generates a signal at the first output, allowing the next information word to be written to the p & memory cell and reading information from the second memory cell of drive 1.

In order to avoid malfunctions of the memory at the expense of races, a signal to the control input of the distributor 2 can be delayed.

The proposed memory device, having a pulse setting unit of various duration, a comparison unit and AND elements with new connections, provides an adjustable delay. This allows us to extend the application area of the device, in a number of cases to reduce the amount of delayed memory used in the equipment, increase the oneipativnost operation of such equipment and to provide virtually all needs for the delay time when using the specified number of types of such memory devices that have the maximum target speed. .

Claims (1)

Invention Formula A storage device containing a drive made on the registers, one of the inputs of which are connected to the outputs of the main elements AND, the outputs of registers are connected to the outputs of the device, one of the inputs of the elements AND connected to the outputs of the distributor, and other inputs of the registers except the first register, others The inputs of the elements I are connected to the inputs of the device, characterized in that, in order to expand the field of application of the device, series-connected pulses of various durations and blocks are inserted into it comparison and additional And elements, one of the inputs of which are connected to the outputs of the distributor, the inputs of additional elements And are connected to the control input of the distributor and the output of the comparison unit, the inputs of which are connected to other outputs of the distributor, the outputs of the additional elements And are connected to another input of the First Register.  -