SU1635225A1 - Device for delay of digital information with control - Google Patents

Abstract

The invention relates to computing and can be used in delay lines of digital information. The aim of the invention is to simplify the device. The device contains an element AND 1, a counter 2 modulo (n + 1), the first 3 and second 8 convolution blocks, an address generation block 4, accumulator 5, register 6 check bits, output register 7, comparison block 9, D-flip-flop 10, address register 11. The device delays the digital information by the value of n, where n is the number of accumulator cells, it is checked in each cycle of the delay on one cell of the accumulator. Thus, for n delay cycles, all pens of the accumulator are checked. 2 Il.

Description

p "g /

The invention relates to computing and can be used in delay lines of digital information.

The aim of the invention is to simplify the device.

FIG. 1 shows a block diagram of the device; in fig. 2 are timing diagrams explaining the operation of the device for, where n is the delay value.

The device contains an AND 1 element, a modulo-2 counter (n + 1), a first convolution unit 3, an address generation unit 4, an accumulator 5, a check digit register 6, an output register 7, a second convolution unit 8, a comparison unit 9, D- trigger 10, address register 11; The diagram shows the input 12 of the device synchronization, the information input 13 of the device, the input 14 of the reset, the output 15 of the address of the failure, the information output 16 of the device, the output 17 of the control device.

The device works as follows.

At the initial moment of time, the registers 6, 11, the device trigger 10, the address generation unit 4 and the module 2 modulo (n + 1) are reset by the input signal 14 of the reset.

Next, the information input of the device 13 begins to receive the words of the delayed sequence, followed by a square wave type sync pulse at the sync input of the device 12. During the first half of the clock cycle, the information recorded 5 n clock cycles back to this cell is read, and during the second half of the clock cycle, the the same cell of input information, which, in turn, will be read in n cycles. The address generation unit 4 in this case sequentially iterates the addresses of the accumulator cells, ensuring that the next delayed word is written into the next memory location. The delay value n (where n is the number of cells) is determined by the recalculation factor of the address generation unit 4, which is a counter modulo p.

One delay cycle is n clock cycles. In each delay cycle, the check bits calculated by the second convolution unit 8 are compared for the information read from the ith cell of the accumulator with the check bits calculated by the first convolution unit 3 for the same information before writing it to the lth cell of the accumulator in the previous delay cycle. The check bits calculated by the first block of 3 convolutions are stored in the register of 6 check bits. In each subsequent cycle, the comparison result for the i-th cell is fixed and the calculated bits for the next (K1) -th accumulator cell are recorded. Thus, for n delay cycles all the accumulator cells will be checked.

The result of the comparison is recorded in the D trigger 10 for the duration of one cycle. If the check bits calculated by convolution blocks 3 and 8 as a convolution modulo m, coincided, then the storage cell of the accumulator

0 is working normally and the signal O from the output of the comparison block 9 is recorded in the D-flip-flop 10. If the comparison did not take place, the drive cell under test fails, then the D-flip-flop 10 records the signal 1, which goes to the control output of the device 17 and fixes the address of the faulty cell of the accumulator in the register 11 of the address. At the same time, the signal O comes from the inverted output of the D-flip-flop 10 to the second input of the element I 1, thereby blocking the arrival of synchronization pulses to the counter 2. Thus, the control system stops and at the output of the register 11 the address is faulty

5 storage cells 5.

After elimination of the malfunction, in order to search for the next malfunctioning cells, it is necessary to give the reset signal again at the output 14 at the beginning of the next delayed cycle,

The fixation of the comparison results and recording in the register 6 check bits for the next checked cell are made on the leading and trailing edges

5 signals from the output of counter 2 loan modulo (n + 1), respectively.

Claims (1)

The invention includes a digital information delay device with a control comprising an address generation block, a storage unit, first and second convolution units, an output register, a comparison unit and an AND element, the synchronization input of the address generation unit being connected to the control input of the storage unit and 5 is the sync input of the output register and is the sync input of the device, the information input of the accumulator is connected to the input of the first convolution unit and is the information input of the device, the output of the address generation unit is connected to the address input of the accumulator, whose information output is connected to the input of the output register connected to the input of the second convolution unit 5 and is an information output of the device, the output of the second convolution block is connected to the first input of the comparison block, characterized in that, in order to simplify the device, a modulo (n + 1) counter is entered into it. where n is the delay value, the control bits register, the address register and the D-flip-flop, the direct output of which is connected to the synchronization input of the address register and is the device control output, the inverse output of the D-flip-flop is connected to the second input of the element And the input of which is connected to the synchronization input of the device, the output of the element I is connected to the synchronization input of the counter modulo n + 1, the output of which is connected to the synchronization inputs of the register of check bits and D-flip-flop, the output the first convolution unit is connected to the input of the check bits register, the output of which is connected to the second input of the comparison unit, the output of which is connected to the D-flip-flop input, the output of the address generation unit is connected to the information input of the address register, the reset input of which and the reset inputs of the address generation unit, the modulo counter (n + 1), the check digit register, the output register, the D-flip-flop are combined and are the device reset input. ) zing  simroniiiii 12 Vyyud block address 4 Informational 13 hours was the device See output on the counter m pada "(p 1) f Vyhod Bek Comparison 1 2 3 4 1 2 3 4 1 2 5 4 gsc pg T T T -DTJnJTjTJTJThj UT7U7X U7 X T Y Fisher vitraa catch f 2i. Zsikl