SU1308885A1 - Device for eddy-current flaw detection - Google Patents

Abstract

The invention relates to eddy current testing means for conducting materials and products and can be used to control surface cracks in the automatic scanning mode of the product surface. The aim of the invention is to increase the monitoring performance by increasing the impulse response of the object. The signal from the primary converter is fed to analog-to-digital converter 4 of the following type. If the rate of change of the information signal does not exceed its speed, the voltage from the comparator 5 is fed to the selector 11 and in each clock cycle

Description

There is no counting direction, and the output code is almost constant. When a defect appears, the clock pulses on. Are accumulated, after which the control signal of the defect tester 14 appears. At the same time, the successive approximation code starts to accumulate in the difference difference block 8

smoothed counts. At this time, the circuit characteristic of the defect. 1 il.

The invention relates to eddy current non-destructive agents (its controlling conductive materials and products made from them and can be used to control surface cracks in carbon-graphite composites in the mode of automatic scanning of the product surface.

The aim of the invention is to increase the productivity of the control in the automatic mode due to the impulse response characteristics of the defect.

The drawing shows a block diagram of a device for eddy-current flaw detection.

The device for eddy current testing contains, in series, a harmonic voltage generator 1, a resonant system 2 with a eddy current converter, an amplitude conversion circuit 3 of the signal, and an analog-to-digital converter 4 consisting of a comparator 5; the first input of which is connected to the output of the amplitude conversion circuit 3 of the signal, the reversible counter 6, the control input of which is connected to the output of the comparator 5, and the digital-to-analog converter 7, whose input is connected to the output of the reversing counter 6, and the output to the second input of the comparator 5. The device contains a series of smoothed samples difference allocation unit 8 connected in series, the information input of which is connected to the output of a reversible counter 6, and a register 9. In addition, the device has a series connection data conjunctor 10, selector 11, trigger 12 mode, shaper 13 codes, flaw detector 14 and circuit

1308885

The prohibit signal generation unit 15 blocks transmission until the end of the accumulation mode. To fix the pulse. These characteristics are used in block 16 of the impulse response characteristic of the defect, which allows to memorize in the recorder 18 only the differences of the smoothed samples, i.e. impulse5

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Forming the inhibit signals / first; the input of which is combined with the input of the defect tester 14 and the third input of the reversing counter 6 and connected to the forward output of the mode trigger 12, the second input combined with the second input of the conjunctor 10 and connected to the inverse output of the mode trigger 12, the third input of the circuit The inhibit signal generation unit 15 is combined with the reset input of the mode trigger 12 and connected to the control output of the imager "13 codes, the data output of which is connected to the input of the reversing counter 6, and the output of the signal conditioning circuit 15 This is connected to the clock. input of register 9, the control inputs of the selector 11 and the shaper 13 of the code are combined and connected to the output of the comparator 5. The device also contains a block 16 for impulse response of the defect, the first input of which is connected to the register 9, and the second input - to the output reversible counter.6, control block 17, the first output of which is connected to the fourth input of the inhibit signal generation circuit 15, the first input of the conjunctor 10 and clock inputs of the code generator 13 and the reversing counter 6, the second output block 17.up The control unit is connected to the second input of the block 8 for allocating the difference of smoothed samples, and the third output of the control unit 17 is connected to the fifth input of the prohibition signaling circuit 15, the recorder 18 connected to the output of the impulse response block 16, the third input of which is connected to the code generator 13 .

The prohibit signal generation circuit 15 comprises a serializer 19, a counter 20, a trigger 21, a disjunctor 22 and a second conjunctor 23. The inputs of the conjunctor 19 are the second and third inputs of the prohibition signal generation circuit 15. The setup input of the trigger 21 is the first input of the inhibit signal generation circuit 15. Second

the input of the disjunctor 22 is the third input of the signal forming circuit 15. The second input of conjunctor 23 is the fifth input of the inhibit signal generation circuit 15, and the output of conjunctor 23 is the output of this circuit.

The defect impulse response unit 16 includes a serially connected register 24, a comparator 25 and a pulse shaper 26, a coincidence circuit 27, a delay element 28, a trigger 29 and a conjunctor 30. The information input of the register 24 is the second input of the impulse response characteristic 16. With the information input of the register 24, the first input of the comparator 25 is combined. The first input of the coincidence circuit 27 is the first input of the impulse response characteristic selection unit 16. The output of the comparator 25 is connected to the second input of the matching circuit 27. The output of the pulse former 26 is connected to the net input of the trigger 29, as well as to the setup input of the register 24. The first input of the conjuncer 30, combined with the input of the delay element 28, is the third input of the defect impulse response unit 16. The second input of the conjunctor 30 is connected to the inverted output of the trigger 29, whose setup input with the single output of the delay element 28. The output of the conjuncer 30 is connected to the control input of the register 24. The output of the matching circuit 27 is the output of the defect impulse response unit 16.

The device works as follows.

With automatic scanning of a defect-free surface of the material (not shown), the rate of change of the output voltage of the amplitude-conversion circuit 3 of the signal is not limited.

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speeds up the analog-digital converter 4. At the same time, the direct output of the mode 12 trigger is logical O, the investment output is logical 1. The clock pulses from the output of the control unit 17 pass through the conjunctor 10 to the counting input of the selector 11. The output voltage of the comparator 5, arriving at the control input of the selector 11, changes the counting direction (totalization or subtraction of clock pulses) depending on whether the compensating voltage at the second input exceeds the voltage at the first input of the comparator 5 or vice versa. If the analog-digital converter 4 has enough speed and its input voltage is monitored with an accuracy of ± 1 low-order, then the output level of the comparator 5 changes on each clock (on each clock, the comparator 5 changes its state to the opposite). At the same time, the counting direction of the selector 11 changes on each clock cycle and its output code practically retains its value.

If the voltage at the first input of the comparator 5 changes so fast that the compensating voltage at the second input does not catch up with it (a defect in the control zone), then the output level of the comparator 5 remains unchanged. In this case, the selector 11 produces the accumulation of clock pulses in one direction. When a certain number of pulses accumulate (for example, 16) a pulse appears at the output of the selector 11 (the selector seems to make the sixteenth pulse), which sets the mode trigger 12 to one state, while the Selector 11 returns to the initial state. The occurrence of a logical 0 on the inverse output trigger mode 12 closes conjunctor 10 for clock pulses.

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Logic 1 from the direct output of the mode trigger 12 sets the code generator 13 to the operating state and it begins to generate a sequential approximation code. The successive approximation code is fed to the input of the installation of the bits of the reversible counter 6, and since there is a logical 1 at the installation input of the reversing counter 6, this code is transmitted to

the input of the digital-to-analog converter 7. Simultaneously, the output of the tripler 12 of the mode of logical 1 goes to the defect detector 14, which marks the location of the defect. one

In the trail mode, block 8, in the difference between the smoothed readings, accumulates the measurement results on each: clock tick of clock pulses and generates a code of successive approximation. In this case, the trigger 12 mode is in a single state. Logic 1 arriving at the setup S input of the trigger 21 sets it to one state, while the inverse output of the trigger 21 is logical O. After the formation of the sequential approximation code, a pulse is generated at the control output of the code generator 13, which is applied to the third input of the inhibit signal generation circuit 15, i.e. to the input of the disjunctor 22. The duration of this pulse is equal to the period of the clock pulses, therefore the corresponding control pulse passes through the conjunctor 23 to the control input of the register 9 and the corresponding difference value arrives at the output of the register 9. Since the block 8, the difference of the smoothed samples difference, works with a delay, then after the count using the sequential approximation code, it is necessary to skip N ticks.

This is accomplished using a prohibition signal generation circuit 15. The inputs 2 and 4 of the scheme, i.e. to the inputs of the conjunctor 19, respectively, comes the level with inverse1 of the output of the trigger 12 mode and clock pulses. When the digital samples begin to arrive again, the mode trigger 12 goes to the zero state, a logical unit appears at its inverse output and the clock pulses start to flow to the counter 20. At the output of the counter 20, an N-pulse is output that arrives at the clock trigger input 21. And since at the same time the direct output of trigger 12 of the mode is logical O, then at the time of the first arrival of the sync pulse trigger 21 goes to the zero state and the logical T from its inverse output enters through disjunctor 22 n input conjunctor 23. In this case, soot

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The corresponding control pulse arrives through the conjunctor 23 to the control input of register 9, moving the difference of the smoothed samples to its output. To fix the impulse responses, a block 16 is used to allocate the impulse response of the defect. When the trigger 29 is in the zero state, at its inverting output it is logical 1, but since there are no pulses at the other input of the conjunctor 30, the information at the output of the register 24 is not transmitted. In this case, the output of this register is set to the highest code value. In this case, the output of the comparator 25 is the logic level O and the information through the circuit 27 does not pass to the recorder 18. If there is a defect in the control zone, an abrupt change in the output voltage of the amplitude conversion circuit 3 of the signal occurs. The trigger 12 of the mode goes into a single state and begins to form a counterbalance sequential approximation code. At the end of the code generation, a pulse appears at the control output of the code generator 13, which is fed to the input 3 of the defect impulse response selection unit 16. And since at the output of the trigger 29 at this moment is logical 1, this impulse passes to the control input

5 of register 24, transmitting to its output the difference of smoothed readings corresponding to the instant of the first count of the successive approximation, i.e. the first steep part of the modulation characteristic of a defect having a bell-shaped appearance.

Depending on how steep the following sections are

from the modulation characteristic, readings from the output of the reversing counter are generated either by using the following analog-digital converter 4 or by using

sequential approximation code, but in any case, in the upstream portion of the modulation characteristic, they exceed in magnitude the value of the first sample recorded in the register

g 24. In atioM. the case at the output of the comparator 25 is logical 1 and the information through the coincidence circuit 27 is passed to the registration. The same process continues on the downstream mod0 branch.

tional characteristics until the current code values become less than the first successive approximation. As the current value becomes less than this count, the comparator 25 is transferred to. O, a negative impulse generator 26 generates a pulse, which triggers the trigger 29 to the zero state (the trigger is set to one state by the delayed pulse from the control output of the coder 13 code) and at the same time sets the maximum code value at the register output 24, Thus, the recorder 18 transmits the values of the difference of the smoothed samples, describing only the impulse response of the defect, and not the process of monitoring defect-free areas of the material.

Claims (1)

Invention Formula A device for eddy current testing comprising a harmonic voltage generator connected in series .5 a resonant system with a eddy current converter, an amplitude conversion circuit and an analog-to-digital converter consisting of a comparator connected in series, the first input of which is an input of an analog-to-digital converter, reversible counter and D / A converter j whose output is connected to the second input of the comparator, connected in series with the control unit laziness, the output of which is connected to the control input of the reversible counter, the block of the difference of smoothed Editor A, Gratilllo Order 1790/34 Compiled by Yu.Glazkov Tehred L.Oleynik Proofreader N.Korol Circulation 777 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., d, 4/5 Production and printing company, Uzhgorod, Projecto st., 4 five samples, the second input of which is connected to the output of the reversible counter, and the register, as well as the recorder, so that, in order to increase the performance of the control in automatic mode, it is equipped with a block for the impulse response of the defect, the first input of which is connected to penicTpy, 0 the second input is connected to the output of the reversible counter, and the output is connected to the recorder, a prohibition signal generating circuit, a control input of the terminal is connected to the control unit, and the output is connected to a clock input of the register connected in series by a conjunct, selector, mode trigger, the direct output of which connected to the first input of the formation of the prohibition signals, and the inverse output is connected to the second inputs of the conjunctor and the formation of the prohibition signals, and the driver of the code whose output is connected to the input down counter data, control output coupled to the mode latch reset input and a third input signal generating circuit and a prohibition unit impulse vscheleni 0 characteristics of the defect, the counting input of the code conditioner is combined with the first input of the conjunctor and the fourth input of the inhibit signal generation circuit and connected to the output of the block 5, the control input of the code generator is combined with the control input of the selector and connected to the output of the comparator, and a defect detector, the input of which is combined with the third About the input of the reversible counter and is connected to the direct output of the mode trigger. 0 five