SU1287181A1 - Averaging device - Google Patents

Abstract

This invention relates to a measurement technique. The purpose of the invention is to simplify the device. The device contains a delay element, triggers. clock generator, registers, adder, counter, logic elements. The information, represented by binary coded signals, passes through a delay element before entering the adder. In this case, if the signal has a negative sign, the information moves from the negative representation region to the positive region. With triggers, the AND element and the EXCLUSIVE OR element, the representation region of the binary-modulated signals is corrected for negative numbers. 1 il.

Description

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The invention relates to a measuring technique and can be used in automated and automatic measuring systems.

The purpose of the invention is to simplify the device.

The drawing shows the block diagram of the proposed device for averaging.

The device contains elements OR - NOT 1, trigger 2, element IZ, trigger 4, element NOT 5, element OR-NOT 6,

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Delay element 7, EXCLUSIVE OR 8, one-bit adder 9, bit S

It is assumed that the area predisposed to -28 is equal to 5 and 1.11001. Delays of 0.0111001 should be considered as O 1.1101010 in terms of 2 and 4 EXCLUSIVE

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register 10, element 11, element OR 12, register 13, elements 14, 15, generator 16 clock pulses, distributor 17 pulses, counter 18, element 19, input 20, output 21.

The device works as follows.

The processing in the device of information represented in the form of a binary sequential additional code, and its advancement is performed using clock clock pulses (TI) taken from the output of generator 16 and generated by the distributor 17 pulses of the main clock pulses determining the beginning and end of the serial code.

Subject to averaging the variable Xi is fed to the input 20 of the device.

To illustrate the operation of the device, the averaging of the following four numbers was chosen as an example: 92, -88, 60, and -28, represented as a 7-bit binary code with a fixed comma (8th bit, signed). The variable X from input 20 goes to the elements OR NOT 1 and 6 (to the second element in

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removed from the first output of the distributor 17 pulses.

From the output of the EXCLUSIVE OR 8 element, the variable X. is fed to a one-digit adder 9 connected to the shift register 10, in which the partial values of the sum of the variables Xj are accumulated.

The number of variables averaged for one cycle of averaging X-j is counted by an n-bit counter 18 (for the considered example), the output of which is a signal that stops the averaging cycle and records the result of averaging in the shift register 13.

Claims (1)

Invention Formula An averaging device comprising a clock pulse generator, a pulse distributor, a counter, a delay element, an adder, the first element I, the input of the delay element being the information input of the device, a clock generator output connected to the pulse distributor input, the first output of which is connected to the first input the first element of the AND, and the second exit - with inverse form), on which it is realized by the input of the counter, characterized in that, for the purpose of simplification. analysis of the sign of X., the resultant of the analysis is fixed on trigger 2, which is set to state 1, if X is negative, and to condition O with positive X. 50 In the element / delay, the value of X. i is subjected to a delay of n cycles, where n is the degree of the averaging coefficient represented in binary (Counting. For the case in question, 55 n 2. Codes of negative Xj when passing through the delay element 7 looking for it entered two registers, two. trigger, EXCLUSIVE CMM element, two elements OR NOT, two elements NOT element OR, second, third and fourth elements AND, with the input of the delay element connected to the first input of the first element OR NOT and. through the first element NOT to the first input of the second element NL-NES, the second output of the pulse distributor is connected to the second inputs of the first and second elements OR NONE; bit s 7181 2 the transition to the positive view is compressed. Thus, in this example, the codes of the numbers -88 and -28, equal to 1.0101000 5 and 1.1100100, respectively, at the output of delay element 7 take the form 0.0101010 and 0.0111001. Restoration of the form (for the considered example, these codes must be O 1.1101010 and 1.1111001, respectively) in the device using triggers 2 and 4, the element AND 3, the element EXCLUSIVE OR 8 and the signal (p-1) -th bit s five about five 0 five 0 removed from the first output of the distributor 17 pulses. From the output of the EXCLUSIVE OR 8 element, the variable X. is fed to a one-digit adder 9 connected to the shift register 10, in which the partial values of the sum of the variables Xj are accumulated. The number of variables averaged for one cycle of averaging X-j is counted by an n-bit counter 18 (for the considered example), the output of which is a signal that stops the averaging cycle and records the result of averaging in the shift register 13. Invention Formula An averaging device comprising a clock pulse generator, a pulse distributor, a counter, a delay element, an adder, the first element I, the input of the delay element being the information input of the device, a clock generator output connected to the pulse distributor input, the first output of which is connected to the first one the input of the first element is AND, and the second output is from Two registers are entered into it, two. . trigger, EXCLUSIVE CMM element, two OR-NOT elements, two NO elements, OR element, second, third and fourth AND elements, and the input of the delay element is connected to the first input of the first OR-NOT element and. through the first element NOT - to the first input of the second element SH-NONE, the second output of the pulse distributor is connected to the second inputs of the first and second elements OR-NOT, ko-12 outputs They are connected respectively to the inputs of the installer in 1 and O of the first trigger, the output of which is connected to the second input of the first element I, the output of which is connected to the input of the installation to 1 of the second trigger input of the installation to which is connected to the second output of the pulse distributor, and the setup input to the initial state is connected to the zero potential bus, the output of the second trigger is connected to the first input of the EXCLUSIVE OR element, the second input of which is connected to the output of the delay switch, and the output to the first input of the adder, the second input of which go is connected to the output of the second element I, and the output is connected to the information input of the first register, the permission input 81 the shift of which is connected to the same input of the second register and connected to the output of the clock pulse generator, the output of the first register is connected to the first inputs of the third and second elements AND, the second input of which is connected to the output of the second element NOT and the first input of the fourth element AND, the second input of which is connected to the output of the second register is the output of the device, the output of the counter is connected to the input of the second element NOT and the second input of the third element AND, the output of which is connected to the first input of the element OR, the second input which is connected to the output of the fourth element And, and the output - with the information input of the second register. Editor S. Lisin Compiled by V. Orlov Tehred A. Kravchuk, Order 7719/53 Circulation 694 VNIIGSh of the USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 I j j nf  J Proofreader T. Kolb Subscription