SU1282113A1 - Universal logic module - Google Patents

Abstract

The invention relates to the field of automation and computer technology and is intended to implement logical functions. The purpose of the invention is to expand the functionality by implementing an arbitrary logical function of n variables. The universal logic module contains information inputs, groups of configured inputs, a group of inputs of the code of the number of the function being implemented, blocks of AND elements, modulo-two adders, logical blocks implementing the generating functions, and the OR element. The number of logical blocks that implement generating functions is equal to the number of classes of functions that make up the complete system. The blocks of elements And carry out the component-wise multiplication of n input information variables by the values of the tuning variables in the first n groups of tuning inputs of the module. The resulting products are componentwise added together modulo-two with the values of the tuning variables on the (n + 1) -and group of the tuning inputs of the module. For a given number of the function being implemented, the outputs of modulo-two adders commute with the inputs of one of the logic blocks implementing the corresponding generating function. At the output of the logic block, the value of the logic function is formed, which through the OR element is output to the module. 1 hp f-ly, 2 ill. (Lu 00

Description

The invention relates to automation and computing and is intended to implement logical functions.

The purpose of the invention is to expand the functionality by implementing an arbitrary logical function of n variables.

Fig, 1 shows the functionality

.n the scheme of the universal logic module; 2 is a functional diagram of one of the possible options for building a switch.

The module contains blocks of elements AND, elements AND 2 of blocks 1 (-1r adders 3, -3 „modulo two, switch 4, logical blocks realizing the spawning function, element OR 6, information inputs 7i-7 of the group of tuning inputs 8 "I.,, Group of inputs 9 of the code number

n. , a group of function inputs and output 10.

Switch 3 contains a group of information inputs 11, a group of control inputs 12, a decoder 13 of the code of the function number, the group of elements And, and the group of outputs 15 15 The universal logic module works as follows.

Signals representing input

variables x.,. .., x ,,.

, x, are fed to the corresponding information inputs 7, -7 of the module. Signals representing w ,, ..., w;, ..,. .., Wj, and Wp respectively. The group of inputs 9 is supplied with the code of the number of the function being implemented. As a result, signals are generated at the output groups of the blocks representing the results of the component multiplication of the variables x, .., ,, ... , x to w ,, ,,,, .. ,, W; w respectively. The signals representing the results of the component-wise modulo two values Wjj with products at the outputs of the blocks are fed to the inputs of switch 4, the switch inputs are connected only to one of its output groups, and the group number is fully determined by the code of the implemented function. The number of logical blocks 5 (-5 in the module is equal to the number of m classes of functions that form the complete system. Each group of outputs of switch 4 is connected to the corresponding logical block 5 .. As a result

five

whatever logical function is implemented, logic block 5 always exists for it; it implements the required generating function, which ultimately ensures the universality of the module.

Boolean functions of the corresponding number of variables are implemented as generating functions in logical blocks. For example, when it is sufficient to implement only two functions as porous functions - AND, OR. In general, logical blocks 5 (-5fy, can be implemented on the basis of chips that implement any basic set, for example, AND, OR, NOT.

Claims (1)

Invention Formula 1, A universal logic module containing AND blocks, modulo-two adders and a logic block implementing the generating function, with the i-th (1 i tn) information input of the module connected to the information input of the i-ro block of AND, j- elements th (1: j p) configuration input of which is connected to the jM input  the group of tuning inputs of the module, the first input of the j-ro element AND the i-ro of the block of elements And is connected to the J-M setup input of the i-ro of the block of the elements And, the second inputs of the elements And the i-ro the block of elements I are combined and connected to the information input of i-ro, the block of elements I, the j-th output of the i-ro of the block of elements I are connected to the i-th input of the j-ro modulo two, The () -th input of the j-ro modulo adder is connected to the J-M input of the (n + 1) -th group of configuration inputs of the module, characterized in that, in order to expand the functional capabilities due to the implementation of the njjo- arbitrary logic function of n variables, the switchboard is introduced into it, the logical blocks implement the generating functions, and the OR element, and the output of the j-th modulo-two adder is connected to the J-M information input of the switch, the group of control inputs of which is connected to the group of inputs of the code of the module’s function number, k- (-1, m is the number of classes of functions that make up the complete system) the group of byodes of the switch is connected to the group of inputs of the logic block that implements the k-th logic function, vy312821 the stroke of which is connected to the kth input of the OR element, the output of which is connected to the output of the module. I. 2. The module of claim 1, about tl and h and yu-. u and with the fact that the switchboard contains the code decoder of the function number and the group of elements AND, and the group of control inputs of the switch Not with the input group of the decoder of the function number code, the k-th output of which is connected to the control input of the k-th group of I elements, whose j-th information input is connected to the jM information input of the switch, the output group of the k-th group of I elements is connected to k -th group of switch outputs. figure 1