SU1282112A1 - Polyfunctional logic module - Google Patents

Abstract

The invention relates to the field of automation and computing. The purpose of the invention is to increase the reliability as well as enhance the functionality due to the possibility of summing the input variables. The module contains three non-equivalent elements, two modulo-two adders, three AND elements, AND-NOT element, three EQUIVALENT elements. Depending on the tuning signals, the module works as an adder, forms transfer signals, and also as a universal logic module that implements all Boolean functions of two variables. 1 il. "

Description

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This invention relates to automation and computing.

The purpose of the invention is to increase the reliability, as well as to expand the functional capabilities due to the possibility of summing the input variables.

The drawing shows the functional diagram of the module.

The module contains configuration input JO 1, information input 2, configuration inputs 3-5, information input 6, configuration input 7, the item NOT

8, the element is UNIQUENESS 9, the sum is l i The motors 10 and 11 are modulo two, the element de 21 and the output 20 are sum and I 12 signals, the EQUIVALENCE element 13, the elem signals And 1 and. And 2, which can take the values O or 1. If the tuning inputs 3, 5 and 7 as the control signals to send information signals and X, the module additionally implements at the outputs 20, 21, 22 p d logical. functions.

The functionality of the module is given in the table.

Thus, at output 22 of the module, with tuning signals O and 1, eight Boolean functions AND 14, the UNEQUALING element 15, the UNIMPLANITY 16 and 17 elements, the UNEQUALITY 18 element, the AND 19 element, the output 20 of the transfer, the output 21 of the sum, the information output 22 and output 23 errors.

The module works as follows.

If the tuning input of module 4 is given a signal AND 4 O, and the information inputs 2 and 6 are fed bits Y and X binary numbers, from the outputs of adders 10 and 11, depending on the value of the control signals I 1 and I 2 Inputs 3 and 5 of the module remove inverse or direct values of input codes Elements 14 and 17; implement: depending on the value of the control signal AND 3 at input 7, the module is a logical product or a logical sum of the output signals of the adders 10 and 11, and the resulting signal This is removed from the output of module 22. Elements 13 and 16 are implemented at output 21 module O signal, which is the signal of the sum of the codes of numbers X and Y, taking into account the signal of the signal supplied to the input of module 1. Elements 9, 12 and 15 realize at the output 20 of the module the signal O transfer to the next bit.

Thus, depending on the value of the signals AND 1, AND 2, FROM on the tuning inputs 3, 5 and 7 of the module, at output 22, a logical product or logical sum over direct or inverse codes of binary numbers is realized. Y and X. At the same time, the sum and carry signals over the direct or inverse codes of the input numbers are implemented at the outputs 21 and 20 of the module, which is determined by the tuning of each / I and the output of Zu are the signals of the sum of transfer. When the X and Y signals are fed to the control inputs, the module at output 22 implements the remaining eight

2Q functions of two variables, in this case, at the outputs 20 and 21, some logical functions of the variables X, Y and Z are also implemented.

In control mode on the setup

25 input 4 is given a signal AND 4 1 and through: through the element IS-NOT 8 is closed. There is a feedback connection from the output of the 20 module. UNEQUALITY 15 and 18 signals are observed like a square wave with a period of UT in the common mode (T is the delay time of the valve), and the output 23 is error 30

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Signal 1. To control the inputs of elements not included in the feedback, inputs 1–3 and 5–7 of the module are fed with an inverse input set 1 1 1 ll O, which also shows a signal 1 at output 40 of module 23. Thus, in the absence of constant faults in the circuit, with two input sets at output 23 of the module, a signal 1 is observed.

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The presence of one or more constant faults of type S. O or S | 1 (where the i-number of the input element in the module circuit) results in either

50 to change the phase of the meander at the output of the UNEQUALITY 18 element by 180, or to the generation failure at the same output, or to the generation failure both at the output of the UNEQUALTABLE 55 HOST 18 element, and at the output of the UNEQUALITY 15 element. This leads to the appearance of the O signal at the output 23 module errors at least in one of the input sets.

  l iMode 21 and output 20 are sum signal and

mi signals And 1 and. And 2, which can take the values O or 1. If the tuning inputs 3, 5 and 7 as the control signals to send information signals and X, the module additionally implements at the outputs 20, 21, 22 p d logical. functions.

The functionality of the module is given in the table.

Thus, at the output 22 of the module, with the tuning signals O and 1, eight Boolean functions are implemented i Moda 21 and output 20 are sum signals and

de / I and output Zu - sum transfer signals. When the X and Y signals are fed to the control inputs, the module at output 22 implements the remaining eight

functions of two variables, in this case, at the outputs 20 and 21, some logical functions of the variables X, Y and Z are also implemented.

In control mode on the setup

input 4 is given a signal AND 4 1 and through the element IS-NOT 8 is closed. feedback from the output 20 of the module is found. If inputs 1 - 3 and 5 - 7 of the module send signals 00000 1, respectively, then at the outputs of the elements UNACTAL 15 and 18 signals of the meander type are observed with a period of YT in the common mode (T is the valve delay time), and the output has 23 errors

35

Signal 1. To control the inputs of elements not included in the feedback, inputs 1–3 and 5–7 of the module are fed with an inverse input set 1 1 1 ll O, which also shows a signal 1 at output 40 of module 23. Thus, in the absence of constant faults in the circuit, with two input sets at output 23 of the module, a signal 1 is observed.

45

The presence of one or more constant faults of type S. O or S | 1 (where the i-number of the input element in the module circuit) results in either

50 to change the phase of the meander at the output of the UNEQUALITY 18 element by 180, or to the generation failure at the same output, or to the generation failure both at the output of the UNEQUAL DEFINITION 55 HOST 18 and the output of the UNEQUALITY 15 element. This leads to the appearance of the O signal at the output 23 module errors at least in one of the input sets.

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Thus, the module performs a logical sum or logical product on the codes of input binary numbers, and also implements all Boolean functions of two variables.

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Claims (1)

Invention Formula A multifunctional logic module containing the first and second elements of EQUALITY, the first element is UNIQUENESS, the first and second elements are AND, and the output of the first element of EQUALITY is connected to the first input of the first element of UNIFORM, the output of which is connected to the first element of EQUALITY is connected with the first tuning input of the module, which is being read. By the fact that, in order to increase the reliability, as well as to expand the functionality due to the possibility of summing the input variables, the module contains two modulo-two adders, the third element is UNIVERSAL, the second and third elements are UNABLE, the third element is AND-NOT, and the second The configuration input of the module .l is connected to the first inputs of the second and third elements of the UNEQUAL DENSITY and the first input of the second element EQUALITY, the second input of which is connected to the output of the third element EQUALITY and the first m input of the second element And, wto Control signals and 1 I2IZ Q1 Q2 | dz ABOUT about eleven about about 1 oh oh oh oh 1 1 1, five five About 0 5 0 five 1124 A swarm whose input is connected to the output of the non-EQUALITY element, the second input of which is connected to the output of the first modulo-2 adder, with the first inputs of the third element UTILITY and the third element And, the second input of which is connected to the output of the second adder modulo two and the second input of the third the EQUALITY element, the output of the third element AND is connected to the second input of the first element EQUALITY, the output of which is the information output of the module, the error output of which is connected to the output of the first element that And, the second input of which is connected to the output of the third element UNEQUALITY, with the first input of the NAND element, and is the output of the module transport, the sum of which is connected to the output of the second EQUALITY element and to the second input of the first EQUALITY element, while the output of the AND AND element is connected to the first inputs of the first and second adders modulo two, the second inputs of which are connected to the first and second information inputs of the module, respectively, the third inputs of the first and second adders on the Kodul two are connected to the third and fourth tuning inputs of the module, the fifth tuning in od which is connected to the second input of AND-NO ,, and the output of the second AND gate second input soedinen.s third element unequal. Realizable functions e X + Y X + Y X + Y X + Y X + Y X + Y X + Y X v y X v y x v y X v y x -y x y X -Y Table continuation