RU2756445C1 - Voltage level converter - Google Patents

Abstract

FIELD: computer technology.

SUBSTANCE: invention relates to computer technology and can be used to build high-speed voltage level converters, including when interfacing elements of electronic systems with multiple power supplies. The voltage level converter circuit contains: five P-type field-effect transistors (1-5) and three - N-type (6-8), direct IN and inverse

input signals, OUT output, VDD high voltage power supply, low power supply output voltage level (GND).

EFFECT: proposed voltage level converter has a higher speed of conversion of high voltage and return to low voltage level.

1 cl, 1 dwg

Description

The proposed invention relates to digital computing and can be used to match circuits with different voltage levels of power supplies and internal signals.

Known signal level converter for MIS transistors [1]. This device is designed to convert the signal voltage level (for example, when interfacing TTL and CMDP logic elements).

The disadvantage of the above scheme is its low performance. The low speed of the circuit is caused by limiting the appearance of a high-level voltage at the output of the circuit through a low-conductivity circuit, up to the connection of a high-conductivity transistor, shunting the low-conductive circuit, which is delayed by the signal propagation time required for sequential switching of two gates.

In addition, each of the output nodes of the trigger, in addition to the gates of the transistors of the output transistors, is connected to the gates of two P-type transistors, which additionally increases the parasitic capacitance of the output nodes of the trigger and delays the switching transient process.

The objective of the present invention is to increase the speed of the voltage level converter.

входных сигналов, подсоединенные к затворам транзисторов, соответственно, восьмого и шестого, выход OUT преобразователя уровня напряжения, вывод питания высокого уровня напряжения VDD, соединенный с истоком первого транзистора, вывод питания низкого уровня напряжения GND, соединенный с истоками седьмого и восьмого транзисторов, причем сток первого транзистора соединен с истоками второго и третьего, сток третьего - со стоком шестого и затвором четвертого транзисторов, и затвор третьего транзистора - со стоками четвертого и восьмого, а затворы второго и седьмого транзисторов соединены между собой введены первый и второй инверторы, входы которых соединены со стоком восьмого транзистора, а выходы, соответственно, первого инвертора - с затворами второго и пятого транзисторов, и второго инвертора - с выходом OUT, затвор первого транзистора соединен с выводом питания низкого уровня напряжения GND, исток четвертого транзистора соединен с выводом питания высокого уровня напряжения VDD, исток пятого - со стоком первого транзистора, сток второго транзистора - со стоком третьего, сток пятого - со стоком четвертого транзистора, и исток шестого транзистора соединен со стоком седьмого.The task is achieved by the fact that the voltage level converter containing P-type field-effect transistors from the first to the fifth and N-type from the sixth to the eighth, inputs of direct IN and inverse

input signals connected to the gates of the eighth and sixth transistors, respectively, the OUT output of the voltage level converter, the high voltage power supply terminal VDD connected to the source of the first transistor, the low voltage power supply terminal GND connected to the sources of the seventh and eighth transistors, and the drain of the first transistor is connected to the sources of the second and third, the drain of the third - with the drain of the sixth and the gate of the fourth transistors, and the gate of the third transistor - with the drains of the fourth and eighth, and the gates of the second and seventh transistors are connected to each other, the first and second inverters are introduced, the inputs of which are connected to the drain of the eighth transistor, and the outputs, respectively, of the first inverter - with the gates of the second and fifth transistors, and the second inverter - with the OUT output, the gate of the first transistor is connected to the power supply terminal of the low voltage level GND, the source of the fourth transistor is connected to the power supply terminal of the high voltage level VDD , source pya that - with the drain of the first transistor, the drain of the second transistor - with the drain of the third, the drain of the fifth - with the drain of the fourth transistor, and the source of the sixth transistor is connected to the drain of the seventh.

Thus, in the proposed circuit of the voltage level converter, due to the differences from the known device described above, the appearance of a high-level voltage at the output of the OUT circuit through the low-conductivity circuit is excluded before connecting the high-conductivity transistor, since the formation of the output signal at the OUT output always occurs immediately and through only high-conductivity circuits.

In addition, in the proposed voltage level converter, in contrast to the known signal level converter on MIS transistors [1], the loads of the inputs of the first and second inverters and the gate of only one P-type transistor are connected to one output node of the trigger, and to the other output node the trigger is connected to the gate of only one transistor, without the gates of the transistors of the output inverter, which reduces the parasitic capacitance of the output nodes of the trigger and further accelerates the transient process of switching the voltage level converter.

The figure shows a diagram of the proposed voltage level converter.

входных сигналов, подсоединенные к затворам транзисторов, соответственно, восьмого (8) и шестого (6), выход OUT, вывод питания высокого уровня напряжения VDD, соединенный с истоками транзисторов первого (1) и четвертого (4), вывод питания низкого уровня напряжения (GND), соединенный с истоками транзисторов седьмого (7) и восьмого (8) и затвором первого (1) транзистора, сток которого соединен с истоками второго (2), третьего (3) и пятого (5) транзисторов, причем сток второго транзистора (2) соединен со стоками третьего (3) и шестого (6) и затвором четвертого (4) транзисторов, а сток пятого (5) транзистора - со стоками четвертого (4) и восьмого (8) транзисторов, затвором третьего (3) и входами первого (9) и второго инверторов (10), выходы которых соединены, соответственно, первого инвертора (9) с затворами транзисторов (2), пятого (5) и седьмого, и второго инвертора (10) с выходом OUT, а исток шестого (6) транзистора соединен со стоком седьмого (7).The proposed voltage level converter contains field-effect transistors of the P-type from the first to the fifth (1-5) and N-type from the sixth to the eighth (6-8), inputs of direct IN and inverse

input signals connected to the gates of the eighth (8) and sixth (6) transistors, respectively, the OUT output, the high voltage supply output VDD connected to the sources of the first (1) and fourth (4) transistors, the low voltage supply output ( GND), connected to the sources of the seventh (7) and eighth (8) transistors and the gate of the first (1) transistor, the drain of which is connected to the sources of the second (2), third (3) and fifth (5) transistors, and the drain of the second transistor ( 2) is connected to the drains of the third (3) and sixth (6) and the gate of the fourth (4) transistors, and the drain of the fifth (5) transistor is connected to the drains of the fourth (4) and eighth (8) transistors, the gate of the third (3) and inputs of the first (9) and second inverters (10), the outputs of which are connected, respectively, of the first inverter (9) with the gates of the transistors (2), the fifth (5) and seventh, and the second inverter (10) with the OUT output, and the source of the sixth ( 6) of the transistor is connected to the drain of the seventh (7).

The proposed voltage level converter is a digital logic device designed to convert the input voltage of a logical unit "1 *" (VCC) into a logical "1" voltage corresponding to the supply voltage of a high voltage level VDD and operates as follows.

- напряжение логической единицы «1*» (VCC). Минимальное значение напряжения логической единицы «1*» должно быть больше либо равно значению порогового напряжения транзистора N-типа. Кроме того, напряжение источника питания высокого уровня VDD («1») и напряжение логической единицы VCC («1*») должны быть больше или равны сумме пороговых напряжений транзисторов Р- и N-типа. Транзистор Р-типа 1 низкой проводимости открыт всегда, т.к. его затвор подключен к источнику питания низкого уровня напряжения «0». На затворы транзисторов N-типа 8 и 9 с входов IN и

поступают напряжения, соответственно, низкого уровня GND («0») и напряжение логической единицы «1*» (VCC). Поэтому транзистор 8 закрыт, а транзистор 6 открыт. Также, в результате действия предыдущего регенеративного цикла транзисторы 2 и 5 открыты, а транзисторы 3, 4 и 7 закрыты, а на выходе OUT преобразователя уровня напряжения установлено напряжение низкого уровня «О» (GND).The initial state. A low level voltage is applied to the GND power pin and the IN input, corresponding to the logic "0" voltage, to the VDD pin - high ("1"), and the input

- voltage of logical unit "1 *" (VCC). The minimum voltage value of the logical unit "1 *" must be greater than or equal to the threshold voltage value of the N-type transistor. In addition, the high-level power supply voltage VDD ("1") and the logic-one voltage VCC ("1 *") must be greater than or equal to the sum of the threshold voltages of the P- and N-type transistors. P-type transistor 1 of low conductivity is always open, because its gate is connected to a low voltage "0" power supply. To the gates of N-type transistors 8 and 9 from inputs IN and

voltage, respectively, low level GND ("0") and the voltage of logical unit "1 *" (VCC) are supplied. Therefore, the transistor 8 is off and the transistor 6 is on. Also, as a result of the action of the previous regenerative cycle, transistors 2 and 5 are open, and transistors 3, 4 and 7 are closed, and a low level voltage "O" (GND) is set at the OUT output of the voltage level converter.

и, следовательно, на затворы транзисторов 8 и 6 поступают напряжения, соответственно, логической единицы «1*» (VCC) и логического «0» (GND), в результате чего транзистор N-типа 8 открывается, а транзистор N-типа 6 - закрывается. Через открытый транзистор 8 на затвор транзистора 3 и входы инверторов первого (9) и второго (10) поступает напряжение низкого уровня «0» (GND). Поэтому транзистор Р-типа 3 открывается, а на выходах первого (9) и второго (10) инверторов устанавливается напряжение высокого уровня VDD, которое поступает на затворы транзисторов 2, 5 и 7 и на выход OUT преобразователя уровня напряжения. При этом транзисторы Р-типа 2 и 5 закрываются, транзистор Р-типа 4 удерживается в закрытом состоянии напряжением высокого уровня VDD, поступающем через открытые транзисторы Р-типа 1 и 3, а транзистор N-типа 7 - открывается. Таким образом, на выходе OUT преобразователя уровня напряжения установлено напряжение высокого уровня VDD, полученное преобразованием входного высокого напряжения логической единицы «1*» (VCC).In the mode of converting the high voltage of the logical unit VCC into the high voltage VDD at the input IN and at the input

and, therefore, the voltages of the logical unit "1 *" (VCC) and logical "0" (GND) are applied to the gates of the transistors 8 and 6, as a result of which the N-type transistor 8 opens, and the N-type transistor 6 - closes. Through the open transistor 8, a low level voltage "0" (GND) is supplied to the gate of the transistor 3 and the inputs of the inverters of the first (9) and second (10). Therefore, the P-type transistor 3 opens, and a high voltage VDD is set at the outputs of the first (9) and second (10) inverters, which is fed to the gates of transistors 2, 5 and 7 and to the OUT output of the voltage level converter. In this case, the P-type transistors 2 and 5 are closed, the P-type transistor 4 is kept closed by the high-level voltage VDD supplied through the open P-type transistors 1 and 3, and the N-type transistor 7 is opened. Thus, the output voltage of the voltage level converter OUT is set to a high level voltage VDD obtained by converting the input high voltage to a logical unit "1 *" (VCC).

- инверсного входного сигнала, и, следовательно, на затворы транзисторов 8 и 6, поступают, соответственно, напряжения логического «0» (GND) и логической единицы «1*» (VCC). Поэтому транзистор N-типа 8 закрывается, а транзистор N-типа 6 - открывается. Через открытые транзисторы N-типа 6 и 7 на затвор транзистора высокой проводимости Р-типа 4 поступает напряжение низкого уровня GND («0»). Поэтому транзистор 4 открывается и через него на затвор транзистора 3 и входы инверторов первого (9) и второго (10) поступает напряжение высокого уровня VDD («1»). Поэтому транзистор Р-типа 3 закрывается, а на выходах первого (9) и второго (10) инверторов устанавливается напряжение низкого уровня GND («0»), которое поступает на затворы транзисторов 2, 5 и 7 и на вход OUT преобразователя уровня напряжения. При этом транзисторы Р-типа 2 и 5 открываются, а транзистор N-типа 7 закрывается. Поэтому через открытые транзисторы 1 и 2 на затвор транзистора 4 поступает напряжение высокого уровня VDD («1»), в результате чего транзистор Р-типа 4 закрывается. Однако, через открытый транзистор Р-типа 5, на затворе транзистора 3 и на входах первого (9) и второго (10) инверторов удерживается напряжение высокого уровня. Поэтому на выходе OUT преобразователя уровня напряжения сохраняется напряжение низкого уровня GND («0»), и схема переходит в исходное состояние.When the voltage level converter switches to the initial state and the mode of formation of a low level voltage GND ("0") at the output OUT, a direct input signal at the IN inputs and

- an inverse input signal, and, therefore, to the gates of transistors 8 and 6, respectively, the voltage of the logical "0" (GND) and the logical unit "1 *" (VCC). Therefore, N-type transistor 8 turns off and N-type transistor 6 turns on. Through the open N-type transistors 6 and 7, a low-level voltage GND ("0") is supplied to the gate of the high-conductivity transistor P-type 4. Therefore, the transistor 4 opens and through it the high-level voltage VDD ("1") is supplied to the gate of the transistor 3 and the inputs of the inverters of the first (9) and second (10). Therefore, the P-type transistor 3 is closed, and a low level voltage GND ("0") is set at the outputs of the first (9) and second (10) inverters, which is fed to the gates of transistors 2, 5 and 7 and to the OUT input of the voltage level converter. In this case, the P-type transistors 2 and 5 open, and the N-type transistor 7 is closed. Therefore, through the open transistors 1 and 2, a high voltage VDD ("1") is supplied to the gate of the transistor 4, as a result of which the P-type transistor 4 is closed. However, through the open P-type transistor 5, a high voltage is maintained at the gate of the transistor 3 and at the inputs of the first (9) and second (10) inverters. Therefore, the OUT output of the voltage level converter maintains a low level voltage GND ("0"), and the circuit returns to its original state.

Thus, in the proposed circuit of the voltage level converter, the formation of the output signal of a high level VDD ("1") at the OUT output occurs immediately and through circuits of only high conductivity, which significantly accelerates the transient process of recharging the output capacitance and thereby increases the operating speed of the circuit.

In addition, in the proposed voltage level converter, in contrast to the known signal level converter on MIS transistors [1], the loads of the inputs of the first and second inverters and the gate of only one P-type transistor are connected to one output node of the trigger, and to the other output node the trigger is connected to the gate of only one transistor, without the gates of the transistors of the output inverter, which reduces the parasitic capacitance of the output nodes of the trigger and further accelerates the transient process of switching the voltage level converter.

Literature

1. USSR author's certificate (SU) No. 1538246, "Converter of signal levels on MIS-transistors" / V.А. Maksimov, A.E. Zabolotny and Ya. Ya. Petrichkovich // Bulletin No. 3 from 23.01.90.

Claims (1)

Voltage level converter containing field-effect transistors P-type from the first to the fifth and N-type from the sixth to eighth, inputs of direct IN and inverse

input signals connected to the gates of the eighth and sixth transistors, respectively, an OUT output, a high voltage power supply terminal VDD connected to the source of the first transistor, a low voltage power supply terminal GND connected to the sources of the seventh and eighth transistors, wherein the drain of the first transistor is connected with the sources of the second and third transistors, the drain of the third transistor is connected to the drain of the sixth and the gate of the fourth transistors, the gate of the third transistor is connected to the drains of the fourth and eighth transistors, and the gates of the second and seventh transistors are interconnected, characterized in that the first and second inverters are introduced, whose inputs are connected to the drain of the eighth transistor, and the outputs of the first inverter, respectively, are connected to the gates of the second and fifth transistors, and the second inverter is connected to the OUT output, the gate of the first transistor is connected to the power supply terminal of the low voltage level GND, the source of the fourth transistor is connected to the power supply terminal v High voltage level VDD, the source of the fifth transistor is connected to the drain of the first transistor, the drain of the second transistor is connected to the drain of the third transistor, the drain of the fifth transistor is connected to the drain of the fourth transistor, and the source of the sixth transistor is connected to the drain of the seventh transistor.

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