KR980012618A - Semiconductor Memory and Manufacturing Method - Google Patents

Abstract

The semiconductor memory includes a plurality of diffusion layers, a plurality of gate electrodes, a plurality of MOS transistors, an interlayer insulating film, and a plurality of metal wirings. The diffusion layers are arranged in parallel to each other on the major surface of the semiconductor substrate. The gate electrodes are arranged in parallel with each other on the semiconductor substrate through the gate insulating film in a direction perpendicular to the diffusion layers. MOS transistors are formed in cross regions including intersections between diffusion layers and gate electrodes at a major surface of the semiconductor substrate, thereby forming memory cells. The crossing regions include a channel through which channel current flows. Data is written into the memory cells by selectively ion implanting impurities in the channels. An interlayer insulating film is formed on a semiconductor substrate including gate electrodes. Metal wires are formed on the interlayer insulating film corresponding to the diffusion layers to function as a mask for ion implantation of impurities. Also disclosed is a method of manufacturing such a semiconductor memory.

Description

Semiconductor Memory and Manufacturing Method Thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory and a manufacturing method thereof, and more particularly, to a mask read only memory (ROM) and a manufacturing method thereof.

In the mask ROM, customer data is written during the manufacturing process. If the data writing step is set within a subsequent period of the mask ROM manufacturing process, the period from the designated time of the program data by the user called TAT (Tum Around Time) to the product delivery time can be shortened. The data writing step is performed after the formation of the gate electrode or after the formation of the interlayer insulating film. The step performed after the formation of the interlayer insulating film is advantageous in terms of the delivery time since the data is written in the latest period of the manufacturing process.

3A and 3B illustrate a conventional flat-cell NOR mask ROM. In this mask ROM, a plurality of n-type diffusion layers 12 each having a linear pattern are formed so as to be arranged in parallel with each other with respect to the main surface of the p-type silicon substrate 11. The plurality of gate electrodes 14 are arranged in parallel with each other through the gate insulating layer 13, and are arranged to be perpendicular to the n-type diffusion layers 12. The memory cells have intersection points between the n-type diffusion layers 12 and the gate electrodes 14 as sources and drains, and regions immediately below the gate electrodes 14 between the n-type diffusion layers 12 are channels. It is configured as MOS transistors used as regions. By selectively ion implanting the p-type impurity in the channel region, the transistor of the memory cell implanted with the p-type impurity is turned off to write data. Reference numeral 16 denotes a metal wiring to be formed in a later step.

In order to perform this data writing, after the interlayer insulating film 15 is formed on the entire surface of the silicon substrate 11 to apply the gate electrodes 14, the resist film 17 is shown in Fig. 3B. It is used on the interlayer insulating film 15. The opening 18 is formed in the resist film 17 while writing data. In this case, when the interval between the n-type diffusion layers 12 is 1.0 mu m, the cross section of the data write opening is set to be a rectangle having an opening diameter L of 1.2 mu m including a mask alignment margin of 0.1 mu m. Since the p-type impurity is ion implanted in the channel region by using the resist film 17 as a mask to form the p-type implanted layer 19, the transistor of the memory cell exposed through the opening 18 is turned off. .

In this mask ROM, the resist film 17 is used as a mask for ion implantation of p-type impurities into the selected memory cell. The resist film 17 must be formed thick to ensure the mask function because ion implantation is performed after the gate insulating film 13, the gate electrode 14 and the interlayer insulating film l5 are formed. As the thickness of the resist film 17 increases, the sidewalls of the openings 18 cannot be formed sharply. Therefore, it is difficult to pattern the ion implantation region by forming the opening 18 with high precision.

On the other hand, as the memory cells are reduced in order to incorporate the recent demand for high density of the memory, the pattern dimension of the mask needs to be further reduced. As a result, the mask alignment margin of the resist mask is also reduced, and higher dimension precision is required for the opening 18. It is difficult to perform high-precision data writing using the mask of the resist film 17.

In order to solve this problem, Japanese Patent Laid-Open No. 4-63472 (first reference) forms a metal wiring along an upper portion of an element insulating oxide film of a memory cell in a NAND mask ROM, and this metal wiring is used for data write ion implantation. The technique used as part of the mask for the present invention is presented. This technique is advantageous for realizing a high density memory because the sidewalls of the metal wiring are sharply formed and the mask dimension can be managed precisely with high precision. Further, Japanese Patent Laid-Open No. 1-184864 (second reference) shortens the TAT by suggesting a technique in which a metal film can be used as a mask for performing data writing after the final protective film is formed.

In the technique described in the first reference, since the metal wiring to be used as a mask must be formed on the device insulating oxide film of the memory cell, the width and pitch of the metal wiring can be reduced by the size reduction of the device insulating oxide film as the size decreases in the memory cell. The width and pitch must be reduced in response to the decrease. However, in order to form a small width deceleration wiring at a small pitch, a mask having a fine pattern must be aligned with high precision. In practice, such metal wiring is very difficult to form.

Although the technique described in the second reference is effective for a single memory cell or memory cell with progressive dimensional accuracy, as shown in Figs. 3A and 3B, the flat cell mask ROM required for realizing high density is required. It cannot be applied directly. In the NOR type mask ROM, the n type diffusion layer serving as the drain of the memory cell transistor overlaps with the p type diffusion layer for data writing due to the mask alignment error. As a result, the resistance and cushion capacitance of the n-type diffusion layer serving as the drain are inappropriately increased to reduce the read rate.

An object of the present invention is to provide a semiconductor memory capable of performing high-speed, high-precision data writing in a MOS mask 170M having fine memory cells and a method of manufacturing the same.

In order to achieve the above object according to the present invention, a plurality of diffusion layers arranged in parallel with each other in the main surface of the semiconductor substrate and a plurality of diffusion layers arranged in parallel with each other on the semiconductor substrate through a gate insulating film in a direction perpendicular to these diffusion layers Formed in intersecting regions including gate electrodes and intersecting points between diffusion layers and gate electrodes in a major surface of the semiconductor substrate to form memory cells, the intersecting regions including channels through which channel current flows, and Is a plurality of MOS transistors written into a memory cell by selectively ion implanting impurities in the channel, an interlayer insulating film formed on a semiconductor substrate including the gate electrodes, and diffusion layers to function as a mask for ion implantation of impurities. A plurality of formed on the interlayer insulating film corresponding to It provides a semiconductor memory comprising in wiring.

1A is a plan view showing a flat NOR mask ROM according to the first embodiment of the present invention.

1B is a cross-sectional view taken along the line A-A in FIG. 1A in the data writing step,

2a is a plan view showing a flat NOR mask ROM according to a second embodiment of the present invention;

FIG. 2B is a cross-sectional view taken along the line B-B in FIG. 2A in the data writing step.

3A is a plan view showing a conventional flat NOR mask ROM.

FIG. 3b is a cross-sectional view taken along the line C-C in FIG. 3a at the data passing step.

* Explanation of symbols for main parts of the drawings

1: p-type silicon substrate 2: n-type diffusion layers

3: gate insulating film 4: gate electrodes

5 interlayer insulating film 6 metal wires

7: resist film 8: opening

The invention will be described in detail below with reference to the accompanying drawings.

1A and 1B show a flat cell NOR mask ROM in accordance with a first embodiment of the present invention. 1A and 1B, a plurality of n-type diffusion layers 2 each having a linear pattern are parallel to each other at equal intervals in the main surface of the p-type silicon substrate 1 on which many memory cells are formed. It is formed to be arranged. The plurality of gate electrodes 4 are equally spaced on the p-type silicon substrate 1 including the n-type diffusion layers 2 through the gate insulating film 3 so as to be perpendicular to the n-type diffusion layers 2. It is formed to be arranged in parallel with each other. The memory cells are alternately used as source regions 2a and drain regions 2b of the n-type diffusion layers 2 having gate electrodes 4, and source and drain regions 2a and 2b. The regions immediately below the gate electrodes 4 between the electrodes are composed of MOS transistors used as channel regions. The interlayer insulating film 5 is formed on the p-type silicon substrate 1 to apply the gate electrodes 4, and the metal wires 6 are formed on the interlayer insulating film 7.

The metal wires 6 constitute column lines or ground lines or other lines of the memory cells, and are arranged on top of the n-type diffusion layers 2 at an array interval twice as large as that of the n-type diffusion layer 2. Formed in parallel with each other. That is, the metal wirings 6 correspond to, for example, the n-type diffusion layers corresponding to the drain regions 2b because the source and drain regions 2a and 2b alternately correspond to the n-type diffusion layers 2. It is formed corresponding to all the other n-type diffusion layers 2 formed to be arranged only on (2). The width of the metal wiring 6 is set to be slightly larger than the width of the n-type diffusion layer 2. Even if a normal alignment error occurs, the metal wiring 6 serves the drain region 2b. After data writing (which will be described later) is performed, a passivation film and an upper line (none of which are shown) are formed to complete the mask ROM.

In writing data in this mask ROM, a resist film 7 is applied on the interlayer insulating film 5 including the metal wires 6, as shown in Fig. 1B. An opening 8 having a rectangular cross section is formed in the resist film 7 in a region corresponding to the memory cell selected for data writing. In this case, when the spacing between the n-type diffusion layers 2 is 1.0 mu m, the dimension L of the opening is set to 1.6 mu m including a momsk alignment margin of 0.1 mu m. As a result, a part of the metal wiring 6 is exposed through the opening 8 of the resist film. The region surrounded by the metal wiring 6 and the inner sidewall of the opening 8 of the resist film is patterned with respect to the actual ion implantation opening 8a.

The p-type impurity is ion implanted through the opening 8a using the resist film 7 and the metal wiring 6 as a mask to form the P-type injection layer 9 in the channel of the selected memory cell. With this process, the MOS transistors of the selected memory cell are turned off to write data. At this time, since the sidewall of the resist film 7 on the side of the drain region 2b in the opening 8a is adjusted by the metal wiring 6 so as to have a sharp vertical surface, the precision of the dimension is the source region 2a. ) On the side of the side wall is higher. After the resist film 7 is removed, a passivation film and an upper line (none of which are shown) are formed to complete the mask ROM.

Even when the resist film 7 has a thickness that reduces the dimensional accuracy of the opening 8, a higher mask dimension precision can be obtained at least on the side of the drain region 2b. The dimension of the opening 8 of the resist film 7 can be increased to 1.6 mu m as described above. As a result, the design and manufacture of the mask ROM is simplified to ensure a stable production supply.

The metal wiring 6 is formed in the dimension which can apply | coat the drain region 2b. Even when a slight alignment error occurs, the p-type impurity is not ion implanted in the drain region 2b even though it may be ion implanted in the source region 2a. Therefore, the p-type impurity layer formed into the channel by ion implantation does not extend to at least the drain region 2b. Increasing the layer resistance and junction capacitance of the drain region 2b can be suppressed to prevent a decrease in operating speed.

Even when the width and pitch of the n-type diffusion layer 2 decrease with the size reduction in the memory cell, the metal wires 6 are on all other n-type diffusion layers 2 corresponding to the drain regions 2b. Is formed. In addition, since the width of the metal wiring 6 becomes larger than the width of the drain region 2b, the metal wiring 6 can be easily formed. As a result, the mask ROM can be formed with high precision.

2A and 2B show a second embodiment of the present invention. Like reference numerals as in FIGS. La and 1b denote like parts, and a description thereof will be omitted. The second embodiment illustrates the case of the metal wiring 6 which can be patterned in micro units. Metal wires 6 are formed on n-type diffusion layers 2 in which source and drain regions 2a and 2b are formed. The metal wiring 6 is formed to the dimension which can apply | coat the n type diffused layer 2 completely. When the data write opening 8 is formed in the resist film 7, two metal wires 6 are exposed through the opening 8 on the side surfaces of the source and drain regions 2a and 2b. The region constituted by the two metal wires 6 and the resist film 7 is patterned with respect to the actual ion implantation opening 8a.

In the above-described alignment, when the ions are implanted through the opening 8 of the resist film 7, the ion implanted region is masked by the metal wires 6 with the two source and drain regions 2a, 2b. Can be patterned with very high precision. Therefore, the dimensional accuracy of the opening 8 of the resist film 7 can be relaxed compared with the first embodiment. The above design and manufacture can be further simplified. Since the p-type impurity implantation layer 9 formed by ion implantation does not extend to one of the source and drain regions 2a and 2b, an increase in the layer resistance and the junction capacitance of the source and drain regions 2a and 2b. Can be suppressed to increase the operating speed of the device.

The first and second embodiments are exemplified in the case where the metal lines are formed on the n-type diffusion layers 2 respectively corresponding to the drain regions 2b and the two source and drain regions 2a and 2b. Metal wires may be formed only on the n-type diffusion layers corresponding to the source regions 2a.

As described above, according to the present invention, the metal wiring is formed on at least one of the diffusion layers constituting the drain and source regions of the MOS transistor provided as the memory cell, and the resist film is implanted so that the mask ion implants the data write impurity. Since it is constituted by using a metal wiring together, the data writing step can be set in a subsequent period of the manufacturing process. For this reason, the delivery date of production can be shortened. At the same time, the dimensional precision of the mask can be relaxed while ensuring the necessary alignment precision and the design of the mask pattern can be stably simplified in the manufacturing process temperature. In addition, since the diffusion layer is applied by the metal line, the data write impurity does not enter the diffusion layer, and the increase in the layer resistance and cushion capacitance of the diffusion charge can be suppressed to prevent the reduction of the data read ratio.

Claims (7)

A semiconductor memory; A plurality of diffusion layers 2 arranged in parallel with each other in the main surface of the semiconductor substrate 1; A plurality of gate electrodes (4) arranged in parallel with each other on the semiconductor substrate through a gate insulating film (3) in a direction perpendicular to the diffusion layers; Formed in intersection regions including intersections between the diffusion layers and gate electrodes at the major surface of the semiconductor substrate to constitute memory cells, the intersection regions including a channel through which channel current flows, and data being A plurality of MOS transistors (2a, 2b, 9) written into the memory cells by selectively ion implanting impurities in the channels; An interlayer insulating film (5) formed on said semiconductor substrate including said gate electrodes; And a plurality of metal wirings (6) formed on said interlayer insulating film corresponding to said diffusion layers to function as a mask for ion implantation of impurities. The semiconductor memory of claim 1, wherein the metal wires have a width larger than that of the diffusion layers, and are formed to apply the diffusion layers in a direction perpendicular to a direction in which a channel current flows through the channels. 2. The diffusion layer of claim 1, wherein the diffusion layers alternately constitute source regions 2a and drain regions 2b of the MOS transistors, and the channels are the gate between the source and drain regions in the cross regions. A semiconductor memory formed under the electrodes, wherein the metal lines are formed on the diffusion layers corresponding to at least one of the source and drain regions. The semiconductor memory of claim 1, wherein the MOS transistors constitute a flat cell NOR mask ROM. A semiconductor memory; A plurality of diffusion layers 2 arranged in parallel with each other in the main surface of the semiconductor substrate 1; A plurality of gate electrodes (4) arranged in parallel with each other on the semiconductor substrate through a gate insulating film (3) in a direction perpendicular to the diffusion layers; The alternate regions of the gate electrodes and the diffusion layers are alternately configured as source regions 2a and drain regions 2b, and are directly under the gate electrodes between the source and drain regions in the semiconductor substrate. MOS transistors each configured as a channel, each constituting a memory cell to which data is written by selectively ion implanting impurities into the channel; An interlayer insulating film (5) formed on said semiconductor substrate including said gate electrodes; And a plurality of metal wires (6) formed on said interlayer insulating film corresponding to at least one of said source and drain regions so as to act as a mask for ion implantation of impurities. A method of manufacturing a semiconductor device; Forming a plurality of diffusion layers (2) in parallel with each other in a major surface of the semiconductor substrate (1); Forming a plurality of gate electrodes (4) in parallel with each other on the semiconductor substrate through a gate insulating film (3) in a direction perpendicular to the diffusion layers; Forming memory cells in intersection regions including intersections between the diffusion layers and the gate electrodes, the intersection regions forming a plurality of MOS transistors including channels through which channel current flows; Forming an interlayer insulating film (5) on said semiconductor substrate, said gate electrodes; Forming metal wirings (6) on the interlayer insulating film corresponding to the diffusion layers; Forming a resist film (7) having an opening (8) in a region corresponding to the selected memory cell, on the interlayer insulating film including the metal wirings; And implanting impurities into the channel using the resist and the metal wiring exposed through the opening of the resist film to write data in a MOS transistor. The method of claim 6, wherein the diffusion layers alternately form source regions 2a and drain regions 2b of the MOS transistors, and the forming of the metal line comprises at least one of the source and drain regions. Forming the metal wires on the interlayer insulating film so as to apply a film. ※ Note: The disclosure is based on the initial application.