JPH1041411A - Semiconductor memory device and method of manufacturing the same - Google Patents

Abstract

(57) Abstract: MOS mask R having fine memory cell
In OM, data writing becomes difficult as memory cells are miniaturized. SOLUTION: In a flat cell NOR type mask ROM, a metal wiring 6 is provided along a drain of a source / drain region 2 constituting a MOS transistor as a memory cell so as to cover the drain. Since the metal wiring 6 is used as a mask together with the resist film 7 to form the impurity implantation layer 9 for data writing, the dimensional accuracy of the mask can be relaxed, the mask pattern can be easily designed, and the impurity for data writing is drain region. To suppress the increase in the layer resistance and the junction capacitance of the diffusion layer 2,
A decrease in the reading speed is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly to a mask ROM (Read Only Memory) which is a read-only memory device and a method of manufacturing the same.

[0002]

2. Description of the Related Art Mask RO which is a read only storage device
In M, since the data of the customer is written during the manufacturing, the delivery date of the product can be shortened as the data writing process is set at a later stage of the manufacturing process. The data writing process may be performed mainly after the formation of the gate electrode or after the formation of the interlayer insulating film, and the process after the formation of the interlayer insulating film for writing data in a later stage of the manufacturing process is more described above. It is advantageous in terms of delivery time. 3A and 3B are a plan view of a conventional flat cell NOR type mask ROM and a cross-sectional view taken along line CC in a data writing process. In the mask ROM, a plurality of N-type diffusion layers 12 in a linear pattern are formed in parallel on the main surface of a P-type silicon substrate 11, and a plurality of gate electrodes are formed thereon via a gate insulating film 13. 14 are arranged in parallel to each other perpendicular to the N-type diffusion layer 12. Here, the memory cell has a source and a drain at the intersection of the N-type diffusion layer 12 and the gate electrode 14, and between the N-type diffusion layer 12 and the gate electrode 1.
4 is configured as a MOS transistor having a channel immediately below. Then, by selectively introducing a P-type impurity into the channel, the transistor of the introduced memory cell is turned off, and data is written. Reference numeral 16 denotes a metal wiring formed in a later step.

To write such data, as shown in FIG. 3B, after an interlayer insulating film 15 covering the gate electrode 14 is formed on the entire surface, a resist film 17 is formed on the entire surface.
And a resist film 1 for writing data.
An opening 18 is formed in 7. In this case, the opening 18 for writing data includes 1. .mu.m including a mask alignment margin of 0.1 .mu.m when the interval between the N-type diffusion layers 12 is 1.0 .mu.m.
It is set to 2 μm. Then, this resist film 17
Is used as a mask to ion-implant a P-type impurity, whereby a P-type impurity is ion-implanted into the channel of the memory cell exposed in the opening to form an implantation layer 19, and the transistor is turned off.

In such a mask ROM, as described above, the resist film 17 is used as a mask for performing ion implantation on a selected memory cell.
In order to ensure the mask function, it is necessary to form the resist film 17 with a large thickness, and the side wall of the opening 18 becomes slow as the resist film thickness increases.
8 becomes difficult to form with high dimensional accuracy. Also,
On the other hand, memory cells have been reduced in size in accordance with recent demands for higher density of storage devices, and it is desired that the pattern size of a mask be further reduced. For this reason, the margin for mask alignment of the resist film described above also becomes smaller, and an even higher dimensional accuracy is required, and it becomes difficult to perform high-precision writing with a mask using the resist film.

To solve such a problem, Japanese Patent Laid-Open No. 4-634 has been proposed.
No. 72 discloses a technique in which a metal wiring is formed along an upper part of an element isolation oxide film of a memory cell in a NAND type mask ROM, and the metal wiring is used as a part of a mask for ion implantation for writing data. Proposed.
In this technique, since the side wall of the metal wiring is formed steeply, the mask dimensions can be controlled finely and with high accuracy, which is advantageous in realizing a high-density storage device. Also, Japanese Patent Application Laid-Open No. 1-184864 proposes a technique in which data writing can be performed after the formation of a final protective film and a delivery time can be reduced by using a metal film as a mask.

[0006]

However, in the technique disclosed in the former publication, it is necessary to form a metal wiring used as a mask on an element isolation oxide film of a memory cell.
As the width and pitch of the element isolation oxide film become finer due to the miniaturization of the memory cell, it is necessary to make the metal wiring narrower and finer in pitch. Is required to align a mask of a fine pattern with high precision, and it is extremely difficult to actually form such a metal wiring. Further, the technique disclosed in the latter publication is effective for a memory cell having a single or loose dimensional accuracy, but the flat cell type mask R which requires a high density as shown in FIG.
It is difficult to apply to OM as it is. Furthermore, N
In the case of an OR-type mask ROM, the N-type diffusion layer serving as the drain of the memory cell transistor overlaps with the P-type diffusion layer for writing data due to misalignment of the mask. Also, there is a problem that the reading speed is lowered due to an increase in the junction capacitance.

An object of the present invention is to enable high-speed operation in a MOS mask ROM having fine memory cells,
Another object of the present invention is to provide a semiconductor memory device capable of writing data with high accuracy and a method of manufacturing the same.

[0008]

The present invention is characterized in that a metal wiring is provided along a diffusion layer constituting a MOS transistor as a memory cell so as to cover the diffusion layer. It is preferable that the metal wiring is formed to have a larger width dimension than the diffusion layer and to cover the diffusion layer at least in the channel length direction. Further, the diffusion layers are alternately arranged as a source region and a drain region, and a metal wiring is formed on at least one of the source region and the drain region.

Further, according to the manufacturing method of the present invention, when data is written by performing ion implantation on a selected memory cell among the memory cells constituted by MOS transistors, the memory cell is formed on the diffusion layer as a mask for ion implantation. And a resist formed on the metal wiring and having an opening in a region corresponding to the memory cell.
Here, a part of the metal wiring is exposed in the opening of the resist, and an ion implantation mask is formed by the side wall of the opening of the resist and the exposed side wall of the metal wiring. The metal wiring is formed directly above at least one of the source and the drain of the MOS transistor so as to cover the source and drain regions.

[0010]

Next, embodiments of the present invention will be described with reference to the drawings. 1A and 1B are a plan view of an embodiment in which the present invention is applied to a flat cell NOR type mask ROM and a cross-sectional view along a line AA in a data writing process. In the figure, on a main surface of a P-type silicon substrate 1, a plurality of N-type diffusion layers 2 in a linear pattern are formed in parallel and arranged at equal intervals. A gate insulating film 3 is formed thereon, and a plurality of gate electrodes 4 are formed on the gate insulating film 3 at right angles to the N-type diffusion layer 2 in parallel and at equal intervals. Here, the memory cell is configured as a MOS transistor having a source and a drain at the intersection of the N-type diffusion layer 2 and the gate electrode 4 and a channel between the N-type diffusion layer 2 and a region immediately below the gate electrode. Then, an interlayer insulating film 5 is formed so as to cover the gate electrode, and a metal wiring 6 is formed on the interlayer insulating film 5.
Are formed.

The metal wiring 6 is formed as a column line or a ground line of a memory cell or another wiring, and is arranged along the upper side of the N-type diffusion layer 2 at an interval twice as large as that of the N-type diffusion layer 2. Is formed. That is, since the N-type diffusion layers 2 are alternately arranged as a drain region and a source region on every other N-type diffusion layer 2 in the arrayed N-type diffusion layers 2, the drain region Is formed only on The width of the metal wiring 6 is somewhat larger than the width of the N-type diffusion layer 2, so that the metal wiring 6 is formed so as to cover the drain region even when a normal misalignment occurs. ing. Then, after performing data writing described later, a mask ROM is formed by forming a protective film and an upper layer wiring (not shown).

When data is written to the mask ROM, a resist film 7 is applied on the metal wiring 6 and selected for data writing as shown in FIG. 1B. An opening 8 is formed in the resist film 7 in a region corresponding to the memory cell. In this case, the opening size is N
When the interval between the mold diffusion layers 2 is 1.0 μm, the thickness is 1.6 μm including the alignment margin of the mask of 0.1 μm. As a result, the metal wiring 6 is formed in the opening 8 of the resist film.
The metal wiring 6 and the resist film opening 8 are partially exposed.
A region surrounded by the inner side wall of the gate is formed as an opening for writing data.

Then, a P-type impurity is ion-implanted using the resist film 7 and the metal wiring 6, and a P-type impurity is ion-implanted into a channel of a selected memory cell to form an implantation layer 9. And the MOS of this memory cell
The transistor is turned off, and data is written. At this time, since one side of the region in the opening 8 is regulated by the metal wiring 6, the side wall of the mask is steep at least on the side of the drain region 2 and is smaller than the side wall of the resist film on the source side. The dimensional accuracy is improved. Therefore, even when the thickness of the resist film 7 is large and the dimensional accuracy of the opening 8 is reduced, a mask having high dimensional accuracy at least on the drain side can be obtained. This also gives
As described above, the size of the mask opening 8 of the resist film is set to 1.
It can be enlarged to 6 μm, which facilitates the design and manufacture, and enables stable manufacture of products.

Further, since the metal wiring 6 is formed so as to cover the drain region 2, a part of the P-type impurity implantation layer 9 is ion-implanted into the source region even if some misalignment occurs. However, the ions are not implanted into the drain region. Therefore, the P-type impurity layer ion-implanted into the channel does not penetrate at least into the drain region, so that an increase in the layer resistance and junction capacitance of the drain region can be suppressed, and a decrease in operation speed can be prevented. Further, even when the width dimension and the pitch dimension of the N-type diffusion layer 2 are reduced in accordance with the miniaturization of the memory cell, the metal wiring 6 is formed only on every other drain region. Since the width is formed to be larger than the drain region as described above, the formation of the metal wiring 6 is easy, and therefore, the formation with high precision is also possible.

FIGS. 2A and 2B are a plan view of another embodiment of the present invention and a sectional view taken along the line BB of FIG. 1 in a data writing state. The same reference numerals are given. This embodiment is an example in which the metal wiring 6 can be minutely formed, and the metal wiring 6 is formed on each of the N-type diffusion layers 2 as the drain region and the source region.
Is formed. Each of the metal wirings 6 is formed in a size to completely cover the drain region and the source region, respectively. When an opening 8 is formed in the resist film 7, each metal wiring 6 on the drain region and the source region is formed in the opening 8.
Is configured to be exposed.

Therefore, in this apparatus, when the ion implantation is performed through the opening 8 of the resist film, the drain region and the source region are masked by the metal wiring 6, so that the ion implantation can be performed with extremely high precision. Therefore, the dimensional accuracy of the opening 8 of the resist film 7 can be relaxed as compared with the above embodiment, and the design and manufacturing can be performed more easily. Further, since the P-type impurity implanted layer 9 ion-implanted into the channel does not penetrate into either the drain region or the source region, it is possible to suppress an increase in the layer resistance and the junction capacitance of the drain region and the source region. As a result, the high-speed operation of the device can be further enhanced.

Although the above embodiment shows an example in which the metal wiring is formed on the drain region and on both the drain region and the source region, the metal wiring may be formed only on the source region. .

[0018]

As described above, according to the present invention, a metal wiring is formed on at least one of diffusion layers constituting a drain region and a source region of a MOS transistor as a memory cell, and the metal wiring is formed together with a resist. Since the mask is used to perform impurity ion implantation for data writing, it is possible to set the data writing process at a later stage of the manufacturing process, shorten the product delivery time, and achieve the required alignment accuracy. The dimensional accuracy of the mask can be relaxed while securing the mask pattern, and the design of the mask pattern can be facilitated to realize more stable product manufacturing. Furthermore, since the diffusion layer is covered with the metal wiring, the impurity for data writing does not enter the diffusion layer, the increase in the layer resistance and the junction capacitance of the diffusion layer is suppressed, and the reading speed is prevented from lowering.

[Brief description of the drawings]

FIG. 1 is a plan view of a first embodiment of the present invention and a sectional view taken along line AA of FIG. 1 having an exposure mask.

FIG. 2 is a plan view of a second embodiment of the present invention and a cross-sectional view taken along a line BB of FIG.

FIG. 3 is a plan view of a conventional semiconductor memory device and a cross-sectional view taken along line CC of the semiconductor memory device having an exposure mask.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 P-type silicon substrate 2 N-type diffusion layer (drain region, source region) 3 Gate insulating film 4 Gate electrode 5 Interlayer insulating film 6 Metal wiring 7 Resist film 8 Opening 9 P-type impurity injection layer

Claims (7)

[Claims] A MOS transistor formed in a semiconductor substrate in which a plurality of diffusion layers are arranged in parallel and a plurality of gate electrodes are arranged in parallel in a direction perpendicular to the plurality of diffusion layers, and formed in an intersection region between the diffusion layers and the gate electrodes. The transistor is a memory cell,
A semiconductor memory device in which data is written to a selected memory cell, wherein a metal wiring is provided on the diffusion layer so as to cover the diffusion layer. 2. The semiconductor memory device according to claim 1, wherein the metal wiring is formed to have a larger width than the diffusion layer, and is formed so as to cover the diffusion layer at least in a channel length direction. 3. The semiconductor memory device according to claim 2, wherein the diffusion layers are alternately arranged as a source region and a drain region, and the metal wiring is formed on at least one of the source region and the drain region. 4. The semiconductor memory device according to claim 1, wherein said semiconductor memory device is configured as a flat cell NOR type mask ROM. 5. A MOS transistor, wherein a plurality of diffusion layers are arranged in parallel on a semiconductor substrate, and a plurality of gate electrodes are arranged in parallel in a direction perpendicular to the plurality of diffusion layers, and a MOS formed in an intersection region between these diffusion layers and the gate electrodes. The transistor is a memory cell,
In a method for manufacturing a semiconductor memory device in which data is written by performing ion implantation on a selected memory cell, a metal wiring formed to cover the diffusion layer as a mask for the ion implantation, and a metal wiring formed on the metal wiring A method of manufacturing a semiconductor memory device, comprising using a resist having an opening in a region corresponding to the selected memory cell. 6. A method for manufacturing a semiconductor memory device according to claim 4, wherein a part of the metal wiring is exposed in the opening of the resist, and a mask for ion implantation is formed by the side wall of the opening of the resist and the exposed side wall of the metal wiring. . 7. The method according to claim 5, wherein the metal wiring is formed immediately above at least one of the source and the drain of the MOS transistor so as to cover the source and drain regions.