KR100286732B1 - Semiconductor memory and method of manufacturing the same - Google Patents

Abstract

The semiconductor memory includes a plurality of diffusion layers, a plurality of gate electrodes, a plurality of MOS transistors, an interlayer insulating film, and a plurality of metal wirings. The diffusion layers are arranged in parallel with each other on the main surface of the semiconductor substrate. The gate electrodes are arranged in parallel with each other on the semiconductor substrate through the gate insulating film in the direction perpendicular to the diffusion layers. The MOS transistors are formed in the intersection areas including the intersection points between the diffusion layers and the gate electrodes on the main surface of the semiconductor substrate to constitute memory cells. The crossing regions include channels through which the channel current flows. Data is written into the memory cells by selectively ion implanting impurities into the channels. An interlayer insulating film is formed on the semiconductor substrate including the gate electrodes. The metal wirings are formed on the interlayer insulating film corresponding to the diffusion layers so as to function as a mask for ion implanting impurities. A method of manufacturing such a semiconductor memory has also been disclosed.

Description

Technical Field [0001] The present invention relates to a semiconductor memory,

The present invention relates to a semiconductor memory and a manufacturing method thereof, and more particularly to a mask ROM (Mask Read Only Memory) and a manufacturing method thereof.

In the mask ROM, customer data is written during the manufacturing process. If the data writing step is set within the subsequent cycle of the mask ROM manufacturing process, the period from the designation time of the program data by the user called TAT (Turn Around Time) to the product delivery time can be shortened. The data writing step is performed after the formation of the gate electrode or after the formation of the interlayer insulating film. The step performed after the formation of the interlayer insulating film is advantageous in terms of the delivery time because the data is written in the latest cycle of the manufacturing process.

3A and 3B show a conventional flat-cell NOR mask ROM. In this mask ROM, a plurality of n-type diffusion layers 12 each having a linear pattern are formed so as to be arranged in parallel with each other with respect to the main surface of the p-type silicon substrate 11. [ The plurality of gate electrodes 14 are arranged in parallel with each other on the final structure through the gate insulating film 13 and are arranged to be perpendicular to the n-type diffusion layers 12. The memory cells are used as source and drain at the intersections between the n-type diffusion layers 12 and the gate electrodes 14 and the regions immediately below the gate electrodes 14 between the n- Lt; RTI ID = 0.0 > MOS transistors < / RTI > By selectively implanting the p-type impurity in the channel region, the transistor of the memory cell into which the p-type impurity is implanted is turned off to write data. Reference numeral 16 denotes a metal wiring to be formed in a subsequent step.

The interlayer insulating film 15 is formed on the entire surface of the silicon substrate 11 in order to apply the gate electrodes 14 and then the resist film 17 is patterned to form the interlayer insulating film 15 as shown in FIG. , And is used on the interlayer insulating film 15. The opening portion 18 is formed in the resist film 17 while writing the data. In this case, when the interval between the n-type diffusion layers 12 is 1.0 탆, the cross section of the data write-in opening 18 is set to be a rectangle having an opening diameter L of 1.2 탆 including a mask alignment margin of 0.1 탆 do. the p-type impurity is implanted into the channel region by using the resist film 17 as a mask to form the p-type implanted layer 19, and the transistor of the memory cell exposed through the opening 18 is turned off .

In this mask ROM, a resist film 17 is used as a mask for ion-implanting p-type impurity into a selected memory cell. Since the ion implantation is performed after the gate insulating film 13, the gate electrode 14, and the interlayer insulating film 15 are formed, the resist film 17 must be formed thick to ensure the mask function. As the thickness of the resist film 17 increases, the side walls of the opening 18 can not be formed in a sharp manner. Therefore, it is difficult to pattern the ion implantation region by forming the opening portion 18 with high dimensional precision.

On the other hand, as the memory cell is scaled down to accommodate the recent demands for high density of memory, the pattern dimension of the mask needs to be much smaller. As a result, the mask alignment margin of the resist mask is also reduced, and a higher dimension accuracy is required for the aperture 18. It is difficult to perform data writing with a high accuracy by using the mask of the resist film 17.

In order to solve such a problem, Japanese Patent Laid-Open Publication No. 4-63472 (No. 1) discloses a method of forming a metal interconnection along an upper portion of an element insulating oxide film of a memory cell in a NAND mask ROM, A mask is used as a part of the mask. This technique is advantageous for realizing a high-density memory because the side wall of the metal wiring is formed in a sharp manner and the mask dimension can be precisely controlled with high precision. Further, Japanese Patent Laid-Open No. 1-184864 (No. 2) proposes to shorten the TAT by suggesting a technique that can be used as a mask for the metal film to perform data writing after the final protective film is formed.

In the technique described in the first patent, the metal wiring to be used as a mask must be formed on the element insulating oxide film of the memory cell, so that the width and the pitch of the metal wiring can be changed in accordance with the size reduction in the memory cell. The width and pitch must be reduced corresponding to the decrease. However, in order to form a small-width metal wiring at a small pitch, a mask having a fine pattern must be aligned with high precision. In practice, such metallization is very difficult to form.

Although the technique described in the second patent is effective for a single memory cell or memory cell having a graduated dimensional accuracy, as shown in FIGS. 3A and 3B, the flat cell mask ROM required to realize high density It is not directly applicable. In the NOR type mask ROM, the n-type diffusion layer provided as the drain of the memory cell transistor overlaps with the p-type diffusion layer for data writing due to the alignment error of the mask. As a result, the resistance and junction capacitance of the n-type diffusion layer provided as drain increase inappropriately in order to reduce the read rate.

It is an object of the present invention to provide a semiconductor memory capable of performing high-speed and high-precision data writing in a MOS mask ROM having fine memory cells and a method of manufacturing the same.

According to the present invention, there is provided a semiconductor device comprising: a plurality of diffusion layers arranged in parallel with each other in a main surface of a semiconductor substrate; a plurality of diffusion layers arranged in parallel on the semiconductor substrate through a gate insulating film in a direction perpendicular to the diffusion layers; Gate electrodes and intersection regions between diffusion layers and gate electrodes in the main surface of the semiconductor substrate to form memory cells comprising the channels through which the channel current flows, A plurality of MOS transistors to be written in the memory cell by selectively implanting impurities into the channel, an interlayer insulating film formed on the semiconductor substrate including the gate electrodes, and an interlayer insulating film formed on the diffusion layers Formed on the interlayer insulating film corresponding to the plurality of gold And inner wires.

1A is a plan view showing a flat NOR mask ROM according to a first embodiment of the present invention;

1B is a cross-sectional view taken along line A - A in FIG. 1A in the data write step. FIG.

2A is a plan view showing a flat NOR mask ROM according to a second embodiment of the present invention;

FIG. 2B is a cross-sectional view taken along line B-B in FIG. 2A in the data write step. FIG.

3A is a plan view showing a conventional flat NOR mask ROM.

FIG. 3B is a cross-sectional view taken along line C-C in FIG. 3A in the data write step. FIG.

Description of the Related Art

1: p-type silicon substrate

2: n-type diffusion layers

3: Gate insulating film

4: Gate electrodes

5: Interlayer insulating film

6: metal wiring

7: Resist film

8: opening

The present invention will be described in detail below with reference to the accompanying drawings.

1A and 1B show a flat-cell NOR mask ROM according to a first embodiment of the present invention. 1A and 1B, a plurality of n-type diffusion layers 2 each having a linear pattern are arranged in parallel with each other at equal intervals in the main surface of a p-type silicon substrate 1 in which many memory cells are formed . The plurality of gate electrodes 4 are formed on the p-type silicon substrate 1 including the n-type diffusion layers 2 at regular intervals through the gate insulating film 3 so as to be perpendicular to the n-type diffusion layers 2 And are arranged to be arranged in parallel with each other. The memory cells are formed such that the intersecting regions of the n-type diffusion layers 2 having the gate electrodes 4 are alternately used as the source regions 2a and the drain regions 2b and the source and drain regions 2a and 2b, The regions directly below the gate electrodes 4 are composed of MOS transistors used as a channel region. The interlayer insulating film 5 is formed on the p-type silicon substrate 1 to apply the gate electrodes 4 and the metal wirings 6 are formed on the interlayer insulating film 5.

The metal wirings 6 constitute column lines or ground lines or other lines of memory cells and are arranged on the upper portion of the n-type diffusion layers 2 at an arrangement interval twice as large as that of the n- Are formed in parallel with each other. That is, since the metal wirings 6 correspond to the n-type diffusion layers 2 alternately, for example, the source and drain regions 2a and 2b correspond to the n-type diffusion layers 2b corresponding to the drain regions 2b, Type diffusion layers 2 formed so as to be arranged only on the n-type diffusion layer 2, as shown in Fig. The width of the metal wiring 6 is set to be slightly larger than the width of the n-type diffusion layer 2. Even if a normal alignment error occurs, the metal wiring 6 applies the drain region 2b. After data writing (to be described later) is performed, a passivation film and an upper line (none of which are shown) are formed to complete the mask ROM.

In writing data in this mask ROM, the resist film 7 is applied on the interlayer insulating film 5 including the metal wirings 6, as shown in Fig. 1B. An opening 8 having a rectangular cross section is formed in the resist film 7 in the region corresponding to the memory cell selected for data writing. In this case, when the interval between the n-type diffusion layers 2 is 1.0 占 퐉, the dimension L of the opening portion is set to 1.6 占 퐉 including the mask alignment margin of 0.1 占 퐉. As a result, a part of the metal wiring 6 is exposed through the opening 8 of the resist film. The region surrounded by the metal wiring 6 and the inner side wall of the opening 8 of the resist film is patterned with respect to the actual ion implantation opening 8a.

The p-type impurity is ion-implanted through the opening 8a using the resist film 7 and the metal wiring 6 as a mask so as to form the p-type implantation layer 9 in the channel of the selected memory cell. With this process, the MOS transistor of the selected memory cell is turned off to write data. Since the side wall of the resist film 7 on the side of the drain region 2b in the opening 8a is adjusted by the metal wiring 6 so as to have a sharp vertical surface, ) Side is higher than that of the side wall. After the resist film 7 is removed, a passivation film and an upper line (none of which are shown) are formed to complete the mask ROM.

Even when the resist film 7 has a thickness that reduces the dimensional accuracy of the opening 8, the accuracy of the higher mask dimensions can be obtained at least on the side of the drain region 2b. The dimension of the opening 8 of the resist film 7 can be increased to 1.6 占 퐉 as described above. As a result, the design and manufacture of the mask ROM are simplified to enable stable production and supply.

The metal wiring 6 is formed to have a dimension capable of applying the drain region 2b. Even when a slight alignment error occurs, the p-type impurity can not be ion-implanted into the drain region 2b even if it can be implanted into the source region 2a. Therefore, the p-type impurity layer formed by the channel by ion implantation does not extend to at least the drain region 2b. Increasing the layer resistance and junction capacitance of the drain region 2b can be suppressed to prevent a reduction in the operating speed.

The metal wirings 6 are formed on all the other n-type diffusion layers 2 corresponding to the drain regions 2b even when the width and the pitch of the n-type diffusion layer 2 are reduced in accordance with the decrease in size in the memory cell. As shown in FIG. Further, since the width of the metal wiring 6 is larger than the width of the drain region 2b, the metal wiring 6 can be easily formed. As a result, the mask ROM can be formed with high precision.

2A and 2B show a second embodiment of the present invention. The same reference numerals as in Figs. 1A and 1B denote the same parts, and a description thereof will be omitted. The second embodiment exemplifies the case of the metal wiring 6 which can be patterned on a micro-scale basis. The metal wirings 6 are formed on the n-type diffusion layers 2 on which the source and drain regions 2a and 2b are formed. The metal wiring 6 is formed so as to be capable of completely applying the n-type diffusion layer 2. Two metal wirings 6 are exposed through the opening 8 on the sides of the source and drain regions 2a and 2b when the data write opening 8 is formed in the resist film 7. [ The region constituted by the two metal wirings 6 and the resist film 7 is patterned with respect to the actual ion implantation opening 8a.

In the above arrangement, when the ions are implanted through the opening 8 of the resist film 7, the ion-implanted region is formed such that the two source and drain regions 2a and 2b are exposed to the mask So that it can be patterned with very high precision. Therefore, the dimensional accuracy of the opening 8 of the resist film 7 can be relaxed as compared with the first embodiment. The design and manufacture described above can be further simplified. Since the p-type impurity implantation layer 9 formed by ion implantation does not extend to one of the source and drain regions 2a and 2b, an increase in the layer resistance and the change capacitance of the source and drain regions 2a and 2b May be suppressed to increase the operating speed of the device.

The first and second embodiments are exemplified in the case where the metal wirings are formed on the n-type diffusion layers 2 corresponding to the drain regions 2b and the two source and drain regions 2a and 2b. The metal wirings can be formed only on top of the n-type diffusion layers corresponding to the source regions 2a.

As described above, according to the present invention, the metal interconnection is formed on at least one of the diffusion layers constituting the drain and source regions of the MOS transistor provided as a memory cell, and the mask is provided with a resist film The data writing step can be set in the subsequent period of the manufacturing process. For this reason, the delivery time of production can be shortened. At the same time, the dimensional accuracy of the mask can be mitigated while ensuring the necessary alignment precision, and the design of the mask pattern can stably simplify the manufacturing process. Further, since the diffusion layer is applied as a metal line, the data write impurity does not enter the diffusion layer, and the increase in the layer resistance and junction capacitance of the diffusion layer can be suppressed to prevent the reduction of the data readout ratio.

Claims (7)

In a semiconductor memory, A plurality of diffusion layers (2) arranged in parallel with each other in a main surface of a semiconductor substrate (1); A plurality of gate electrodes (4) arranged in parallel with each other on the semiconductor substrate through a gate insulating film (3) in a direction perpendicular to the diffusion layers; Wherein the memory cells are formed in intersecting regions that include intersections between the diffusion layers and the gate electrodes on the main surface of the semiconductor substrate, wherein the intersecting regions comprise channels through which channel currents flow, A plurality of MOS transistors (2a, 2b, 9) into which data is written into the memory cells by selectively implanting impurities into the memory cells; An interlayer insulating film (5) formed on the semiconductor substrate including the gate electrodes; And A plurality of metal wirings (6) formed on the interlayer insulating film corresponding to the diffusion layers so as to function as a mask for ion implantation of impurities, And a semiconductor memory. The semiconductor memory of claim 1, wherein the metal interconnects are formed to have a width greater than the width of the diffusion layers and to apply the diffusion layers in a direction perpendicular to the direction in which the channel current flows through the channels. 2. The semiconductor device according to claim 1, wherein the diffusion layers alternately constitute source regions (2a) and drain regions (2b) of the MOS transistors, The channels being formed directly under the gate electrodes between the source and drain regions in the crossing regions, Wherein the metal wirings are formed on the diffusion layers corresponding to at least one of the source and drain regions And a semiconductor memory. 2. The semiconductor memory according to claim 1, wherein the MOS transistors constitute a flat cell NOR mask ROM. In a semiconductor memory, A plurality of diffusion layers (2) arranged in parallel with each other in a main surface of a semiconductor substrate (1); A plurality of gate electrodes (4) arranged in parallel with each other on the semiconductor substrate through a gate insulating film (3) in a direction perpendicular to the diffusion layers; Wherein intersecting regions of the gate electrodes and the diffusion layers are alternately configured as source regions (2a) and drain regions (2b), and a region beneath the gate electrodes between the source and drain regions in the semiconductor substrate MOS transistors constituting each channel and each constituting a memory cell into which data is written by selectively implanting impurities into the channel; An interlayer insulating film (5) formed on the semiconductor substrate including the gate electrodes; And A plurality of metal wirings (6) formed on the interlayer insulating film corresponding to at least one of the source and drain regions so as to function as a mask for ion implantation of impurities, And a semiconductor memory. A method of manufacturing a semiconductor device, Forming a plurality of diffusion layers (2) in parallel with each other in a main surface of a semiconductor substrate (1); Forming a plurality of gate electrodes (4) in parallel with each other on the semiconductor substrate through a gate insulating film (3) in a direction perpendicular to the diffusion layers; Forming memory cells in intersecting regions including intersections between the diffusion layers and the gate electrodes, wherein the intersecting regions comprise a plurality of MOS transistors including channels through which a channel current flows; Forming an interlayer insulating film (5) on the semiconductor substrate including the gate electrodes; And Forming metal wirings (6) on the interlayer insulating film corresponding to the diffusion layers; Forming a resist film (7) having an opening (8) in an area corresponding to a selected memory cell on the interlayer insulating film including the metal wirings; And Implanting impurities into the channel using the metal wiring exposed through the opening of the resist film to write data in the MOS transistor and the resist as a mask Wherein the step of forming the semiconductor device comprises the steps of: 7. The semiconductor device according to claim 6, wherein the diffusion layers alternately constitute source regions (2a) and drain regions (2b) of the MOS transistors, Wherein the step of forming the metal wiring includes forming the metal wirings on the interlayer insulating film so as to apply at least one of the source and drain regions.

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