[go: up one dir, main page]

KR970052023A - 에스 오 아이 소자 및 그의 제조방법 - Google Patents

에스 오 아이 소자 및 그의 제조방법 Download PDF

Info

Publication number
KR970052023A
KR970052023A KR1019950069461A KR19950069461A KR970052023A KR 970052023 A KR970052023 A KR 970052023A KR 1019950069461 A KR1019950069461 A KR 1019950069461A KR 19950069461 A KR19950069461 A KR 19950069461A KR 970052023 A KR970052023 A KR 970052023A
Authority
KR
South Korea
Prior art keywords
layer
forming
soi
wafer
soi device
Prior art date
Application number
KR1019950069461A
Other languages
English (en)
Inventor
김재갑
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950069461A priority Critical patent/KR970052023A/ko
Priority to TW085115674A priority patent/TW312854B/zh
Priority to DE19654280A priority patent/DE19654280B4/de
Priority to JP8357091A priority patent/JPH1074921A/ja
Priority to GB9626979A priority patent/GB2309825B/en
Priority to CN96123937A priority patent/CN1075246C/zh
Publication of KR970052023A publication Critical patent/KR970052023A/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6708—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing the kink effect or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
    • H10D30/6711—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing the kink effect or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect by using electrodes contacting the supplementary regions or layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)

Abstract

본 발명은 에스 오 아이(이하 SOI : silicon on insulator)소자 및 그의 제조방법에 관한 것으로, 특히 SOI의 기판의 플로팅(floating) 현상을 방지할 수 있는 SOI 소자 및 그의 제조방법에 관한 것으로, 본 발명에 의하면 SOI 기판의 고질적인 문제점인 기판 플로팅 현상을 방지하기 위하여 소자가 형성된 실리콘 웨이퍼 내부에 소자의 채널영역과 연결되도록 전도층을 형성하여 기판 전극 영역에 연결시키므로써, 기판의 항복 전압 및 스위칭 특성을 향상시키어 소자의 특성을 개선한다.

Description

에스 오 아이 소자 및 그의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도 (가) 내지 (다)는 본 발명에 에스 오 아이 기판 제조방법을 설명하기 위한 각 제조공정에 있어서의 요부 단면도.

Claims (4)

  1. 모스 트랜지스터를 구성하는 전극 및 소자 분리막이 형성된 SOI 소자층과, 상기 SOI 소자층 하부에 일정부분의 SOI 소자층이 노출되도록 형성된 제1절연막과, 상기 제1절연막의 하부에 위치하여 SOI 소자층에 접속되도록 형성된 전도층과, 상기 전도층 하부에 형성된 절연막과, 상기 SOI 소자를 지지하는 핸들링 웨이퍼를 포함하는 것을 특징으로 하는 SOI 소자.
  2. 실리콘 웨이퍼 상의 적소에 소자 분리막을 형성하는 단계; 상기 구조물 상부에 제1절연막을 형성하는 단계; 상기 제1절연막을 채널 예정 영역 및 기판 전극 영역에 노출되도록 식각하는 단계; 상기 구조물 상부에 전도층을 형성하는 단계; 상기 전도층 상부에 제2절연막을 형성하는 단계; 상기 제2절연막이 형성된 실리콘 웨이퍼와 부착될 핸들링 웨이퍼를 준비하는 단계; 상기 핸들링 웨이퍼 상부에 제3절연막을 형성하는 단계; 상기 핸들링 웨이퍼 및 실리콘 웨이퍼를 접착시키는 단계; 및 상기 실리콘 웨이퍼의 표면을 에치백하여 SOI층을 형성하는 단계를 포함하는 것을 특징으로 하는 SOI 소자의 제조방법.
  3. 제2항에 있어서, 상기 전도층은 기판 불순물과 동일한 타입의 불순물이 도핑된 실리콘층인 것을 특징으로 하는 SOI 소자의 제조방법.
  4. 제2항에 있어서, 상기 SOI층을 형성하기 위한 에치백 공정시, 소자 분리막을 식각 정지층으로 하여 에치백하는 것을 특징으로하는 하는 SOI 소자의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950069461A 1995-12-30 1995-12-30 에스 오 아이 소자 및 그의 제조방법 KR970052023A (ko)

Priority Applications (6)

Application Number Priority Date Filing Date Title
KR1019950069461A KR970052023A (ko) 1995-12-30 1995-12-30 에스 오 아이 소자 및 그의 제조방법
TW085115674A TW312854B (ko) 1995-12-30 1996-12-19
DE19654280A DE19654280B4 (de) 1995-12-30 1996-12-24 Verfahren zur Herstellung einer Halbleitereinrichtung auf einem SOI-Wafer
JP8357091A JPH1074921A (ja) 1995-12-30 1996-12-26 半導体デバイスおよびその製造方法
GB9626979A GB2309825B (en) 1995-12-30 1996-12-27 Semiconductor device and a method of fabricating the same
CN96123937A CN1075246C (zh) 1995-12-30 1996-12-30 半导体器件及其制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950069461A KR970052023A (ko) 1995-12-30 1995-12-30 에스 오 아이 소자 및 그의 제조방법

Publications (1)

Publication Number Publication Date
KR970052023A true KR970052023A (ko) 1997-07-29

Family

ID=19448459

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950069461A KR970052023A (ko) 1995-12-30 1995-12-30 에스 오 아이 소자 및 그의 제조방법

Country Status (6)

Country Link
JP (1) JPH1074921A (ko)
KR (1) KR970052023A (ko)
CN (1) CN1075246C (ko)
DE (1) DE19654280B4 (ko)
GB (1) GB2309825B (ko)
TW (1) TW312854B (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100318463B1 (ko) * 1998-10-28 2002-02-19 박종섭 몸체접촉실리콘이중막소자제조방법

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100281109B1 (ko) * 1997-12-15 2001-03-02 김영환 에스오아이(soi)소자및그의제조방법
EP0989613B1 (en) * 1998-08-29 2005-05-04 International Business Machines Corporation SOI transistor with body contact and method of forming same
DE69925078T2 (de) 1998-08-29 2006-03-09 International Business Machines Corp. SOI-Transistor mit einem Substrat-Kontakt und Verfahren zu dessen Herstellung
TW476993B (en) * 2000-01-19 2002-02-21 Advanced Micro Devices Inc Silicon on insulator circuit structure with buried semiconductor interconnect structure and method for forming same
US6368903B1 (en) * 2000-03-17 2002-04-09 International Business Machines Corporation SOI low capacitance body contact
JP2003100907A (ja) 2001-09-26 2003-04-04 Mitsubishi Electric Corp 半導体記憶装置およびその製造方法
JP5567247B2 (ja) * 2006-02-07 2014-08-06 セイコーインスツル株式会社 半導体装置およびその製造方法
CN101621009B (zh) * 2008-07-02 2012-03-21 中国科学院微电子研究所 一种制作部分耗尽soi器件体接触结构的方法
US9496227B2 (en) 2009-07-15 2016-11-15 Qualcomm Incorporated Semiconductor-on-insulator with back side support layer
US8232597B2 (en) 2009-07-15 2012-07-31 Io Semiconductor, Inc. Semiconductor-on-insulator with back side connection
US9466719B2 (en) 2009-07-15 2016-10-11 Qualcomm Incorporated Semiconductor-on-insulator with back side strain topology
US9390974B2 (en) 2012-12-21 2016-07-12 Qualcomm Incorporated Back-to-back stacked integrated circuit assembly and method of making
US9029201B2 (en) 2009-07-15 2015-05-12 Silanna Semiconductor U.S.A., Inc. Semiconductor-on-insulator with back side heat dissipation
US8921168B2 (en) 2009-07-15 2014-12-30 Silanna Semiconductor U.S.A., Inc. Thin integrated circuit chip-on-board assembly and method of making
TWI509780B (zh) 2009-07-15 2015-11-21 Silanna Semiconductor Usa Inc 積體電路及其製造方法
CN102683417A (zh) * 2012-05-17 2012-09-19 中国科学院微电子研究所 Soi mos晶体管
KR20140047494A (ko) * 2012-10-12 2014-04-22 삼성전자주식회사 서브픽셀, 이를 포함하는 이미지 센서, 및 이미지 센싱 시스템
US9215962B2 (en) 2014-03-13 2015-12-22 Ecovacs Robotics, Inc. Autonomous planar surface cleaning robot
US9515181B2 (en) 2014-08-06 2016-12-06 Qualcomm Incorporated Semiconductor device with self-aligned back side features

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5343067A (en) * 1987-02-26 1994-08-30 Kabushiki Kaisha Toshiba High breakdown voltage semiconductor device
DE3921038C2 (de) * 1988-06-28 1998-12-10 Ricoh Kk Verfahren zur Herstellung eines Halbleitersubstrats bzw. Festkörperaufbaus
JP2547663B2 (ja) * 1990-10-03 1996-10-23 三菱電機株式会社 半導体装置
EP0562127B1 (en) * 1991-10-14 2001-04-25 Denso Corporation Method for fabrication of semiconductor device
KR100267755B1 (ko) * 1993-03-18 2000-10-16 김영환 박막트랜지스터 제조방법
JPH08162642A (ja) * 1994-12-07 1996-06-21 Nippondenso Co Ltd 半導体装置およびその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100318463B1 (ko) * 1998-10-28 2002-02-19 박종섭 몸체접촉실리콘이중막소자제조방법

Also Published As

Publication number Publication date
CN1160293A (zh) 1997-09-24
JPH1074921A (ja) 1998-03-17
CN1075246C (zh) 2001-11-21
DE19654280B4 (de) 2005-11-10
DE19654280A1 (de) 1997-07-03
GB2309825A (en) 1997-08-06
GB9626979D0 (en) 1997-02-12
TW312854B (ko) 1997-08-11
GB2309825B (en) 2000-07-05

Similar Documents

Publication Publication Date Title
KR970052023A (ko) 에스 오 아이 소자 및 그의 제조방법
KR100356577B1 (ko) 에스오아이 기판과 그 제조방법 및 이를 이용한에스오아이 엠오에스에프이티
US5294821A (en) Thin-film SOI semiconductor device having heavily doped diffusion regions beneath the channels of transistors
KR100253699B1 (ko) Soi소자 및 그 제조방법
KR20010033347A (ko) 벌크 씨모스 구조와 양립 가능한 에스오아이 구조
KR960030438A (ko) 반도체 장치 및 그 제조 방법
KR960043267A (ko) 인버스 티(t)형 트랜지스터의 개선된 제조방법
KR970054334A (ko) 박막트랜지스터 및 그의 제조방법
US4051506A (en) Complementary semiconductor device
KR100296130B1 (ko) 이중막 실리콘웨이퍼를 이용한 금속-산화막-반도체 전계효과트랜지스터 제조방법
CN1092557A (zh) 一种介质隔离半导体器件及其制造方法
KR970003688A (ko) 반도체 소자의 트랜지스터 제조방법
US20010010380A1 (en) Field-effect transistor and manufacture thereof
KR960042931A (ko) Soi 구조를 갖는 반도체장치의 제조방법
KR850002696A (ko) 유전체 격리 구조를 가진 보상 반도체 장치를 제조 하는 방법
KR940010384A (ko) 박막트랜지스터 제조방법
KR970004079A (ko) 반도체소자 및 그 제조방법
JPS6211273A (ja) Ｍｏｓ集積回路装置の製造方法
JP2002141517A (ja) 半導体装置
KR100356792B1 (ko) 에스오아이 소자 및 그의 제조방법
KR960036037A (ko) 실리콘-온-인슐레이터(soi) 구조에서의 정전방전 보호소자 및 그 제조 방법
KR100327325B1 (ko) 실리콘-온-인슐레이터소자및그제조방법
JPH0669331A (ja) 半導体装置
KR960002744A (ko) 반도체 소자의 소자분리막 형성방법
KR970003962A (ko) 반도체 소자의 고집적 트렌지스터 제조 방법

Legal Events

Date Code Title Description
A201 Request for examination
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19951230

PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 19951230

Comment text: Request for Examination of Application

PG1501 Laying open of application
E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 19980925

Patent event code: PE09021S01D

E601 Decision to refuse application
PE0601 Decision on rejection of patent

Patent event date: 19990427

Comment text: Decision to Refuse Application

Patent event code: PE06012S01D

Patent event date: 19980925

Comment text: Notification of reason for refusal

Patent event code: PE06011S01I