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KR960043273A - Vertical transistor and manufacturing method thereof - Google Patents

Vertical transistor and manufacturing method thereof Download PDF

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Publication number
KR960043273A
KR960043273A KR1019950013443A KR19950013443A KR960043273A KR 960043273 A KR960043273 A KR 960043273A KR 1019950013443 A KR1019950013443 A KR 1019950013443A KR 19950013443 A KR19950013443 A KR 19950013443A KR 960043273 A KR960043273 A KR 960043273A
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KR
South Korea
Prior art keywords
insulating layer
layer pattern
conductive layer
pattern
forming
Prior art date
Application number
KR1019950013443A
Other languages
Korean (ko)
Other versions
KR0165398B1 (en
Inventor
임병학
Original Assignee
김광호
삼성전자 주식회사
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Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950013443A priority Critical patent/KR0165398B1/en
Priority to JP7244414A priority patent/JPH08330586A/en
Priority to US08/653,613 priority patent/US5707885A/en
Publication of KR960043273A publication Critical patent/KR960043273A/en
Priority to US08/925,394 priority patent/US6018176A/en
Application granted granted Critical
Publication of KR0165398B1 publication Critical patent/KR0165398B1/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6728—Vertical TFTs

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

버티칼 트랜지스터 및 그 제조방법이 게시되어 있다. 본 발명은 통상의 반도체기판에 SOI기판 구조를 형성하고 그 위에 차례로 적층되어 형성된 드레인 영역, 채널 영역, 및 소오스 영역과, 상기 채널 영역을 둘러싸는 원통형의 게이트 절연층과, 상기 게이트 절연층을 둘러싸는 원통형의 게이트 전극을 갖는 3차원 구조의 버티칼 트랜지스터를 형성하여 소정의 집적도를 증가시킴은 물론, 트렌치 공정을 사용하지 않음으로써 누설전류에 의한 특성저하를 방지할 수 있다.Vertical transistors and methods of manufacturing the same are disclosed. The present invention provides a drain region, a channel region, and a source region formed by forming an SOI substrate structure on a conventional semiconductor substrate and sequentially stacked thereon, a cylindrical gate insulating layer surrounding the channel region, and a gate insulating layer. By forming a vertical transistor having a three-dimensional structure having a cylindrical gate electrode to increase the predetermined degree of integration, it is possible to prevent the deterioration of characteristics due to leakage current by not using a trench process.

Description

버티칼(vertical) 트랜지스터 및 그 제조방법Vertical transistor and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 의한 3차원 트랜지스터의 평면도이다. 제3도는 제2도의 절단선 AA'에 따른, 본 발명의 제조방법에 의해 형성된 트랜지스터 구조를 도시한 단면도이다.2 is a plan view of a three-dimensional transistor according to the present invention. FIG. 3 is a cross-sectional view showing a transistor structure formed by the manufacturing method of the present invention along the cutting line AA 'of FIG.

Claims (5)

반도체기판 상에 차례로 형성된 제1절연층 및 제1도전층; 상기 제1도전층 상에 콘택홀을 가지면서 형성된 제2절연층 패턴; 상기 콘택홀 주위의 제2절연층 패턴 상부에 원통형의 변형된 제2도전층 패턴으로 형성된 게이트 전극; 상기 게이트 전극 상부에 형성된 제3절연층 패턴; 상기 게이트 전극 내벽에 제4절연층 패턴으로 형성된 게이트 절연층; 상기 제2절연층 패턴에 의해 형성된 홀의 내부에 제1단계의 제3도전층 패턴으로 이루어진 드레인 영역; 상기 게이트 절연층에 의해 형성된 홀의 내부에 제2단계의 제3도전층 패턴으로 이루어진 채널 영역; 및 상기 제3절연층 패턴에 의해 형성된 홀의 내부에 제3단계의 제3도전층 패턴으로 이루어진 소오스 영역을 포함하는 것을 특징으로 하는 버티칼 트랜지스터.A first insulating layer and a first conductive layer sequentially formed on the semiconductor substrate; A second insulating layer pattern having a contact hole on the first conductive layer; A gate electrode formed in a cylindrical deformed second conductive layer pattern on the second insulating layer pattern around the contact hole; A third insulating layer pattern formed on the gate electrode; A gate insulating layer formed on an inner wall of the gate electrode in a fourth insulating layer pattern; A drain region formed of the third conductive layer pattern of the first step in the hole formed by the second insulating layer pattern; A channel region having a third conductive layer pattern of a second step in the hole formed by the gate insulating layer; And a source region formed of the third conductive layer pattern of the third step in the hole formed by the third insulating layer pattern. 제1항에 있어서, 상기 제1도전층은 폴리실리콘 또는 텅스텐 폴리사이드로 형성하는 것을 특징으로 하는 버티칼 트랜지스터.The vertical transistor of claim 1, wherein the first conductive layer is formed of polysilicon or tungsten polyside. 제1항에 있어서, 상기 드레인 영역, 상기 채널 영역, 및 상기 소오스 영역은 에피택시얼층으로 형성하는 것을 특징으로 하느 버티칼 트랜지스터.The vertical transistor of claim 1, wherein the drain region, the channel region, and the source region are formed of an epitaxial layer. 반도체기판 전면에 제1절연층, 제1도전층 및 제2절연층을 차례로 형성하는 단계; 상기 제2절연층 상부에 제2도전층 패턴을 형성하는 단계; 상기 제2도전층 패턴이 형성된 반도체기판 전면에 제3절연층을 형성하는 단계; 상기 제2도전층 패턴의 중앙부분 상부의 제3절연층이 노출되도록 포토레지스트 패턴을 형성하는 단계; 상기 포토레지스트 패턴을 식각마스크로 하여 상기 제3절연층, 상기 제2도전층 패턴, 및 상기 제2절연층을 연속적으로 식각함으로써, 제3절연층 패턴, 1차 변형된 제2도전층 패턴, 및 제2절연층 패턴을 형성하는 단계; 상기 1차 변형된 제2도전층 패턴을 등방성 식각하여 일정 두께의 내벽이 식각된 2차 변형된 제2도전층 패턴으로 이루어진 게이트 전극을 형성하는 단계; 상기 포토레지스트 패턴을 제거하는 단계; 상기 게이트 전극 내벽에 제4절연층 패턴으로 이루어진 게이트 절연층을 형성하는 단계; 상기 제2절연층 패턴에 의해 형성된 홀의 내부에 제1단계의 제3도전층 패턴으로 이루어진 드레인 영역을 형성하는 단계; 상기 게이트 절연층에 의해 형성된 홀의 내부에 제2단계의 제3도전층 패턴으로 이루어진 채널 영역을 형성하는 단계; 및 상기 제4절연층 패턴에 의해 형성된 홀의 내부에 제3단계의 제3도전층 패턴으로 이루어진 소오스 영역을 형성하는 단계를 포함하는 것을 특징으로 하는 버티칼 트랜지스터 제조방법.Sequentially forming a first insulating layer, a first conductive layer, and a second insulating layer on the entire surface of the semiconductor substrate; Forming a second conductive layer pattern on the second insulating layer; Forming a third insulating layer on an entire surface of the semiconductor substrate on which the second conductive layer pattern is formed; Forming a photoresist pattern to expose a third insulating layer over a central portion of the second conductive layer pattern; By sequentially etching the third insulating layer, the second conductive layer pattern, and the second insulating layer using the photoresist pattern as an etching mask, a third insulating layer pattern, a first modified second conductive layer pattern, And forming a second insulating layer pattern; Isotropically etching the first deformed second conductive layer pattern to form a gate electrode including a second deformed second conductive layer pattern etched by an inner wall of a predetermined thickness; Removing the photoresist pattern; Forming a gate insulating layer having a fourth insulating layer pattern on the inner wall of the gate electrode; Forming a drain region formed of the third conductive layer pattern of the first step in the hole formed by the second insulating layer pattern; Forming a channel region having a third conductive layer pattern of a second step in the hole formed by the gate insulating layer; And forming a source region formed of the third conductive layer pattern of the third step in the hole formed by the fourth insulating layer pattern. 제4항에 있어서, 상기 드레인 영역, 상기 채널 영역, 및 상기 소오스 영역은 에피택시얼층으로 형성하는 것을 특징으로 하는 버티칼 트랜지스터의 제조방법.The method of claim 4, wherein the drain region, the channel region, and the source region are formed of an epitaxial layer. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950013443A 1995-05-26 1995-05-26 Vertical transistor manufacturing method KR0165398B1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1019950013443A KR0165398B1 (en) 1995-05-26 1995-05-26 Vertical transistor manufacturing method
JP7244414A JPH08330586A (en) 1995-05-26 1995-09-22 Vertical transistor and manufacturing method thereof
US08/653,613 US5707885A (en) 1995-05-26 1996-05-24 Method for manufacturing a vertical transistor having a storage node vertical transistor
US08/925,394 US6018176A (en) 1995-05-26 1997-09-08 Vertical transistor and memory cell

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KR1019950013443A KR0165398B1 (en) 1995-05-26 1995-05-26 Vertical transistor manufacturing method

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