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KR960035900A - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method Download PDF

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Publication number
KR960035900A
KR960035900A KR1019950006073A KR19950006073A KR960035900A KR 960035900 A KR960035900 A KR 960035900A KR 1019950006073 A KR1019950006073 A KR 1019950006073A KR 19950006073 A KR19950006073 A KR 19950006073A KR 960035900 A KR960035900 A KR 960035900A
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KR
South Korea
Prior art keywords
gate
forming
conductive film
film
layer
Prior art date
Application number
KR1019950006073A
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Korean (ko)
Other versions
KR100321759B1 (en
Inventor
인성욱
최진호
Original Assignee
김주용
현대전자산업 주식회사
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950006073A priority Critical patent/KR100321759B1/en
Publication of KR960035900A publication Critical patent/KR960035900A/en
Application granted granted Critical
Publication of KR100321759B1 publication Critical patent/KR100321759B1/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/013—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0149—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 기판 상에 게이트 산화막 및 게이트 제1전도막을 차례로 형성하는 단계; 상기 게이트 제1전도막의 소정부위를 전체두께중 소정두께 식각하고 상기 식각된 부위에 제1절연막을 형성하는 단계; 게이트 마스크를 사용하여 상기 제1절연막, 게이트 제1전도막, 게이트 산화막을 차례로 식각하는 단계; 소오스/드레인 접합영역을 형성하는 단계; 전체구조 상부에 평탄화 제2절연막을 형성하는 단계; 및 상기 소오스/드레인 접합영역에 상기 게이트 제1전도막 패턴 사이의 공간을 통과하는 제2전도막을 콘택 시키는 단계를 포함하는 것을 특징으로 하는 반도체 소자 제조 방법에 관한 것으로서, 게이트 패턴 상부 코너(conner) 부분을 절연막으로 형성함으로써 게이트 및, 비트라인간의 공간을 증가시켜, 비트라인 또는 Vss 라인 콘택 마스크 작업시의 오정렬에 관련된 공정 마진을 확보하여 누설전류 방지와 소자의 제조 수율을 향상시키는 효과가 있다.The present invention comprises the steps of sequentially forming a gate oxide film and a gate first conductive film on a semiconductor substrate; Etching a predetermined portion of the gate first conductive layer to a predetermined thickness of a total thickness and forming a first insulating layer on the etched portion; Etching the first insulating layer, the gate first conductive layer, and the gate oxide layer in sequence using a gate mask; Forming a source / drain junction region; Forming a planarization second insulating layer on the entire structure; And contacting the second conductive film passing through the space between the gate first conductive film pattern to the source / drain junction region, wherein the upper portion of the gate pattern upper corner is formed. By forming the portion as an insulating film, the space between the gate and the bit line is increased, thereby securing a process margin related to misalignment during bit line or Vss line contact mask operation, thereby preventing leakage current and improving device manufacturing yield.

Description

반도체 소자 제조방법Semiconductor device manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1A도 내지 제1G도는 본 발명의 일실시예에 따른 버퍼용 비트라인 형성 공정도.1A to 1G are diagrams illustrating a process of forming a bit line for a buffer according to an embodiment of the present invention.

Claims (3)

반도체 기판 상에 게이트 산화막 및 게이트 제1전도막을 차례로 형성하는 단계; 상기 게이트 제1전도막의 소정부위를 전체두께중 소정두께 식각하고 상기 식각된 부위에 제1절연막을 형성하는 단계; 게이트 마스크를 사용하여 상기 제1절연막, 게이트 제1전도막, 게이트 산화막을 차례로 식각하는 단계; 소오스/드레인 접합영역을 형성하는 단계; 전체 구조 상부에 평탄화 제2절연막을 형성하는 단계; 및 상기 소오스/드레인 접합영역에 상기 게이트 제1전도막 패턴 사이의 공간을 통과하는 제2전도막을 콘택시키는 단계를 포함하는 것을 특징으로 하는 반도체 소자 제조방법.Sequentially forming a gate oxide film and a gate first conductive film on the semiconductor substrate; Etching a predetermined portion of the gate first conductive layer to a predetermined thickness of a total thickness and forming a first insulating layer on the etched portion; Etching the first insulating layer, the gate first conductive layer, and the gate oxide layer in sequence using a gate mask; Forming a source / drain junction region; Forming a planarization second insulating layer on the entire structure; And contacting the second conductive film passing through the space between the gate first conductive film pattern to the source / drain junction region. 제1항에 있어서; 상기 제2전도막 콘택 단계는 제2전도막 콘택 마스크 및 상기 평탄화 제2절연막 식각공정으로 접합영역을 오픈시켜 콘택홀을 형성하는 단계; 상기콘택홀 측벽에 스페이서 제3절연막을 형성하는 단계; 제2전도막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자 제조 방법.The method of claim 1; The second conductive layer contacting step may include forming a contact hole by opening a junction region through a second conductive layer contact mask and the planarized second insulating layer etching process; Forming a spacer third insulating layer on sidewalls of the contact hole; A method of manufacturing a semiconductor device comprising the step of forming a second conductive film. 제1항에 있어서, 상기 제2전도막 콘택 단계는 제2전도막 콘택 마스크를 사용하여 상기 평탄화 제2연막의 전체두께중 소정두께를 식각하는 단계; 상기 평탄화 제2절연막이 식각된 부위의 측벽에 스페이서 제3절연막을 형성하는 동시에 제2절연막을 식각하여 접합영역을 오픈시키는 단계; 제2전도막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자 제조 방법.The method of claim 1, wherein the second conductive film contacting step comprises: etching a predetermined thickness of the entire thickness of the planarized second smoke film using a second conductive film contact mask; Forming a spacer third insulating film on a sidewall of the portion where the planarized second insulating film is etched and simultaneously etching the second insulating film to open a junction region; A method of manufacturing a semiconductor device comprising the step of forming a second conductive film. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950006073A 1995-03-22 1995-03-22 Method for fabricating semiconductor device KR100321759B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950006073A KR100321759B1 (en) 1995-03-22 1995-03-22 Method for fabricating semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950006073A KR100321759B1 (en) 1995-03-22 1995-03-22 Method for fabricating semiconductor device

Publications (2)

Publication Number Publication Date
KR960035900A true KR960035900A (en) 1996-10-28
KR100321759B1 KR100321759B1 (en) 2002-05-13

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950006073A KR100321759B1 (en) 1995-03-22 1995-03-22 Method for fabricating semiconductor device

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Publication number Publication date
KR100321759B1 (en) 2002-05-13

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