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KR960043091A - 반도체장치의 제조방법 - Google Patents

반도체장치의 제조방법 Download PDF

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Publication number
KR960043091A
KR960043091A KR1019950011830A KR19950011830A KR960043091A KR 960043091 A KR960043091 A KR 960043091A KR 1019950011830 A KR1019950011830 A KR 1019950011830A KR 19950011830 A KR19950011830 A KR 19950011830A KR 960043091 A KR960043091 A KR 960043091A
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KR
South Korea
Prior art keywords
substrate
layer
insulating film
forming
semiconductor device
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Application number
KR1019950011830A
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English (en)
Other versions
KR0179823B1 (ko
Inventor
박종성
Original Assignee
문정환
Lg 반도체 주식회사
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Publication date
Application filed by 문정환, Lg 반도체 주식회사 filed Critical 문정환
Priority to KR1019950011830A priority Critical patent/KR0179823B1/ko
Priority to US08/572,958 priority patent/US5686327A/en
Priority to JP7333448A priority patent/JP2931243B2/ja
Priority to DE19548386A priority patent/DE19548386C2/de
Publication of KR960043091A publication Critical patent/KR960043091A/ko
Application granted granted Critical
Publication of KR0179823B1 publication Critical patent/KR0179823B1/ko

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0151—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/671—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor having lateral variation in doping or structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0135—Manufacturing their gate conductors
    • H10D84/0142—Manufacturing their gate conductors the gate conductors having different shapes or dimensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 모스트랜지스터를 기판에 형성하는 공정을 진행하는 도중에 그 모스트랜지스터의 소자격리 절연막을 자기정합적으로 형성하는 반도체장치의 제조공정을 단순화시킬 수 있음과 아울러 그 기판을 수직으로 식각하여 그 기판의 돌출영역을 형성하고 그 돌출영역의 수직높이로 그 모스트랜지스터의 게이트의 길이를 조절할 수 있어 반도제장치의 집적도를 향상시킬 수 있음으로서 고집적 반도체소자의 설계에 최소 설계법을 용이하게 적용할 수 있다.

Description

반도체장치의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도의 (A)~(F)는 본 발명에 의한 반도체장치의 제조방법을 나타낸 공정도.

Claims (9)

  1. 기판상에 확산층과 그 확산층상의 제1절연막을 원하는 패턴으로 형성하는 단계와, 그 원하는 패턴의 확산층을 제외한 영역의 상기 기판을 원하는 깊이로 식각하는 단계와, 상기 원하는 패턴의 절연막과 확산층 및 상기 깊이에 해당하는 높이로 상기 확산층의 하부에 삭각되지 않고 남아 있는 영역의 상기 기판의 측면에 제2절연 의 측벽 스페이서를 형성하는 단계와, 상기 기판의 측면에 제2절연막의 측벽 스페이서를 형성하는 단계와, 상기 기판의 원하는 영역에 소자격리 절연막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체장치의 제조방법.
  2. 제1항에 있어서, 상기 제2절연막의 측벽 스페이서를 제거하여 상기 기판과 상기 원하는 패턴의 확산층의 표면을 노출하고 그 노출된 기판과 혹산층의 표면상에 게이트 절연막을 형성하는 단계와, 상기 게이트 절연막 상에 게이트로서 도전층의 측벽 스페이서를 형성하는 단계와, 상기 도전층의 측벽 스페이서에 자기정합된 영역의 기판내에 확산영역을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체장치의 제조방법.
  3. 제1항에 있어서, 상기 원하는 패턴의 확산층이 모스트랜지스터의 드레인영역인 것을 특징으로 하는 반도체장치의 제조방법.
  4. 제1항에 있어서, 상기 원하는 패턴의 확산층이 상기 기판상에 단결정 실리콘층을 에피택셜 성장된 것을 특징으로 하는 반도체장치의 제조방법.
  5. 제1항에 있어서, 상기 높이가 상기 게이트의 길이를 결정하는데 이용되는 것을 특징으로 하는 반도체장치의 제조방법.
  6. 제1항에 있어서, 상기 소자격리 절연막이 자기정합되어 형성된 것을 특징으로 하는 반도체장치의 제조방법.
  7. 제6항에 있어서, 상기 소자격리 절연막이 상기 제2절연막의 측벽 스페이서들로 자기정합되어 형성된 것을 특징으로 하는 반도체장치의 제조방법.
  8. 제2항에 있어서, 상기 도전층이 다결정 실리콘층인 것을 특징으로 하는 반도체장치의 제조방법.
  9. 제2항에 있어서, 상기 확산영역이 소오스영역인 것을 특징으로 하는 반도체장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950011830A 1995-05-13 1995-05-13 반도체장치의 제조방법 KR0179823B1 (ko)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1019950011830A KR0179823B1 (ko) 1995-05-13 1995-05-13 반도체장치의 제조방법
US08/572,958 US5686327A (en) 1995-05-13 1995-12-15 Method for fabricating semiconductor device
JP7333448A JP2931243B2 (ja) 1995-05-13 1995-12-21 半導体素子の製造方法
DE19548386A DE19548386C2 (de) 1995-05-13 1995-12-22 Verfahren zur Herstellung eines Halbleiterbauelements

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950011830A KR0179823B1 (ko) 1995-05-13 1995-05-13 반도체장치의 제조방법

Publications (2)

Publication Number Publication Date
KR960043091A true KR960043091A (ko) 1996-12-23
KR0179823B1 KR0179823B1 (ko) 1999-04-15

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ID=19414387

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Application Number Title Priority Date Filing Date
KR1019950011830A KR0179823B1 (ko) 1995-05-13 1995-05-13 반도체장치의 제조방법

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US (1) US5686327A (ko)
JP (1) JP2931243B2 (ko)
KR (1) KR0179823B1 (ko)
DE (1) DE19548386C2 (ko)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW308741B (en) * 1996-11-22 1997-06-21 United Microelectronics Corp Micro-coil structure of integrated circuit and process thereof
DE19758430C2 (de) * 1997-04-28 2002-09-05 Infineon Technologies Ag Integrierte Schaltungsanordnung mit mindestens einem vertikalen MOS-Transistor und Verfahren zu deren Herstellung
KR100261305B1 (ko) * 1997-12-17 2000-07-01 이계철 수직 채널 트랜지스터의 제조방법
US20060108641A1 (en) * 2004-11-19 2006-05-25 Taiwan Semiconductor Manufacturing Company, Ltd. Device having a laterally graded well structure and a method for its manufacture

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Publication number Priority date Publication date Assignee Title
US3993513A (en) * 1974-10-29 1976-11-23 Fairchild Camera And Instrument Corporation Combined method for fabricating oxide-isolated vertical bipolar transistors and complementary oxide-isolated lateral bipolar transistors and the resulting structures
JPS5673446A (en) * 1979-11-21 1981-06-18 Chiyou Lsi Gijutsu Kenkyu Kumiai Manufacture of semiconductor device
US4366613A (en) * 1980-12-17 1983-01-04 Ibm Corporation Method of fabricating an MOS dynamic RAM with lightly doped drain
EP0333426B1 (en) * 1988-03-15 1996-07-10 Kabushiki Kaisha Toshiba Dynamic RAM
US5258635A (en) * 1988-09-06 1993-11-02 Kabushiki Kaisha Toshiba MOS-type semiconductor integrated circuit device
JP2551127B2 (ja) * 1989-01-07 1996-11-06 三菱電機株式会社 Ｍｉｓ型半導体装置およびその製造方法
US5021355A (en) * 1989-05-22 1991-06-04 International Business Machines Corporation Method of fabricating cross-point lightly-doped drain-source trench transistor
US5132238A (en) * 1989-12-28 1992-07-21 Nissan Motor Co., Ltd. Method of manufacturing semiconductor device utilizing an accumulation layer
JPH0461123A (ja) * 1990-06-22 1992-02-27 Nec Corp 半導体装置の素子分離方法
US5177027A (en) * 1990-08-17 1993-01-05 Micron Technology, Inc. Process for fabricating, on the edge of a silicon mesa, a MOSFET which has a spacer-shaped gate and a right-angled channel path
US5087581A (en) * 1990-10-31 1992-02-11 Texas Instruments Incorporated Method of forming vertical FET device with low gate to source overlap capacitance
JPH0817814A (ja) * 1994-06-28 1996-01-19 Sony Corp 素子分離用酸化阻止膜の形成方法
US5494837A (en) * 1994-09-27 1996-02-27 Purdue Research Foundation Method of forming semiconductor-on-insulator electronic devices by growing monocrystalline semiconducting regions from trench sidewalls

Also Published As

Publication number Publication date
US5686327A (en) 1997-11-11
KR0179823B1 (ko) 1999-04-15
JPH08316477A (ja) 1996-11-29
DE19548386A1 (de) 1996-11-14
JP2931243B2 (ja) 1999-08-09
DE19548386C2 (de) 2002-01-17

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