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KR960006002A - 트랜지스터 제조방법 - Google Patents

트랜지스터 제조방법 Download PDF

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Publication number
KR960006002A
KR960006002A KR1019940017683A KR19940017683A KR960006002A KR 960006002 A KR960006002 A KR 960006002A KR 1019940017683 A KR1019940017683 A KR 1019940017683A KR 19940017683 A KR19940017683 A KR 19940017683A KR 960006002 A KR960006002 A KR 960006002A
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KR
South Korea
Prior art keywords
forming
nitride film
substrate
gate
source
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KR1019940017683A
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English (en)
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KR0135147B1 (ko
Inventor
김홍선
황이연
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문정환
엘지반도체 주식회사
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Priority to KR1019940017683A priority Critical patent/KR0135147B1/ko
Priority to US08/462,042 priority patent/US5620912A/en
Priority to JP7206731A priority patent/JPH0846202A/ja
Publication of KR960006002A publication Critical patent/KR960006002A/ko
Application granted granted Critical
Publication of KR0135147B1 publication Critical patent/KR0135147B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/256—Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 트랜지스터 제조방법에 관한 것으로, 고내압 및 고속특성을 갖는 트랜지스터를 제조하는방법에 관한 것이다.
본 발명은 반도체기판상에 게이트절연막을 개재하여 게이트를 형성하는 공정과, 상기 게이트 측면에 측벽스페이서를 형성하는 공정, 소오스 및 드레인영역이 형성될 기판부위를 등방석식각에 의해 식각하는 공정, 상기 측벽스페이서 하부의 식각된 기판영역상에만 선택적으로 질화막을 제거하는 공정, 상기식각된 기판부위를 폴리실리콘으로 매몰시키는 공정, 열처리를 행하여 상기 폴리실리콘층내의 불순물이 기판으로 자동도핑되도록 하여 소오스 및 드레인영역을 형성하는 공정으로 이루어진다.

Description

트랜지스터 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음

Claims (2)

  1. 반도체기판상에 게이트절연막을 개재하여 게이트를 형성하는 공정과, 상기 게이트 측면에 측벽스페이서를 형성하는 공정, 소오스 및 드레인영역이 형성될 기판부위를 등방성 식각에 의해 식각하는 공정, 상기 측벽스페이서 하부의 식각된 기판영역상에만 선택적으로 질화막을 형성하는 공정, 상기 질화막의 형성된 영역을 제외한 전영역상에 산화막을 형성하는 공정, 상기 질화막을 제거하는 공정, 상기 식각된 기판부위를 폴리실리콘으로 매몰시키는 공정, 열처리를 행하여 상기 폴리실리콘층내의 불순물이 기판으로 자동도핑되도록 하여 소오스 및 드레인영역을 형성하는 공정으로 이루어지는 것을 특징으로 하는 트랜지스터 제조방법.
  2. 제1항에 있어서, 상기 측벽스페이서의 하부의 식각된 기판영역상에만 선택적으로 질화막을 형성하는 공정은 상기 소오스 및 드레인영역이 형성될 기판부위를 등방성식각에 의해 식각하나 후, 결과물 전면에 질화막을 형성하고, 형성된 질화막을 비등방성식각함으로써 행하는 것을 특징으로 하는트랜지스터 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940017683A 1994-07-21 1994-07-21 트랜지스터 제조방법 Expired - Fee Related KR0135147B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019940017683A KR0135147B1 (ko) 1994-07-21 1994-07-21 트랜지스터 제조방법
US08/462,042 US5620912A (en) 1994-07-21 1995-06-05 Method of manufacturing a semiconductor device using a spacer
JP7206731A JPH0846202A (ja) 1994-07-21 1995-07-21 半導体素子の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940017683A KR0135147B1 (ko) 1994-07-21 1994-07-21 트랜지스터 제조방법

Publications (2)

Publication Number Publication Date
KR960006002A true KR960006002A (ko) 1996-02-23
KR0135147B1 KR0135147B1 (ko) 1998-04-22

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940017683A Expired - Fee Related KR0135147B1 (ko) 1994-07-21 1994-07-21 트랜지스터 제조방법

Country Status (3)

Country Link
US (1) US5620912A (ko)
JP (1) JPH0846202A (ko)
KR (1) KR0135147B1 (ko)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100434715B1 (ko) * 1997-12-29 2004-11-06 주식회사 하이닉스반도체 반도체소자및그제조방법
KR20200071544A (ko) * 2018-12-11 2020-06-19 한국공항공사 탑승교 및 탑승교 제어 방법

Families Citing this family (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5710450A (en) * 1994-12-23 1998-01-20 Intel Corporation Transistor with ultra shallow tip and method of fabrication
US5798291A (en) * 1995-03-20 1998-08-25 Lg Semicon Co., Ltd. Method of making a semiconductor device with recessed source and drain
US5691212A (en) * 1996-09-27 1997-11-25 Taiwan Semiconductor Manufacturing Company, Ltd. MOS device structure and integration method
US5908313A (en) * 1996-12-31 1999-06-01 Intel Corporation Method of forming a transistor
JPH10223889A (ja) * 1997-02-04 1998-08-21 Mitsubishi Electric Corp Ｍｉｓトランジスタおよびその製造方法
US6107172A (en) * 1997-08-01 2000-08-22 Advanced Micro Devices, Inc. Controlled linewidth reduction during gate pattern formation using an SiON BARC
US5963841A (en) * 1997-08-01 1999-10-05 Advanced Micro Devices, Inc. Gate pattern formation using a bottom anti-reflective coating
US5965461A (en) * 1997-08-01 1999-10-12 Advanced Micro Devices, Inc. Controlled linewidth reduction during gate pattern formation using a spin-on barc
US6121123A (en) * 1997-09-05 2000-09-19 Advanced Micro Devices, Inc. Gate pattern formation using a BARC as a hardmask
DE19749378B4 (de) * 1997-11-07 2006-10-26 Infineon Technologies Ag MOS-Transistor und Verfahren zu dessen Herstellung
DE19812643C1 (de) * 1998-03-23 1999-07-08 Siemens Ag Schaltungsstruktur mit einem MOS-Transistor und Verfahren zu deren Herstellung
US6198142B1 (en) 1998-07-31 2001-03-06 Intel Corporation Transistor with minimal junction capacitance and method of fabrication
US6071783A (en) * 1998-08-13 2000-06-06 Taiwan Semiconductor Manufacturing Company Pseudo silicon on insulator MOSFET device
JP2000091561A (ja) * 1998-09-14 2000-03-31 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6090673A (en) * 1998-10-20 2000-07-18 International Business Machines Corporation Device contact structure and method for fabricating same
US6887762B1 (en) * 1998-11-12 2005-05-03 Intel Corporation Method of fabricating a field effect transistor structure with abrupt source/drain junctions
US6207514B1 (en) 1999-01-04 2001-03-27 International Business Machines Corporation Method for forming borderless gate structures and apparatus formed thereby
US6759315B1 (en) 1999-01-04 2004-07-06 International Business Machines Corporation Method for selective trimming of gate structures and apparatus formed thereby
US5998248A (en) * 1999-01-25 1999-12-07 International Business Machines Corporation Fabrication of semiconductor device having shallow junctions with tapered spacer in isolation region
US6025242A (en) * 1999-01-25 2000-02-15 International Business Machines Corporation Fabrication of semiconductor device having shallow junctions including an insulating spacer by thermal oxidation creating taper-shaped isolation
US6022771A (en) * 1999-01-25 2000-02-08 International Business Machines Corporation Fabrication of semiconductor device having shallow junctions and sidewall spacers creating taper-shaped isolation where the source and drain regions meet the gate regions
US5998273A (en) * 1999-01-25 1999-12-07 International Business Machines Corporation Fabrication of semiconductor device having shallow junctions
TW415010B (en) * 1999-04-20 2000-12-11 Mosel Vitelic Inc Method for fabricating trench capacitor
US6229187B1 (en) 1999-10-20 2001-05-08 Advanced Micro Devices, Inc. Field effect transistor with non-floating body and method for forming same on a bulk silicon wafer
US6376286B1 (en) * 1999-10-20 2002-04-23 Advanced Micro Devices, Inc. Field effect transistor with non-floating body and method for forming same on a bulk silicon wafer
US6465852B1 (en) 1999-10-20 2002-10-15 Advanced Micro Devices, Inc. Silicon wafer including both bulk and SOI regions and method for forming same on a bulk silicon wafer
US6245636B1 (en) 1999-10-20 2001-06-12 Advanced Micro Devices, Inc. Method of formation of pseudo-SOI structures with direct contact of transistor body to the substrate
US6541343B1 (en) * 1999-12-30 2003-04-01 Intel Corporation Methods of making field effect transistor structure with partially isolated source/drain junctions
US6514809B1 (en) 2000-11-03 2003-02-04 Advanced Micro Devices, Inc. SOI field effect transistors with body contacts formed by selective etch and fill
US6306715B1 (en) * 2001-01-08 2001-10-23 Chartered Semiconductor Manufacturing Ltd. Method to form smaller channel with CMOS device by isotropic etching of the gate materials
DE10121494A1 (de) * 2001-05-03 2002-11-14 Infineon Technologies Ag Transistor und integrierter Schaltkreis
US6509221B1 (en) * 2001-11-15 2003-01-21 International Business Machines Corporation Method for forming high performance CMOS devices with elevated sidewall spacers
KR100406537B1 (ko) * 2001-12-03 2003-11-20 주식회사 하이닉스반도체 반도체장치의 제조 방법
TW569319B (en) * 2002-06-06 2004-01-01 Winbond Electronics Corp Gate structure and method of manufacture
DE10246718A1 (de) 2002-10-07 2004-04-22 Infineon Technologies Ag Feldeffekttransistor mit lokaler Source-/Drainisolation sowie zugehöriges Herstellungsverfahren
US6858505B2 (en) * 2002-10-08 2005-02-22 Samsung Electronics Co. Ltd. Methods of forming transistor structures including separate anti-punchthrough layers
KR100584776B1 (ko) * 2004-03-05 2006-05-29 삼성전자주식회사 반도체 장치의 액티브 구조물 형성 방법, 소자 분리 방법및 트랜지스터 형성 방법
JP5203558B2 (ja) * 2004-08-20 2013-06-05 三星電子株式会社 トランジスタ及びこれの製造方法
KR100547934B1 (ko) * 2004-08-20 2006-01-31 삼성전자주식회사 트랜지스터 및 그의 제조 방법
US7195985B2 (en) * 2005-01-04 2007-03-27 Intel Corporation CMOS transistor junction regions formed by a CVD etching and deposition sequence
US20080121932A1 (en) * 2006-09-18 2008-05-29 Pushkar Ranade Active regions with compatible dielectric layers
KR100637692B1 (ko) * 2005-06-27 2006-10-25 주식회사 하이닉스반도체 반도체 소자 및 그 제조 방법
US20090032880A1 (en) * 2007-08-03 2009-02-05 Applied Materials, Inc. Method and apparatus for tunable isotropic recess etching of silicon materials
DE102008049733B3 (de) * 2008-09-30 2010-06-17 Advanced Micro Devices, Inc., Sunnyvale Transistor mit eingebettetem Si/Ge-Material mit geringerem Abstand zum Kanalgebiet und Verfahren zur Herstellung des Transistors
KR101068575B1 (ko) 2009-07-03 2011-09-30 주식회사 하이닉스반도체 반도체 장치 및 그 제조방법
CN102956493A (zh) * 2011-08-24 2013-03-06 中芯国际集成电路制造(上海)有限公司 晶体管及其形成方法
CN103137490B (zh) * 2011-12-05 2016-02-03 中芯国际集成电路制造(北京)有限公司 半导体器件及其制造方法
US9536945B1 (en) * 2015-07-30 2017-01-03 International Business Machines Corporation MOSFET with ultra low drain leakage
US11881481B2 (en) * 2021-04-06 2024-01-23 Invention And Collaboration Laboratory Pte. Ltd. Complementary MOSFET structure with localized isolations in silicon substrate to reduce leakages and prevent latch-up
CN115602648A (zh) * 2021-07-09 2023-01-13 长鑫存储技术有限公司（Cn） 半导体结构及其制作方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61237470A (ja) * 1985-04-15 1986-10-22 Hitachi Ltd 半導体装置
JPS61237471A (ja) * 1985-04-15 1986-10-22 Hitachi Ltd 半導体集積回路装置及びその製造方法
JPH01187870A (ja) * 1988-01-22 1989-07-27 Hitachi Ltd 半導体装置およびその製造方法
US4963502A (en) * 1988-08-25 1990-10-16 Texas Instruments, Incorporated Method of making oxide-isolated source/drain transistor
JP2510710B2 (ja) * 1988-12-13 1996-06-26 三菱電機株式会社 絶縁体基板上の半導体層に形成されたｍｏｓ型電界効果トランジスタ
JPH02246267A (ja) * 1989-03-20 1990-10-02 Fujitsu Ltd 半導体装置の製造方法
US5191397A (en) * 1989-09-07 1993-03-02 Kabushiki Kaisha Toshiba SOI semiconductor device with a wiring electrode contacts a buried conductor and an impurity region
US5017998A (en) * 1989-09-14 1991-05-21 Fujitsu Limited Semiconductor device using SOI substrate
JP2603886B2 (ja) * 1991-05-09 1997-04-23 日本電信電話株式会社 薄層ｓｏｉ型絶縁ゲート型電界効果トランジスタの製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100434715B1 (ko) * 1997-12-29 2004-11-06 주식회사 하이닉스반도체 반도체소자및그제조방법
KR20200071544A (ko) * 2018-12-11 2020-06-19 한국공항공사 탑승교 및 탑승교 제어 방법

Also Published As

Publication number Publication date
JPH0846202A (ja) 1996-02-16
KR0135147B1 (ko) 1998-04-22
US5620912A (en) 1997-04-15

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