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KR0135147B1 - 트랜지스터 제조방법 - Google Patents

트랜지스터 제조방법

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Publication number
KR0135147B1
KR0135147B1 KR1019940017683A KR19940017683A KR0135147B1 KR 0135147 B1 KR0135147 B1 KR 0135147B1 KR 1019940017683 A KR1019940017683 A KR 1019940017683A KR 19940017683 A KR19940017683 A KR 19940017683A KR 0135147 B1 KR0135147 B1 KR 0135147B1
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South Korea
Prior art keywords
forming
nitride film
substrate
gate
source
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Application number
KR1019940017683A
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English (en)
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KR960006002A (ko
Inventor
김홍선
황이연
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문정환
엘지반도체주식회사
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Priority to KR1019940017683A priority Critical patent/KR0135147B1/ko
Priority to US08/462,042 priority patent/US5620912A/en
Priority to JP7206731A priority patent/JPH0846202A/ja
Publication of KR960006002A publication Critical patent/KR960006002A/ko
Application granted granted Critical
Publication of KR0135147B1 publication Critical patent/KR0135147B1/ko

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/256—Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 트랜지스터 제조방법에 관한 것으로, 고내압 및 고속특성을 갖는 트랜지스터를 제조하는방법에 관한 것이다.
본 발명은 반도체기판상에 게이트절연막을 개재하여 게이트를 형성하는 공정과, 상기 게이트 측면에 측벽스페이서를 형성하는 공정, 소오스 및 드레인영역이 형성될 기판부위를 등방석식각에 의해 식각하는 공정, 상기 측벽스페이서 하부의 식각된 기판영역상에만 선택적으로 질화막을 제거하는 공정, 상기식각된 기판부위를 폴리실리콘으로 매몰시키는 공정, 열처리를 행하여 상기 폴리실리콘층내의 불순물이 기판으로 자동도핑되도록 하여 소오스 및 드레인영역을 형성하는 공정으로 이루어진다.

Description

트랜지스터 제조방법
제1도는 일반적인 MOSFET 단면구조도.
제2도는 본 발명에 의한 트랜지스터 제조방법을 도시한 공정순서도.
* 도면의 주요부분에 대한 부호의 설명
1 : 반도체기판 2 : 게이트절연막
3 : 게이트 6 : 게이트 캡산화막
7 : 측벽스페이서 8 : 질화막
9 : 산화막 10 : 폴리실리콘
11 : 소오스 및 드레인영역 15 : 필드산화막
본 발명은 트랜지스터 제조방법에 관한 것으로, 특히 고내압 및 고속특성을 갖는 트랜지스터 제조방법에 관한 것이다.
가장 일반적인 MOSFET(Metal Oxide Semiconductor)는 제1도에 도시된 바와 같이 반도체기판(1)상에 절연물질인 게이트절연막(2)을 개재하여 형성된 게이트전극(3)과 게이트전극 양단의 기판부위에 형성된 불순물 접합영역인 소오스(4)와 드레인(5)으로 이루어진다.
본 발명은 상기 MOSFET의 동작과 동일한 동작을 하면서 채널영역이외의 불순물 접합영역은 산화막으로 보호되도록 함으로써 접합 누설을 감소시키고, 벌크실리콘과의 접합 커패시턴스를 감소시킬 수 있도록 한 트랜지스터의 제조방법을 제공하는 것을 그 목적으로 한다.
상기 목적을 달성하기 위한 본 발명의 트랜지스터 제조방법은 반도체기판상에 게이트절연막을 개재하여 게이트를 형성하는 공정과, 상기 게이트 측면에 측벽스페이서를 형성하는 공정, 소오스 및 드레인영역이 형성될 기판부위를 등방성 식각에 의해 식각하는 공정, 상기 측벽스페이서 하부의 식각된 기판영역상에만 선택적으로 질화막을 형성하는 공정, 상기 질화막의 형성된 영역을 제외한 전영역상에 산화막을 형성하는 공정, 상기 질화막을 제거하는 공정, 상기 식각된 기판부위를 폴리실리콘으로 매몰시키는 공정, 열처리를 행하여 상기 폴리실리콘층내의 불순물이 기판으로 자동도핑되도록 하여 소오스 및 드레인영역을 형성하는 공정으로 이루어진다.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.
제2도에 본 발명에 의한 트랜지스터 제조방법을 공정순서에 따라 나타내었다.
먼저, 제2a도에 도시된 바와 같이 반도체기판(1)상에 게이트절연막(2)과 게이트(3) 및 게이트 캡산화막(6)을 차례로 형성한 후, 게이트전극패턴을 패터닝한 다음, 게이트측면에 절연물질로 된 측벽스페이서(7)를 형성한다. 여기서 참조부호 15는 활성영역을 한정하는 필드산화막을 나타내는 것이다.
다음에 제2b도와 같이 소오스 및 드레인영역이 되는 기판부위를 등방성식각에 의해 식각하면 게이트 측벽스페이서(7) 하부까지 식각되는 언더컷(undercut)이 일어나게 된다.
이어서 제2c도와 같은 결과물 전면에 질화막(8)을 형성한 후, 제2d도와 같이 상기 질화막을 RIE(Reactive Ion Etching)등의 방법으로 비등방성 식각하면 식각이 언더컷된 측벽스페이서(7) 하부영역에만 질화막(8)이 남게 된다.
다음에 제2e도와 같이 산화공정을 실시하여 질화막(8)이 남아있는 영역을 제외한 전영역상에 산화막(9)을 형성한 후, 제2f도와 같이 남아있는 질화막을 제거해낸다.
이어서 제2g도와같이 결과물 전면에 폴리실리콘(10)을 증착한 후, 제2h도와 같이 상기 폴리실리콘층(10)의 에치백하여 식각된 기판부위를 매몰시킨 다음 열처리를 행하여 드라이브인(Drive-in)공정을 거치면 상기 폴리실리콘층(10)내의 불순물이 기판으로 자동도핑(Auto dopping)되어 제2i도와 같이 측벽스페이서(7) 하부영역에 소오스 및 드레인영역(11)이 형성되게 된다. 상기 폴리실리콘층은 도우프드(doped) 폴리실리콘 또는 언도우프드(undoped) 폴리실리콘으로 형성할 수 있다.
이상과 같이 본 발명은 소오스 및 드레인접합영역을 산화막으로 보호함으로써 소오스 및 드레인영역의 접합누설을 극소화시킬 수 있게 되며 이에 따라 접합 브레이크다운 전압을 향상시킬 수 있어 고내압을 필요로 하는 소자에 유용하게 사용할 수 있다.
또한 접합 커패시턴스를 작게 할 수 있는 구조이므로 고속동작을 필요로 하는 소자에 이용이 가능하게 되며, 또한 폴리실리콘을 사용한 자동도핑에 의해 소오스 및 드레인을 형성하므로 얕은 접합(shallow junction)이 형성이 가능하게 되어 펀치스루(punchthrough)개선에도 기여할 수 있게 된다.

Claims (2)

  1. 반도체기판상에 게이트절연막을 개재하여 게이트를 형성하는 공정과, 상기 게이트 측면에 측벽스페이서를 형성하는 공정, 소오스 및 드레인영역이 형성될 기판부위를 등방성 식각에 의해 식각하는 공정, 상기 측벽스페이서 하부의 식각된 기판영역상에만 선택적으로 질화막을 형성하는 공정, 상기 질화막의 형성된 영역을 제외한 전영역상에 산화막을 형성하는 공정, 상기 질화막을 제거하는 공정, 상기 식각된 기판부위를 폴리실리콘으로 매몰시키는 공정, 열처리를 행하여 상기 폴리실리콘층내의 불순물이 기판으로 자동도핑되도록 하여 소오스 및 드레인영역을 형성하는 공정으로 이루어지는 것을 특징으로 하는 트랜지스터 제조방법.
  2. 제1항에 있어서, 상기 측벽스페이서의 하부의 식각된 기판영역상에만 선택적으로 질화막을 형성하는 공정은 상기 소오스 및 드레인영역이 형성될 기판부위를 등방성식각에 의해 식각하나 후, 결과물 전면에 질화막을 형성하고, 형성된 질화막을 비등방성식각함으로써 행하는 것을 특징으로 하는 트랜지스터 제조방법.
KR1019940017683A 1994-07-21 1994-07-21 트랜지스터 제조방법 KR0135147B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019940017683A KR0135147B1 (ko) 1994-07-21 1994-07-21 트랜지스터 제조방법
US08/462,042 US5620912A (en) 1994-07-21 1995-06-05 Method of manufacturing a semiconductor device using a spacer
JP7206731A JPH0846202A (ja) 1994-07-21 1995-07-21 半導体素子の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940017683A KR0135147B1 (ko) 1994-07-21 1994-07-21 트랜지스터 제조방법

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KR960006002A KR960006002A (ko) 1996-02-23
KR0135147B1 true KR0135147B1 (ko) 1998-04-22

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