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KR920007199A - 반도체기억장치 - Google Patents

반도체기억장치 Download PDF

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Publication number
KR920007199A
KR920007199A KR1019910015732A KR910015732A KR920007199A KR 920007199 A KR920007199 A KR 920007199A KR 1019910015732 A KR1019910015732 A KR 1019910015732A KR 910015732 A KR910015732 A KR 910015732A KR 920007199 A KR920007199 A KR 920007199A
Authority
KR
South Korea
Prior art keywords
bit line
memory device
semiconductor layer
semiconductor memory
memory cell
Prior art date
Application number
KR1019910015732A
Other languages
English (en)
Other versions
KR100225545B1 (ko
Inventor
도시유끼 니시하라
Original Assignee
오가 노리오
소니 가부시기가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP02414488A external-priority patent/JP3128829B2/ja
Application filed by 오가 노리오, 소니 가부시기가이샤 filed Critical 오가 노리오
Publication of KR920007199A publication Critical patent/KR920007199A/ko
Application granted granted Critical
Publication of KR100225545B1 publication Critical patent/KR100225545B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor

Landscapes

  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

내용 없음

Description

반도체기억장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명을 구현하는 반도체기억장치의 주요구성부의 평면도,
제3도는 본 발명의 반도체기억장치에 있어서 제2도의 A-A 선에 따르는 단면도.

Claims (2)

  1. 반도체층의 일측표면상에 메모리셀의 형성되고, 이 반도체층의 다른측 표면상에 비트선이 형성되는 것을 특징으로 하는 반도체기억장치.
  2. 기판상의 반도체층에 메모리셀이 형성되고, 상기 메모리셀에 전기적으로 접속되는 비트선을 절연층을 통하여 비트선시일드 도체가 이 비트선 사이에 개재된 상태로 상기 반도체층 아래에 형성되고, 상기 기판에 배면측으로 부터 상기 비트선시일드도체에 비트선시일드전력이 인가되는 것을 특징으로 하는 반도체기억장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910015732A 1990-09-10 1991-09-10 반도체기억장치 및 디램 형성방법 KR100225545B1 (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP2239418A JP3003188B2 (ja) 1990-09-10 1990-09-10 半導体メモリ及びその製造方法
JP90-239,418 1990-09-10
JP90-238,418 1990-09-10
JP90-414488 1990-12-26
JP02414488A JP3128829B2 (ja) 1990-12-26 1990-12-26 半導体メモリ装置

Publications (2)

Publication Number Publication Date
KR920007199A true KR920007199A (ko) 1992-04-28
KR100225545B1 KR100225545B1 (ko) 1999-10-15

Family

ID=26534240

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910015732A KR100225545B1 (ko) 1990-09-10 1991-09-10 반도체기억장치 및 디램 형성방법

Country Status (6)

Country Link
US (1) US5424235A (ko)
EP (1) EP0475280B1 (ko)
JP (1) JP3003188B2 (ko)
KR (1) KR100225545B1 (ko)
DE (1) DE69125671T2 (ko)
TW (1) TW200602B (ko)

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US5396452A (en) * 1993-07-02 1995-03-07 Wahlstrom; Sven E. Dynamic random access memory
US5585284A (en) * 1993-07-02 1996-12-17 Hyundai Electronics Industries Co., Ltd. Method of manufacturing a SOI DRAM
US6242772B1 (en) 1994-12-12 2001-06-05 Altera Corporation Multi-sided capacitor in an integrated circuit
KR0140657B1 (ko) * 1994-12-31 1998-06-01 김주용 반도체 소자의 제조방법
US5776789A (en) * 1995-06-05 1998-07-07 Fujitsu Limited Method for fabricating a semiconductor memory device
US6831322B2 (en) * 1995-06-05 2004-12-14 Fujitsu Limited Semiconductor memory device and method for fabricating the same
JPH0982918A (ja) * 1995-09-19 1997-03-28 Toshiba Corp 半導体記憶装置およびその製造方法
US5731217A (en) * 1996-10-08 1998-03-24 Advanced Micro Devices, Inc. Multi-level transistor fabrication method with a filled upper transistor substrate and interconnection thereto
US5882959A (en) * 1996-10-08 1999-03-16 Advanced Micro Devices, Inc. Multi-level transistor fabrication method having an inverted, upper level transistor which shares a gate conductor with a non-inverted, lower level transistor
US5872029A (en) * 1996-11-07 1999-02-16 Advanced Micro Devices, Inc. Method for forming an ultra high density inverter using a stacked transistor arrangement
US5926700A (en) 1997-05-02 1999-07-20 Advanced Micro Devices, Inc. Semiconductor fabrication having multi-level transistors and high density interconnect therebetween
US5888872A (en) 1997-06-20 1999-03-30 Advanced Micro Devices, Inc. Method for forming source drain junction areas self-aligned between a sidewall spacer and an etched lateral sidewall
US5818069A (en) 1997-06-20 1998-10-06 Advanced Micro Devices, Inc. Ultra high density series-connected transistors formed on separate elevational levels
US6423596B1 (en) * 1998-09-29 2002-07-23 Texas Instruments Incorporated Method for two-sided fabrication of a memory array
US6465331B1 (en) * 2000-08-31 2002-10-15 Micron Technology, Inc. DRAM fabricated on a silicon-on-insulator (SOI) substrate having bi-level digit lines
DE10105725B4 (de) * 2001-02-08 2008-11-13 Infineon Technologies Ag Halbleiterchip mit einem Substrat, einer integrierten Schaltung und einer Abschirmvorrichtung
US6800892B2 (en) * 2003-02-10 2004-10-05 Micron Technology, Inc. Memory devices, and electronic systems comprising memory devices
US6717839B1 (en) 2003-03-31 2004-04-06 Ramtron International Corporation Bit-line shielding method for ferroelectric memories
KR100615085B1 (ko) 2004-01-12 2006-08-22 삼성전자주식회사 노드 콘택 구조체들, 이를 채택하는 반도체소자들, 이를채택하는 에스램 셀들 및 이를 제조하는 방법들
US7858468B2 (en) 2008-10-30 2010-12-28 Micron Technology, Inc. Memory devices and formation methods
FR2955200B1 (fr) 2010-01-14 2012-07-20 Soitec Silicon On Insulator Dispositif, et son procede de fabrication, disposant d'un contact entre regions semi-conductrices a travers une couche isolante enterree
CN101976681B (zh) * 2010-08-27 2012-09-26 东南大学 一种提高电流密度的p型绝缘体上硅横向器件及其制备工艺
TWI657565B (zh) 2011-01-14 2019-04-21 日商半導體能源研究所股份有限公司 半導體記憶裝置
US8686486B2 (en) * 2011-03-31 2014-04-01 Semiconductor Energy Laboratory Co., Ltd. Memory device
KR102616259B1 (ko) * 2022-05-06 2023-12-20 (주)서연인테크 독립형 푸드 테이블

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US3755012A (en) * 1971-03-19 1973-08-28 Motorola Inc Controlled anisotropic etching process for fabricating dielectrically isolated field effect transistor
US4501060A (en) * 1983-01-24 1985-02-26 At&T Bell Laboratories Dielectrically isolated semiconductor devices
EP0164829B1 (en) * 1984-04-19 1988-09-28 Nippon Telegraph And Telephone Corporation Semiconductor memory device and method of manufacturing the same
US4763180A (en) * 1986-12-22 1988-08-09 International Business Machines Corporation Method and structure for a high density VMOS dynamic ram array
DE3851649T2 (de) * 1987-03-20 1995-05-04 Nippon Electric Co Aus einer Vielzahl von Eintransistorzellen bestehende dynamische Speichervorrichtung mit wahlfreiem Zugriff.
JPH0795568B2 (ja) * 1987-04-27 1995-10-11 日本電気株式会社 半導体記憶装置
JP2510865B2 (ja) * 1987-08-20 1996-06-26 日本電信電話株式会社 無線印刷電信における一括呼出方法
JP2590171B2 (ja) * 1988-01-08 1997-03-12 株式会社日立製作所 半導体記憶装置
JPH0235771A (ja) * 1988-07-26 1990-02-06 Nec Corp 半導体記憶装置
JP2743391B2 (ja) * 1988-08-25 1998-04-22 ソニー株式会社 半導体メモリの製造方法
US5192704A (en) * 1989-06-30 1993-03-09 Texas Instruments Incorporated Method and apparatus for a filament channel pass gate ferroelectric capacitor memory cell

Also Published As

Publication number Publication date
US5424235A (en) 1995-06-13
JP3003188B2 (ja) 2000-01-24
EP0475280B1 (en) 1997-04-16
JPH04118967A (ja) 1992-04-20
TW200602B (ko) 1993-02-21
EP0475280A1 (en) 1992-03-18
DE69125671T2 (de) 1997-11-27
KR100225545B1 (ko) 1999-10-15
DE69125671D1 (de) 1997-05-22

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