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FR2955200B1 - Dispositif, et son procede de fabrication, disposant d'un contact entre regions semi-conductrices a travers une couche isolante enterree - Google Patents

Dispositif, et son procede de fabrication, disposant d'un contact entre regions semi-conductrices a travers une couche isolante enterree

Info

Publication number
FR2955200B1
FR2955200B1 FR1050244A FR1050244A FR2955200B1 FR 2955200 B1 FR2955200 B1 FR 2955200B1 FR 1050244 A FR1050244 A FR 1050244A FR 1050244 A FR1050244 A FR 1050244A FR 2955200 B1 FR2955200 B1 FR 2955200B1
Authority
FR
France
Prior art keywords
insulated
manufacturing
contact
semiconductor regions
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1050244A
Other languages
English (en)
Other versions
FR2955200A1 (fr
Inventor
Carlos Mazure
Richard Ferrant
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Priority to FR1050244A priority Critical patent/FR2955200B1/fr
Priority to US12/984,466 priority patent/US9490264B2/en
Priority to KR1020110003089A priority patent/KR101277328B1/ko
Priority to JP2011004142A priority patent/JP5543383B2/ja
Priority to TW100101081A priority patent/TWI455270B/zh
Priority to CN201110038036.5A priority patent/CN102184927B/zh
Priority to SG2011002458A priority patent/SG173270A1/en
Priority to EP11150845A priority patent/EP2355143A1/fr
Publication of FR2955200A1 publication Critical patent/FR2955200A1/fr
Application granted granted Critical
Publication of FR2955200B1 publication Critical patent/FR2955200B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D48/00—Individual devices not covered by groups H10D1/00 - H10D44/00
    • H10D48/30—Devices controlled by electric currents or voltages
    • H10D48/32—Devices controlled by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H10D48/34—Bipolar devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/40—Vertical BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6727—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having source or drain regions connected to bulk conducting substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/711—Insulated-gate field-effect transistors [IGFET] having floating bodies

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Bipolar Transistors (AREA)
  • Thin Film Transistor (AREA)
  • Element Separation (AREA)
FR1050244A 2010-01-14 2010-01-14 Dispositif, et son procede de fabrication, disposant d'un contact entre regions semi-conductrices a travers une couche isolante enterree Active FR2955200B1 (fr)

Priority Applications (8)

Application Number Priority Date Filing Date Title
FR1050244A FR2955200B1 (fr) 2010-01-14 2010-01-14 Dispositif, et son procede de fabrication, disposant d'un contact entre regions semi-conductrices a travers une couche isolante enterree
US12/984,466 US9490264B2 (en) 2010-01-14 2011-01-04 Device having a contact between semiconductor regions through a buried insulating layer, and process for fabricating said device
JP2011004142A JP5543383B2 (ja) 2010-01-14 2011-01-12 埋め込み絶縁層を貫いて半導体層間に接触を有するデバイス、およびこのデバイスの製造プロセス
TW100101081A TWI455270B (zh) 2010-01-14 2011-01-12 具有穿過埋入式絕緣層在半導體區域間的接點之裝置及其製造方法
KR1020110003089A KR101277328B1 (ko) 2010-01-14 2011-01-12 매립 절연층을 통하여 반도체 영역들 사이에 콘택을 가지는 소자 및 소자의 제조 방법
CN201110038036.5A CN102184927B (zh) 2010-01-14 2011-01-12 具有贯穿隐埋绝缘层的区域间触点的器件及其制造方法
SG2011002458A SG173270A1 (en) 2010-01-14 2011-01-13 Device having a contact between semiconductor regions through a buried insulating layer, and process for fabricating said device
EP11150845A EP2355143A1 (fr) 2010-01-14 2011-01-13 Dispositif doté d'un contact entre les régions semi-conductrices à travers une couche isolante enterrée et procédé de fabrication dudit dispositif

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1050244A FR2955200B1 (fr) 2010-01-14 2010-01-14 Dispositif, et son procede de fabrication, disposant d'un contact entre regions semi-conductrices a travers une couche isolante enterree

Publications (2)

Publication Number Publication Date
FR2955200A1 FR2955200A1 (fr) 2011-07-15
FR2955200B1 true FR2955200B1 (fr) 2012-07-20

Family

ID=42342015

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1050244A Active FR2955200B1 (fr) 2010-01-14 2010-01-14 Dispositif, et son procede de fabrication, disposant d'un contact entre regions semi-conductrices a travers une couche isolante enterree

Country Status (8)

Country Link
US (1) US9490264B2 (fr)
EP (1) EP2355143A1 (fr)
JP (1) JP5543383B2 (fr)
KR (1) KR101277328B1 (fr)
CN (1) CN102184927B (fr)
FR (1) FR2955200B1 (fr)
SG (1) SG173270A1 (fr)
TW (1) TWI455270B (fr)

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FR3095891B1 (fr) 2019-05-09 2023-01-13 St Microelectronics Sa Circuit électronique
KR102690949B1 (ko) 2019-06-14 2024-08-02 에스케이하이닉스 주식회사 반도체 장치 및 그 제조 방법
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US11894450B2 (en) * 2021-11-18 2024-02-06 Globalfoundries U.S. Inc. Lateral bipolar transistor with emitter and collector regions including portions within In-insulator layer cavities and method

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TWI455270B (zh) 2014-10-01
CN102184927A (zh) 2011-09-14
JP5543383B2 (ja) 2014-07-09
FR2955200A1 (fr) 2011-07-15
US20110169090A1 (en) 2011-07-14
US9490264B2 (en) 2016-11-08
TW201135894A (en) 2011-10-16
SG173270A1 (en) 2011-08-29
EP2355143A1 (fr) 2011-08-10

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