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KR910017743A - 레벨변환회로 - Google Patents

레벨변환회로 Download PDF

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Publication number
KR910017743A
KR910017743A KR1019910004844A KR910004844A KR910017743A KR 910017743 A KR910017743 A KR 910017743A KR 1019910004844 A KR1019910004844 A KR 1019910004844A KR 910004844 A KR910004844 A KR 910004844A KR 910017743 A KR910017743 A KR 910017743A
Authority
KR
South Korea
Prior art keywords
output node
potential
terminal
transistor
conversion circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
KR1019910004844A
Other languages
English (en)
Other versions
KR940010675B1 (ko
Inventor
쇼죠 닛타
야스히로 스기모토
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 아오이 죠이치, 가부시키가이샤 도시바 filed Critical 아오이 죠이치
Publication of KR910017743A publication Critical patent/KR910017743A/ko
Application granted granted Critical
Publication of KR940010675B1 publication Critical patent/KR940010675B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/18—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using galvano-magnetic devices, e.g. Hall-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/018—Coupling arrangements; Interface arrangements using bipolar transistors only
    • H03K19/01806—Interface arrangements
    • H03K19/01812—Interface arrangements with at least one differential stage

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

내용 없음

Description

레벨변환회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1도는 본 발명의 1실시예에 따른 구성의 회로도, 제 2도는 본 발명의 레벨변환회로를 이용하여 TTL출력회로에 접속시켜 구체적인 구성의 회로도.

Claims (1)

  1. 입력신호에 의해 부전압으로 동작하는 차동쌍 트랜지스터(Q1,Q2)로 구성된 전류절환수단과, 상기 차동쌍의 한쪽 트랜지스터의 콜렉터가 접속되는 제 1 전위(G ND), 상기 차동쌍의 다른쪽 트랜지스터의 콜렉터에 설치되어 상기 전류절환수단에 의해 전위가 절환되는 제 1 출력노오드(V2), 이 제 1 출력노오드(V2)와 제 1 전위(GND)간에 끼워진 제 1 부하소자(R2), 한쪽 단자에 제 2 전위(VCC)를 인가받고 제어단자에 제 3 전위(VBB)를 인가받음으로써 다른쪽 단자에 일정한 전위를 공급하는 레벨전환용 트랜지스터(Q4), 이 레벨변환용 트랜지스터(Q4)의 다른쪽 단자에 제 2 출력노오드(V1), 상기 제 1 출력노오드(V2)와 제 2 출력노오드(V1)간에 끼워진 제 2 부하소자(R3)를 구비하여 구성된 것을 특징으로 하는 레벨변환회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910004844A 1990-03-30 1991-03-28 레벨변환회로 Expired - Fee Related KR940010675B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2083920A JPH0622325B2 (ja) 1990-03-30 1990-03-30 レベル変換回路
JP2-83920 1990-03-30

Publications (2)

Publication Number Publication Date
KR910017743A true KR910017743A (ko) 1991-11-05
KR940010675B1 KR940010675B1 (ko) 1994-10-24

Family

ID=13816041

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910004844A Expired - Fee Related KR940010675B1 (ko) 1990-03-30 1991-03-28 레벨변환회로

Country Status (5)

Country Link
US (1) US5081376A (ko)
EP (1) EP0449208B1 (ko)
JP (1) JPH0622325B2 (ko)
KR (1) KR940010675B1 (ko)
DE (1) DE69119283T2 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8806675B2 (en) 2012-11-01 2014-08-19 Jeh-kun Lah Cot

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2528028B2 (ja) * 1990-08-22 1996-08-28 三菱電機株式会社 レベル変換回路
DE4225750A1 (de) * 1992-08-04 1994-02-10 Siemens Nixdorf Inf Syst Hochintegrierte Schaltkreise
US5481216A (en) * 1994-05-31 1996-01-02 National Semiconductor Corporation Transistor drive circuit with shunt transistor saturation control
DE202010006624U1 (de) 2010-05-10 2010-08-05 Manitowoc Crane Group France Sas Kranausleger, insbesondere Mobilkranausleger, mit vorgespannten Zugelementen

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4536665A (en) * 1982-12-27 1985-08-20 The Grass Valley Group, Inc. Circuit for converting two balanced ECL level signals into an inverted TTL level signal
JPS6157118A (ja) * 1984-08-29 1986-03-24 Toshiba Corp レベル変換回路
JPH0683053B2 (ja) * 1987-10-30 1994-10-19 日本電気株式会社 レベル変換回路
US4870301A (en) * 1988-09-06 1989-09-26 Motorola, Inc. Differential emitter-coupled-logic bus driver
US4835455A (en) * 1988-09-15 1989-05-30 Honeywell Inc. Reference voltage generator
US4996452A (en) * 1989-11-15 1991-02-26 National Semiconductor Corporation ECL/TTL tristate buffer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8806675B2 (en) 2012-11-01 2014-08-19 Jeh-kun Lah Cot

Also Published As

Publication number Publication date
JPH03283811A (ja) 1991-12-13
EP0449208A2 (en) 1991-10-02
DE69119283D1 (de) 1996-06-13
EP0449208A3 (en) 1991-12-04
JPH0622325B2 (ja) 1994-03-23
KR940010675B1 (ko) 1994-10-24
US5081376A (en) 1992-01-14
EP0449208B1 (en) 1996-05-08
DE69119283T2 (de) 1996-10-10

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