[go: up one dir, main page]

KR890009068A - 레벨변환회로 - Google Patents

레벨변환회로 Download PDF

Info

Publication number
KR890009068A
KR890009068A KR1019880015349A KR880015349A KR890009068A KR 890009068 A KR890009068 A KR 890009068A KR 1019880015349 A KR1019880015349 A KR 1019880015349A KR 880015349 A KR880015349 A KR 880015349A KR 890009068 A KR890009068 A KR 890009068A
Authority
KR
South Korea
Prior art keywords
level conversion
bias voltage
circuit
conversion circuit
input
Prior art date
Application number
KR1019880015349A
Other languages
English (en)
Other versions
KR920003597B1 (ko
Inventor
데츠야 이다
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 아오이 죠이치, 가부시키가이샤 도시바 filed Critical 아오이 죠이치
Publication of KR890009068A publication Critical patent/KR890009068A/ko
Application granted granted Critical
Publication of KR920003597B1 publication Critical patent/KR920003597B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
    • H03K19/09—Resistor-transistor logic

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

내용 없음

Description

레벨변환회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 ECL-CMOS 레벨변환회로의 한 실시예를 나타낸 회로도.
제2도는 본 발명의 다른 실시예를 나타낸 회로도.

Claims (3)

  1. ECL회로(1)의 한 출력노드와 증폭동작할 수 있도록 입력바이어스전압이 가해진 CMOS인버터회로(11;17)의 입력노드 사이를 결합용량(3;13)을 매개하여 접속시켜서 이루어진 것을 특징으로 하는 레벨변환기.
  2. 제1항에 있어서, 상기 CMOS인버터회로(11)의 출력노드와 입력노드 사이에 자기바이어스공급용 저항소자(15)를 접속시켜 입력바이어스전압을 부여하도록 된 것을 특징으로 하는 레벨변환회로.
  3. 제1항에 있어서, 상기 CMOS인버터회로(17)에 입력바이어스 전압을 공급하기 위한 바이어스전압발생회로(18,16)가 CMOS회로(2)내에 설치된 것을 특징으로 하는 레벨변환회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019880015349A 1987-11-26 1988-11-22 레벨변환회로 KR920003597B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP62-297961 1987-11-26
JP62297961A JPH01138813A (ja) 1987-11-26 1987-11-26 Ｅｃｌ―ｃｍｏｓレベル変換回路

Publications (2)

Publication Number Publication Date
KR890009068A true KR890009068A (ko) 1989-07-15
KR920003597B1 KR920003597B1 (ko) 1992-05-04

Family

ID=17853330

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019880015349A KR920003597B1 (ko) 1987-11-26 1988-11-22 레벨변환회로

Country Status (4)

Country Link
US (1) US4906871A (ko)
EP (1) EP0318018A3 (ko)
JP (1) JPH01138813A (ko)
KR (1) KR920003597B1 (ko)

Families Citing this family (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0353508B1 (de) * 1988-07-22 1994-09-21 Siemens Aktiengesellschaft ECL-CMOS-Wandler
JPH0738580B2 (ja) * 1988-09-30 1995-04-26 日本電気株式会社 エミッタ結合論理回路
US5051625B1 (en) * 1988-10-28 1993-11-16 Nissan Motor Co.,Ltd. Output buffer circuits for reducing noise
DE3904901A1 (de) * 1989-02-17 1990-08-23 Texas Instruments Deutschland Integrierte gegentakt-ausgangsstufe
US4958132A (en) * 1989-05-09 1990-09-18 Advanced Micro Devices, Inc. Complementary metal-oxide-semiconductor translator
US4968905A (en) * 1989-08-25 1990-11-06 Ncr Corporation Temperature compensated high speed ECL-to-CMOS logic level translator
US5036226A (en) * 1989-10-23 1991-07-30 Ncr Corporation Signal converting circuit
US5164616A (en) * 1989-12-29 1992-11-17 Xerox Corporation Integrated sample and hold circuit with feedback circuit to increase storage time
US4998028A (en) * 1990-01-26 1991-03-05 International Business Machines Corp. High speed CMOS logic device for providing ECL compatible logic levels
US5038057A (en) * 1990-05-29 1991-08-06 Motorola, Inc. ECL to CMOS logic translator
US5182473A (en) * 1990-07-31 1993-01-26 Cray Research, Inc. Emitter emitter logic (EEL) and emitter collector dotted logic (ECDL) families
US5148059A (en) * 1991-04-02 1992-09-15 International Business Machines Corporation CMOS and ECL logic circuit requiring no interface circuitry
US5254887A (en) * 1991-06-27 1993-10-19 Nec Corporation ECL to BiCMIS level converter
KR940001816B1 (ko) * 1991-07-26 1994-03-09 삼성전자 주식회사 슬루우레이트 스피드엎 회로
US5202594A (en) * 1992-02-04 1993-04-13 Motorola, Inc. Low power level converter
US5319252A (en) * 1992-11-05 1994-06-07 Xilinx, Inc. Load programmable output buffer
JPH0746098A (ja) * 1993-08-03 1995-02-14 Nec Corp 遅延回路
US5682108A (en) * 1995-05-17 1997-10-28 Integrated Device Technology, Inc. High speed level translator
CN1183587C (zh) * 1996-04-08 2005-01-05 德克萨斯仪器股份有限公司 用于把两个集成电路直流上相互隔离的方法和设备
US5754059A (en) * 1997-01-14 1998-05-19 International Business Machines Corporation Multi-stage ECL-to-CMOS converter with wide dynamic range and high symmetry
US5973508A (en) * 1997-05-21 1999-10-26 International Business Machines Corp. Voltage translation circuit for mixed voltage applications
TW381385B (en) * 1997-08-20 2000-02-01 Advantest Corp Signal transmission circuit, CMOS semiconductor device and circuit board
DE19801994C1 (de) * 1998-01-20 1999-08-26 Siemens Ag Referenzspannungsgenerator
US6252421B1 (en) * 1998-07-27 2001-06-26 Texas Instruments Incorporated Differential, high speed, ECL to CMOS converter
JP3609977B2 (ja) * 1999-07-15 2005-01-12 シャープ株式会社 レベルシフト回路および画像表示装置
DE19949843C2 (de) * 1999-10-15 2002-03-21 Siemens Ag Anordnung zur Pegelumsetzung von hochfrequenten Niedervoltsignalen
WO2001047111A2 (en) * 1999-12-21 2001-06-28 Teradyne, Inc. Capacitively coupled re-referencing circuit with positive feedback
EP1164699A1 (de) * 2000-06-14 2001-12-19 Infineon Technologies AG Schaltungsanordnung zur Umsetzung von Logikpegeln
US6621144B2 (en) * 2001-04-05 2003-09-16 Koninklijke Philips Electronics N.V. Data receiver gain enhancement
JP3596540B2 (ja) * 2001-06-26 2004-12-02 セイコーエプソン株式会社 レベルシフタ及びそれを用いた電気光学装置
US6507220B1 (en) * 2001-09-28 2003-01-14 Xilinx, Inc. Correction of duty-cycle distortion in communications and other circuits
KR100487947B1 (ko) * 2002-11-22 2005-05-06 삼성전자주식회사 클럭 스퀘어 회로
US7176720B1 (en) * 2003-03-14 2007-02-13 Cypress Semiconductor Corp. Low duty cycle distortion differential to CMOS translator
JP2005266043A (ja) * 2004-03-17 2005-09-29 Hitachi Displays Ltd 画像表示パネルおよびレベルシフト回路
US7064598B2 (en) * 2004-03-25 2006-06-20 Silicon Laboratories, Inc. Radio frequency CMOS buffer circuit and method
US7979036B2 (en) * 2004-12-30 2011-07-12 Agency For Science, Technology And Research Fully integrated ultra wideband transmitter circuits and systems
TW200715092A (en) * 2005-10-06 2007-04-16 Denmos Technology Inc Current bias circuit and current bias start-up circuit thereof
JP2007259122A (ja) * 2006-03-23 2007-10-04 Renesas Technology Corp 通信用半導体集積回路
US8729954B2 (en) * 2011-08-31 2014-05-20 Freescale Semiconductor, Inc. MOFSET mismatch characterization circuit
US9111894B2 (en) 2011-08-31 2015-08-18 Freescale Semiconductor, Inc. MOFSET mismatch characterization circuit
US9270273B2 (en) * 2011-10-28 2016-02-23 Texas Instruments Incorporated Level shifter
US8680901B2 (en) * 2012-08-06 2014-03-25 Texas Instruments Incorporated Power on reset generation circuits in integrated circuits
US9312858B2 (en) 2014-06-02 2016-04-12 International Business Machines Corporation Level shifter for a time-varying input

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4029971A (en) * 1976-02-13 1977-06-14 Rca Corporation Tri-state logic circuit
GB1564671A (en) * 1978-04-12 1980-04-10 Hughes Microelectronics Ltd Comparator
EP0088291B1 (en) * 1982-02-26 1985-07-10 Kabushiki Kaisha Toshiba Mos switch circuit
US4645951A (en) * 1983-08-31 1987-02-24 Hitachi, Ltd. Semiconductor integrated circuit having a C-MOS internal logic block and an output buffer for providing ECL level signals
JPS60105320A (ja) * 1983-11-14 1985-06-10 Nippon Telegr & Teleph Corp <Ntt> レベル変換回路
JPH0773205B2 (ja) * 1983-12-20 1995-08-02 株式会社日立製作所 レベル変換回路
JPS60194614A (ja) * 1984-03-16 1985-10-03 Hitachi Ltd インタ−フエ−ス回路
JPS6119226A (ja) * 1984-07-05 1986-01-28 Hitachi Ltd レベル変換回路
DE3582802D1 (de) * 1985-10-15 1991-06-13 Ibm Leseverstaerker zur verstaerkung von signalen auf einer vorgespannten leitung.
US4703198A (en) * 1986-07-07 1987-10-27 Ford Motor Company Bi-directional data transfer circuit that is directionally responsive to the impedance condition of an associated input/output port of a microcomputer
US4754165A (en) * 1986-07-29 1988-06-28 Hewlett-Packard Company Static MOS super buffer latch

Also Published As

Publication number Publication date
JPH01138813A (ja) 1989-05-31
US4906871A (en) 1990-03-06
EP0318018A3 (en) 1990-05-02
KR920003597B1 (ko) 1992-05-04
EP0318018A2 (en) 1989-05-31

Similar Documents

Publication Publication Date Title
KR890009068A (ko) 레벨변환회로
KR920000072A (ko) 반도체 집적회로
KR840008097A (ko) 기판 바이어스 전압제어회로 및 방법
KR930003556A (ko) 점진적 턴-온 특성의 cmos 구동기
KR840008075A (ko) 스위칭 제어신호 발생용 반도체 집적회로장치
KR940010530A (ko) 에미터 결합 로직(ECL)-바이폴라 상보형 금속 산화물 반도체(BiCMOS)/상보형금속 산화물 반도체(CMOS) 트랜슬레이터
KR890001293A (ko) 출력 회로
KR880008518A (ko) 필터장치
KR870009528A (ko) 버퍼회로
KR860000719A (ko) 상보형(相補型)Bi-MIS 게이트회로
KR900013509A (ko) 온도보상회로
KR890011209A (ko) 듀일 슬로프 파형 발생회로
KR930005365A (ko) 차동, 고속, 저전력의 에미터 정합논리 대상보형 금속산화막반도체(ecl-cmos)변환기
KR890001274A (ko) 전류미러회로
KR880012009A (ko) BiMOS 논리회로
KR910016077A (ko) 반도체집적회로
KR920015364A (ko) 출력 버퍼회로
KR960009360A (ko) 전압/전류 변환회로
KR880008553A (ko) 세라믹 필터에 변조기를 결합시키기 위한 집적결합회로
KR910007238A (ko) 증폭 회로
KR830006990A (ko) 정전류 회로
KR890013767A (ko) biCMOS 인터페이스 회로
KR880005741A (ko) 증폭기
KR910021022A (ko) 히스테리시스회로
KR910010705A (ko) 반도체집적회로

Legal Events

Date Code Title Description
A201 Request for examination
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19881122

PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 19881122

Comment text: Request for Examination of Application

PG1501 Laying open of application
E601 Decision to refuse application
E902 Notification of reason for refusal
PE0601 Decision on rejection of patent

Patent event date: 19910729

Comment text: Decision to Refuse Application

Patent event code: PE06012S01D

PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 19910729

Patent event code: PE09021S01D

J2X1 Appeal (before the patent court)

Free format text: APPEAL AGAINST DECISION TO DECLINE REFUSAL

PJ2001 Appeal

Appeal kind category: Appeal against decision to decline refusal

Decision date: 19920731

Appeal identifier: 1992201000146

Request date: 19920122

G160 Decision to publish patent application
PG1605 Publication of application before grant of patent

Comment text: Decision on Publication of Application

Patent event code: PG16051S01I

Patent event date: 19920404

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

Patent event code: PE07011S01D

Comment text: Decision to Grant Registration

Patent event date: 19920731

GRNT Written decision to grant
PR0701 Registration of establishment

Comment text: Registration of Establishment

Patent event date: 19921008

Patent event code: PR07011E01D

PR1002 Payment of registration fee

Payment date: 19921008

End annual number: 3

Start annual number: 1

PR1001 Payment of annual fee

Payment date: 19950503

Start annual number: 4

End annual number: 4

PR1001 Payment of annual fee

Payment date: 19960502

Start annual number: 5

End annual number: 5

PR1001 Payment of annual fee

Payment date: 19970503

Start annual number: 6

End annual number: 6

PR1001 Payment of annual fee

Payment date: 19971229

Start annual number: 7

End annual number: 7

PR1001 Payment of annual fee

Payment date: 19990417

Start annual number: 8

End annual number: 8

PR1001 Payment of annual fee

Payment date: 20000428

Start annual number: 9

End annual number: 9

PR1001 Payment of annual fee

Payment date: 20010427

Start annual number: 10

End annual number: 10

PR1001 Payment of annual fee

Payment date: 20020430

Start annual number: 11

End annual number: 11

FPAY Annual fee payment

Payment date: 20030430

Year of fee payment: 12

PR1001 Payment of annual fee

Payment date: 20030430

Start annual number: 12

End annual number: 12

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee