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KR910010331A - 다수의 프로그램가능한 논리 제어기 사이의 통신 방법 - Google Patents

다수의 프로그램가능한 논리 제어기 사이의 통신 방법 Download PDF

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Publication number
KR910010331A
KR910010331A KR1019900017891A KR900017891A KR910010331A KR 910010331 A KR910010331 A KR 910010331A KR 1019900017891 A KR1019900017891 A KR 1019900017891A KR 900017891 A KR900017891 A KR 900017891A KR 910010331 A KR910010331 A KR 910010331A
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South Korea
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message
plc
data
bus
plcs
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KR1019900017891A
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KR930007048B1 (ko
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화이트 섹스톤 다니엘
무어 레이시 앤드류
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도날드 알. 댄서
제 파넉 오토메이션 노스 아메리카, 인크.
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
    • G05B19/052—Linking several PLC's
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Software Systems (AREA)
  • Small-Scale Networks (AREA)
  • Communication Control (AREA)
  • Information Transfer Systems (AREA)
  • Multi Processors (AREA)
  • Programmable Controllers (AREA)

Abstract

내용 없음.

Description

다수의 프로그램가능한 논리 제어기 사이의 통신 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명의 통신 방법이 실행되는 다수의 프로그램가능한 논리제어기를 함께 연결하기 위한 배열의 블럭도.
제3도는 본 발명의 통신 방법 및 프로토콜의 시간선 표시도(time line representation).
제5도는 본 발명에 의해 사용된 슬레이브 PLC에 적용되는 본 발명의 방법을 도시한 플로우챠트.

Claims (2)

  1. 공통 통신 버스에 연결된 다수의 프로그램가능한 논리 제어기(PLC) 사이의 통신 방법에 있어서, 다수의 PLC중의 선택된 한 PLC로 부터 메세지가 전송되는 상기 PLC중의 다른 한 PLC를 식별하기 위해 코드화된 신호를 전송하는 단계, 승인 신호가 상기 PLC중의 다른 한 PLC로 부터 전송될 때까지 메세지의 전송을 지연하는 단계, 승인 신호를 수신하면 상기 PLC중의 다른 한 PLC로 전송될 후속적인 다음 메세지의 길이를 식별하는 데이타를 포함하는 기선택된 길이의 우편함 메세지를 전송하는 단계, 각각의 후속적인 다음 메세지가 바로 뒤따라오는 임의의 메세지의 길이를 식별하는 상기 PLC중의 다른 한 PLC에 상기 후속적인 다음 메세지를 전송하는 단계, 및 상기 PLC중의 다른 한 PLC내의 DMA 제어기에 의해 후속적인 메세지에 포함된 임의의 데이타를 다른 한 PLC의 메모리로 직접 전송하는 단계를 포함하는 것을 특징으로 하는 방법.
  2. 프로그램가능한 논리 제어기(PLC)로 부터 공통 통신 버스 및 PLC에 연결된 모든 슬레이브 장치를 기본으로 하는 다수의 마이크로컴퓨터 중에서 선택된 것으로 데이타를 전송하기 위한 방법에 있어서, 상기 각각의 슬레이브 장치가 상기 버스에 연결된 직렬 포트를 갖고, DMA 제어기, 메모리, 및 중앙 처리 장치(PLC)를 더 포함하고, 중단 문자에 의해 인터럽트될 수 있는 상기 슬레이브 장치로 기결정된 중단 문자를 위해 상기 버스를 모니터하는 단계, 상기 슬레이브 장치를 인터럽트하기 위해 상기 버스로 중잔문자를 상기 PLC에 의해 전송하는 단계, 상기 슬레이브 장치중에서 선택된 것을 상기 PLC에 의해 주소 지정하는 단계, 데이타를 포함하고, 상기 선택된 슬레이브 장치로 전송될 다음 메세지의 길이를 기재한 메세지 길이 정보를 더 포함하는 제1메세지를 상기 PLC에 의해 상기 버스로 전송하는 단계, 데이타를 포함하고, 상기 선택된 슬레이브 장치로 전송될 다른 다음 메세지의 길이를 기재한 메세지 길이 정보를 더 포함하는 다음 메세지를 상기 PLC에 의해 상기 버스로 전송하는 단계, 전송될 데이타가 상기 슬레이브 장치로 모두 전송될때까지 상기 다음 메세지를 전송하는 단계를 반복하는 단계, 및 상기 제1메세지내의 데이타 및 임의의 다음 메세지를 상기 선택된 슬레이브 장치내의 DMA 제어기에 의해 선택된 슬레이브 장치로 부터 메모리로 직접 전송하는 단계를 포함하는 것을 특징으로 하는 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900017891A 1989-11-07 1990-11-06 다수의 프로그램가능한 논리 제어기 사이의 통신 방법 KR930007048B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US433,092 1989-11-07
US07/433,092 US5072374A (en) 1989-11-07 1989-11-07 Method for communicating among a plurality of programmable logic controllers each having a dma controller
US433092 1989-11-07

Publications (2)

Publication Number Publication Date
KR910010331A true KR910010331A (ko) 1991-06-29
KR930007048B1 KR930007048B1 (ko) 1993-07-26

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Country Status (6)

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US (1) US5072374A (ko)
EP (1) EP0427502B1 (ko)
JP (1) JPH0758984B2 (ko)
KR (1) KR930007048B1 (ko)
CA (1) CA2027334C (ko)
DE (1) DE69020306T2 (ko)

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Also Published As

Publication number Publication date
JPH0758984B2 (ja) 1995-06-21
DE69020306D1 (de) 1995-07-27
JPH03175560A (ja) 1991-07-30
US5072374A (en) 1991-12-10
CA2027334A1 (en) 1991-05-08
EP0427502B1 (en) 1995-06-21
EP0427502A3 (en) 1991-08-28
EP0427502A2 (en) 1991-05-15
DE69020306T2 (de) 1996-03-14
KR930007048B1 (ko) 1993-07-26
CA2027334C (en) 2000-06-20

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