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KR900008644A - 반도체 장치 제조 방법 - Google Patents

반도체 장치 제조 방법

Info

Publication number
KR900008644A
KR900008644A KR1019890016671A KR890016671A KR900008644A KR 900008644 A KR900008644 A KR 900008644A KR 1019890016671 A KR1019890016671 A KR 1019890016671A KR 890016671 A KR890016671 A KR 890016671A KR 900008644 A KR900008644 A KR 900008644A
Authority
KR
South Korea
Prior art keywords
semiconductor device
device manufacturing
manufacturing
semiconductor
Prior art date
Application number
KR1019890016671A
Other languages
English (en)
Other versions
KR940010510B1 (ko
Inventor
신 이찌로 아리까와
히로아끼 무라까미
Original Assignee
세이꼬 엡슨 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP63294000A external-priority patent/JPH02139934A/ja
Priority claimed from JP1094120A external-priority patent/JP2748530B2/ja
Priority claimed from JP1125825A external-priority patent/JP2874184B2/ja
Application filed by 세이꼬 엡슨 가부시끼가이샤 filed Critical 세이꼬 엡슨 가부시끼가이샤
Publication of KR900008644A publication Critical patent/KR900008644A/ko
Application granted granted Critical
Publication of KR940010510B1 publication Critical patent/KR940010510B1/ko

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
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    • Y10S148/00Metal treatment
    • Y10S148/131Reactive ion etching rie

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1019890016671A 1988-11-21 1989-11-17 반도체 장치 제조 방법 KR940010510B1 (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP88-294000 1988-11-21
JP63294000A JPH02139934A (ja) 1988-11-21 1988-11-21 集積回路の製造方法
JP1094120A JP2748530B2 (ja) 1989-04-13 1989-04-13 半導体装置の製造方法
JP1125825A JP2874184B2 (ja) 1989-05-19 1989-05-19 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
KR900008644A true KR900008644A (ko) 1990-06-03
KR940010510B1 KR940010510B1 (ko) 1994-10-24

Family

ID=27307484

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890016671A KR940010510B1 (ko) 1988-11-21 1989-11-17 반도체 장치 제조 방법

Country Status (2)

Country Link
US (1) US5298459A (ko)
KR (1) KR940010510B1 (ko)

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US5376584A (en) * 1992-12-31 1994-12-27 International Business Machines Corporation Process of making pad structure for solder ball limiting metallurgy having reduced edge stress
US5367195A (en) * 1993-01-08 1994-11-22 International Business Machines Corporation Structure and method for a superbarrier to prevent diffusion between a noble and a non-noble metal
KR960016007B1 (ko) * 1993-02-08 1996-11-25 삼성전자 주식회사 반도체 칩 범프의 제조방법
KR950004464A (ko) * 1993-07-15 1995-02-18 김광호 칩 범프의 제조방법
US5384283A (en) * 1993-12-10 1995-01-24 International Business Machines Corporation Resist protection of ball limiting metal during etch process
US5665639A (en) * 1994-02-23 1997-09-09 Cypress Semiconductor Corp. Process for manufacturing a semiconductor device bump electrode using a rapid thermal anneal
US5503286A (en) * 1994-06-28 1996-04-02 International Business Machines Corporation Electroplated solder terminal
US5494856A (en) * 1994-10-18 1996-02-27 International Business Machines Corporation Apparatus and method for creating detachable solder connections
US5587336A (en) * 1994-12-09 1996-12-24 Vlsi Technology Bump formation on yielded semiconductor dies
TW253856B (en) * 1994-12-13 1995-08-11 At & T Corp Method of solder bonding, and article produced by the method
US5559056A (en) * 1995-01-13 1996-09-24 National Semiconductor Corporation Method and apparatus for capping metallization layer
DE69617928T2 (de) * 1995-03-20 2002-07-18 Unitive International Ltd., Curacao Löthöcker-herstellungsverfahren und strukturen mit einer titan-sperrschicht
US5901431A (en) * 1995-06-07 1999-05-11 International Business Machines Corporation Method of fabricating a thin film inductive head having a second pole piece having a mushroom yoke portion
US5773359A (en) * 1995-12-26 1998-06-30 Motorola, Inc. Interconnect system and method of fabrication
US5795818A (en) * 1996-12-06 1998-08-18 Amkor Technology, Inc. Integrated circuit chip to substrate interconnection and method
KR100224730B1 (ko) * 1996-12-17 1999-10-15 윤종용 반도체장치의 패턴 형성방법 및 이를 이용한 커패시터 제조방법
US6121120A (en) * 1997-08-07 2000-09-19 Nec Corporation Method for manufacturing semiconductor device capable of flattening surface of selectively-grown silicon layer
US6251528B1 (en) 1998-01-09 2001-06-26 International Business Machines Corporation Method to plate C4 to copper stud
JP2001196404A (ja) * 2000-01-11 2001-07-19 Fujitsu Ltd 半導体装置及びその製造方法
CN1314225A (zh) * 2000-02-18 2001-09-26 德克萨斯仪器股份有限公司 铜镀层集成电路焊点的结构和方法
US20010033020A1 (en) * 2000-03-24 2001-10-25 Stierman Roger J. Structure and method for bond pads of copper-metallized integrated circuits
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