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KR890001172A - 반도체 장치 - Google Patents

반도체 장치 Download PDF

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Publication number
KR890001172A
KR890001172A KR1019870006390A KR870006390A KR890001172A KR 890001172 A KR890001172 A KR 890001172A KR 1019870006390 A KR1019870006390 A KR 1019870006390A KR 870006390 A KR870006390 A KR 870006390A KR 890001172 A KR890001172 A KR 890001172A
Authority
KR
South Korea
Prior art keywords
semiconductor device
wiring board
resin
contact terminal
metal layer
Prior art date
Application number
KR1019870006390A
Other languages
English (en)
Inventor
히로시 야기모도
료우다로우 아라가와
요시미 야나가
쯔요시 후구다
Original Assignee
나가이 아쯔시
히다찌마구세루 가부시기가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 나가이 아쯔시, 히다찌마구세루 가부시기가이샤 filed Critical 나가이 아쯔시
Publication of KR890001172A publication Critical patent/KR890001172A/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745—Mounting details of integrated circuit chips
    • G06K19/07747—Mounting details of integrated circuit chips at least one of the integrated circuit chips being mounted as a module
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745—Mounting details of integrated circuit chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49855—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5388—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates for flat cards, e.g. credit cards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00015—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Theoretical Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Credit Cards Or The Like (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

내용 없음

Description

반도체 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 의한 반도체 장치(IC 모듈)의 제1실시예를 도시한 단면도.
제2도는 제1도에 도시한 반도체 장치의 작성 공정도.
제4도는 본 발명의 제4의 실시예를 도시한 반도체 장치의 단면도.

Claims (6)

  1. 배선 기판과, 그 배선 기판에 탑재헌 IC와, 이 배선 기판과 그 IC를 수지에 의해 일체로 몰드한 반도체 장치에 있어서, 상기 배선 기판은 수지 베이스 필름을 기판으로 하여 그 위에 배선, 접합 단자등의 도체 패턴을 형성한 테이프 상태이고, 상기 IC는 상기 집합 단자와 범프 전극을 거쳐서 접속시켜 형성되고, 상기 배선 기판과 상기IC를 상기 수지로서 일체로 봉하여 막도록 몰드한 구조를 가지는 것을 특징으로 하는 반도체 장치.
  2. 특허청구의 범위 제1항의 반도체 장치에 있어서, 상기 배선 기판의 도체 패턴의 일부에 외부기기용의 접촉 단자를 가지고, 그 접촉 단자와 상기 배선 기판과 상기 IC를 상기 수지에 의해 봉하여 막았을때에, 그상부가 노출하도록 구성한 것을 특징으로 하는 IC카드용의 반도체 장치.
  3. 특허청구의 범위 제2항의 반도체 장치에 있어서, 상기 배선 기판은 글라스 에폭시, 폴리이미드, 폴리에틸렌 텔레프탈레이트에서 선택되는 플라스틱 베이스 필름으로 구성되어 있는 것을 특징으로 하는 IC 카드용의 반도체 장치.
  4. 특허청구의 범위 제2항의 반도체 장치에 있어서, 접촉 단자는 금속의 적층 구조로되어 있는 것을 특징으로 하는 IC카드용의 반도체 장치.
  5. 특허청구의 범위 제4항의 반도체 장치에 있어서, 접촉 단자는, Cu 금속층, Ni 금속층, Au금속층의 3층의 적층 구조로되어 있는 것을 특징으로 하는 IC 카드용의 반도체 장치.
  6. 특허청구위 범위 제1항의 반도체 장치에 있어서, 배선 기판과 IC를 광 경화성 수지로서 일체로 봉하여 막도록 몰드한 것을 특징으로 하는 반도체 장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019870006390A 1986-07-07 1987-06-23 반도체 장치 KR890001172A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP61157918A JPS6314455A (ja) 1986-07-07 1986-07-07 半導体装置
JP61-157918 1986-07-07

Publications (1)

Publication Number Publication Date
KR890001172A true KR890001172A (ko) 1989-03-18

Family

ID=15660303

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019870006390A KR890001172A (ko) 1986-07-07 1987-06-23 반도체 장치

Country Status (3)

Country Link
EP (1) EP0254444A1 (ko)
JP (1) JPS6314455A (ko)
KR (1) KR890001172A (ko)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2602834B2 (ja) * 1987-06-09 1997-04-23 三菱電機株式会社 半導体装置
JP2559834B2 (ja) * 1989-01-12 1996-12-04 三菱電機株式会社 Ｉｃカード
JP2559849B2 (ja) * 1989-05-23 1996-12-04 三菱電機株式会社 Ｉｃカード
JPH03187791A (ja) * 1989-12-19 1991-08-15 Toshiba Corp Ｉｃカード
DE4038126C2 (de) * 1990-11-27 1993-12-16 Mannesmann Ag Verfahren und Vorrichtung zur Herstellung einer dekorierten Chip-Karte
FR2671417B1 (fr) * 1991-01-04 1995-03-24 Solaic Sa Procede pour la fabrication d'une carte a memoire et carte a memoire ainsi obtenue .
DE69523010T2 (de) 1994-10-04 2002-07-04 Nec Corp., Tokio/Tokyo Mittels automatischer Bandmontage hergestelltes Halbleitergehäuse
SG91249A1 (en) * 1999-01-14 2002-09-17 Lintec Corp Process for producing non-contact data carrier
FR2794059B1 (fr) 1999-05-31 2001-08-10 Gemplus Card Int Dispositif portable a circuit integre et procede de fabrication
GB2387714A (en) * 2002-04-19 2003-10-22 Denselight Semiconductors Pte Mount for a semiconductor device
JP2005101506A (ja) * 2003-08-21 2005-04-14 Seiko Epson Corp 電子部品実装体の製造方法、電気光学装置の製造方法、電子部品実装体、電気光学装置
EP1724712A1 (fr) * 2005-05-11 2006-11-22 Stmicroelectronics Sa Micromodule, notamment pour carte à puce
JP2010098077A (ja) * 2008-10-15 2010-04-30 Mitsumi Electric Co Ltd 回路モジュールの製造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52124865A (en) * 1976-04-13 1977-10-20 Sharp Corp Semiconductor device
US4300153A (en) * 1977-09-22 1981-11-10 Sharp Kabushiki Kaisha Flat shaped semiconductor encapsulation
DE3029667A1 (de) * 1980-08-05 1982-03-11 GAO Gesellschaft für Automation und Organisation mbH, 8000 München Traegerelement fuer einen ic-baustein
DE3130206A1 (de) * 1981-07-30 1983-02-17 Siemens AG, 1000 Berlin und 8000 München Tragbare karte zur informationsverarbeitung
FR2520541A1 (fr) * 1982-01-22 1983-07-29 Flonic Sa Procede d'insertion d'un circuit integre dans une carte a memoire et carte obtenue suivant ce procede
DE3235650A1 (de) * 1982-09-27 1984-03-29 Philips Patentverwaltung Gmbh, 2000 Hamburg Informationskarte und verfahren zu ihrer herstellung

Also Published As

Publication number Publication date
JPS6314455A (ja) 1988-01-21
EP0254444A1 (en) 1988-01-27

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Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19870623

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