[go: up one dir, main page]

KR910013444A - 전자장치 및 그 제조방법 - Google Patents

전자장치 및 그 제조방법 Download PDF

Info

Publication number
KR910013444A
KR910013444A KR1019900021113A KR900021113A KR910013444A KR 910013444 A KR910013444 A KR 910013444A KR 1019900021113 A KR1019900021113 A KR 1019900021113A KR 900021113 A KR900021113 A KR 900021113A KR 910013444 A KR910013444 A KR 910013444A
Authority
KR
South Korea
Prior art keywords
electronic component
bonding
substrate
area
component receiving
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1019900021113A
Other languages
English (en)
Inventor
티. 린 폴
비.맥셰인 마이클
Original Assignee
빈센트 죠셉 로너
모토로라 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 빈센트 죠셉 로너, 모토로라 인코포레이티드 filed Critical 빈센트 죠셉 로너
Publication of KR910013444A publication Critical patent/KR910013444A/ko
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985Flexible insulating substrates
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015Shape
    • H01L2924/1016Shape being a cuboid
    • H01L2924/10162Shape being a cuboid with a square active surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227Other objects, e.g. metallic pieces
    • H05K2201/10295Metallic connector elements partly mounted in a hole of the PCB
    • H05K2201/10303Pin-in-hole mounted pins
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10681Tape Carrier Package [TCP]; Flexible sheet connector
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/16Inspection; Monitoring; Aligning
    • H05K2203/167Using mechanical means for positioning, alignment or registration, e.g. using rod-in-hole alignment
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

내용 없음.

Description

전자장치 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 따라 부분적으로 도시된 프린트 배선판에 적층된 얇고, 몰드되고 흡착된 면의 캡슐형 전자장치 3/4의 사시도.

Claims (3)

  1. 본딩 랜드를 갖는 프린트 배선판(PCB)(12)상에 장착되는 면을 위한 전자 장치(10)로서, 주변(44)을 갖는 절연성있고, 유연성 있는 기판(32)을 구비하며, 여기서 기판(32)은 전자 성분 수용 영역(36)을 가지며, 상기 전자 성분 수용영역(36)에서 주변(44)까지 연장되는 기판(32)상에 다수의 전기적 전도 트레이스(34)를 구비하며, 여기서 상기 트레이스는 내부 밴딩 영역(42)은 전자 성분 수용영역(36)이 가까이 있으며, 상기 주변(44) 가까이 외부 본딩 영역(50)을 구비하며, 여기서 적어도 2개의 트레이스 그룹(34)은 상기 장치(10)가 거기에 장착될때 PCB(12)상의 본딩 랜드(16)에 밴드되고 접촉되기 위해 상기 외부 본딩 영역(50)을 허용하기 위해 리드 어레이(24)내에 형성되며; 다수의 본딩 패드(40)를 가지는 전자 성분(38)을 구비하며, 여기서 전자 성분(38)이 기판(32)상의 전자 성분 수용영역(36)에 접착되고 상기 본딩 패드는 내부 본딩 영역(42)에 전기적으로 접속되며; 적어도 전자 성분(38)과 내부 본딩 영역(42)둘레에 패캐지 바디(20)를 구비하는 전자 장치.
  2. 본딩 랜드(16)를 갖는 프린트 배선판 상에 장착되는 면에 대한 전자 장치로서, 주변(44)을 갖는 절연성, 유연성 있는 기판(32)을 구비하며, 여기서 상기 기판(32)은 전자 성분 수용영역(36)을 가지며, 상기 전자성분 수용영역(36)에서 주변(44)까지 연장되는 기판상에 다수의 전기적 전도성 트레이스(34)를 구비하며, 여기서 상기 트레이스는 전자 성분 수용영역(36) 가까이 내부 본딩 영역(42)을 가지며, 주변(44)까지 이 외부 본딩 영역(50)과, 각 트레이스(34)에 대해 테스트 포인트(46)를 가지며 여기서 테스트 포인트는 외부 본딩 영역(50)보다는 전자 성분 수용영역(36)으로부터 약간 제거되어 기판 주변(44)에서 존재하며, 상기 테스트 포인트(46)와 기판 주변(44)은 외부 본딩 영역(50)을 포함하는 기판 부분으로부터 세이브 가능하며, 적어도 2개의 트레이스(34) 그룹은 상기 장치가 거기에 적층될때 PCB(12)상의 본딩 랜드(16)에 대해 본드되고 접촉하기 위해 외부 본딩 영역(50)을 허용하기 위해 리드 어레이(24)내에 형성되며, 거기로부터 다수의 본딩 패드(40)를 가지는 전자성분(38)을 구비하며, 여기서 상기 전자 성분은 기판(32)상에서 전자 성분 수용영역에서 위치하며 상기 본딩 패드(40)는 내부 본딩 영역(42)에 전기적으로 접속되며, 적어도 전자 성분(38)과 내부 본딩 영역(42)을 캡슐레이팅하는 패캐지 바디(20)를 구비하는 전자 장치.
  3. 본딩 랜드(16)를 갖는 프린트 배선판(PCB)(12)에 적층되는 면에 적당한 전자 장치제조 방법으로서, 주변(44)을 갖는 절연성, 유연성 있는 기판(32)을 제공하는 것을 포함하며, 상기 기판(32)은 거기에서 전자성분 수용 영역(36)을 가지며, 상기 기판(32)는 첨가적으로 전자 성분 수용영역(36)에서 주변(44)까지 연장된 다수의 전기적 전도 트레이스(34)를 가지며, 상기 트레이스(34)는 전자 성분 수용영역(36) 가까이 내부 밴딩 영역(42)을 가지며; 주변(44) 가까이 외부 밴딩 영역(50)과; 기판(32)상에 전자 성분 수용영역(36)에 대해 다수의 본딩 패드(40)을 갖고 에픽싱하는 전자 성분(38)을 가지며, 내부 본딩 영역(42)에 전기적으로 접속되는 본딩 패드(40)와, 패캐지 바디(20)를 갖는 최소한의 전자 성분(38)과 내부 본딩 영역(42)을 서라운딩하는 것과, (PCB)(12)상에 본딩 랜드(16)에 본드되고 접촉하기 위한 외부 본딩 영역(50)을 허용하기 위해 리드 어레이(24)내에 적어도 2개의 트레이스(34) 그룹을 형성하는 것을 포함하는 전자 장치 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900021113A 1989-12-27 1990-12-20 전자장치 및 그 제조방법 Withdrawn KR910013444A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/457,648 US5018005A (en) 1989-12-27 1989-12-27 Thin, molded, surface mount electronic device
US457648 1999-12-09

Publications (1)

Publication Number Publication Date
KR910013444A true KR910013444A (ko) 1991-08-08

Family

ID=23817589

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900021113A Withdrawn KR910013444A (ko) 1989-12-27 1990-12-20 전자장치 및 그 제조방법

Country Status (4)

Country Link
US (1) US5018005A (ko)
EP (1) EP0435093A3 (ko)
JP (1) JPH04129262A (ko)
KR (1) KR910013444A (ko)

Families Citing this family (52)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8918482D0 (en) * 1989-08-14 1989-09-20 Inmos Ltd Packaging semiconductor chips
US5200362A (en) * 1989-09-06 1993-04-06 Motorola, Inc. Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film
JPH0770806B2 (ja) * 1990-08-22 1995-07-31 株式会社エーユーイー研究所 超音波溶着による電子回路およびその製造方法
JP2857492B2 (ja) * 1990-11-28 1999-02-17 シャープ株式会社 Tabパッケージ
JP2538112Y2 (ja) * 1991-05-21 1997-06-11 シャープ株式会社 実装基板
JP2923096B2 (ja) * 1991-09-10 1999-07-26 株式会社日立製作所 テープキャリアパッケージおよび高周波加熱はんだ接合装置
US5220489A (en) * 1991-10-11 1993-06-15 Motorola, Inc. Multicomponent integrated circuit package
JP2745933B2 (ja) * 1992-02-17 1998-04-28 日本電気株式会社 Tab−集積回路
US5334857A (en) * 1992-04-06 1994-08-02 Motorola, Inc. Semiconductor device with test-only contacts and method for making the same
KR930024126A (ko) * 1992-05-12 1993-12-22 아키라 기타하라 표면실장소자와 그의 반제품
US5278724A (en) * 1992-07-06 1994-01-11 International Business Machines Corporation Electronic package and method of making same
US5521427A (en) * 1992-12-18 1996-05-28 Lsi Logic Corporation Printed wiring board mounted semiconductor device having leadframe with alignment feature
US5479319A (en) * 1992-12-30 1995-12-26 Interconnect Systems, Inc. Multi-level assemblies for interconnecting integrated circuits
US5481436A (en) * 1992-12-30 1996-01-02 Interconnect Systems, Inc. Multi-level assemblies and methods for interconnecting integrated circuits
JPH06318589A (ja) * 1993-05-10 1994-11-15 Mitsubishi Electric Corp 半導体集積回路装置
US5432486A (en) * 1993-05-20 1995-07-11 Northern Telecom Limited Capacitive and inductive coupling connector
EP0641019A3 (en) * 1993-08-27 1995-12-20 Poly Flex Circuits Inc Flexible lead frame printed on a polymer.
BE1007618A3 (nl) * 1993-10-13 1995-08-22 Philips Electronics Nv Flexibel bevestigingsorgaan alsmede object voorzien van een dergelijk bevestigingsorgaan, drager voorzien van een object en een dergelijk bevestigingsorgaan en verpakking voorzien van een aantal van dergelijke bevestigingsorganen.
US5508558A (en) * 1993-10-28 1996-04-16 Digital Equipment Corporation High density, high speed, semiconductor interconnect using-multilayer flexible substrate with unsupported central portion
US5408126A (en) * 1993-12-17 1995-04-18 At&T Corp. Manufacture of semiconductor devices and novel lead frame assembly
US5468996A (en) * 1994-03-25 1995-11-21 International Business Machines Corporation Electronic package assembly and connector for use therewith
US5578869A (en) * 1994-03-29 1996-11-26 Olin Corporation Components for housing an integrated circuit device
KR950034696A (ko) * 1994-05-16 1995-12-28 김광호 초박형 반도체 패키지 및 그 제조방법
JPH0846104A (ja) * 1994-05-31 1996-02-16 Motorola Inc 表面実装電子素子およびその製造方法
US5586010A (en) * 1995-03-13 1996-12-17 Texas Instruments Incorporated Low stress ball grid array package
US5569956A (en) * 1995-08-31 1996-10-29 National Semiconductor Corporation Interposer connecting leadframe and integrated circuit
US5612513A (en) * 1995-09-19 1997-03-18 Micron Communications, Inc. Article and method of manufacturing an enclosed electrical circuit using an encapsulant
EP0767492A3 (en) * 1995-10-02 1998-09-09 Altera Corporation Integrated circuit test system
US5731709A (en) * 1996-01-26 1998-03-24 Motorola, Inc. Method for testing a ball grid array semiconductor device and a device for such testing
US6020758A (en) * 1996-03-11 2000-02-01 Altera Corporation Partially reconfigurable programmable logic device
US5692911A (en) * 1996-03-27 1997-12-02 Electronic Products, Inc. Flexible electrical test fixure for integrated circuits on prototype and production printed circuit boards
US6075289A (en) * 1996-10-24 2000-06-13 Tessera, Inc. Thermally enhanced packaged semiconductor assemblies
US5907817A (en) * 1996-12-24 1999-05-25 Ericsson Inc. Radiotelephones with coplanar antenna connectors and related assembly methods
US5917709A (en) * 1997-06-16 1999-06-29 Eastman Kodak Company Multiple circuit board assembly having an interconnect mechanism that includes a flex connector
US6008532A (en) * 1997-10-23 1999-12-28 Lsi Logic Corporation Integrated circuit package having bond fingers with alternate bonding areas
US6329594B1 (en) * 1998-01-16 2001-12-11 Bae Systems Information And Electronic Systems Integration, Inc. Integrated circuit package
US6172874B1 (en) * 1998-04-06 2001-01-09 Silicon Graphics, Inc. System for stacking of integrated circuit packages
EP1028464B1 (en) 1999-02-11 2006-07-26 STMicroelectronics S.r.l. Semiconductor device with improved interconnections between the chip and the terminals, and process for its manufacture
DE19929754C2 (de) * 1999-06-29 2001-08-16 Siemens Ag Verguß einer bestückten Baugruppe mit vibrationsdämpfender Gießmasse
JP2001119115A (ja) * 1999-10-15 2001-04-27 Japan Aviation Electronics Industry Ltd プリント基板モジュール
US6437436B2 (en) * 2000-01-20 2002-08-20 Ang Technologies Inc. Integrated circuit chip package with test points
US6469909B2 (en) 2001-01-09 2002-10-22 3M Innovative Properties Company MEMS package with flexible circuit interconnect
US6931369B1 (en) 2001-05-01 2005-08-16 National Semiconductor Corporation Method to perform thermal simulation of an electronic circuit on a network
US6678877B1 (en) * 2001-08-15 2004-01-13 National Semiconductor Corporation Creating a PC board (PCB) layout for a circuit in which the components of the circuit are placed in the determined PCB landing areas
TWI286381B (en) * 2002-08-27 2007-09-01 Gigno Technology Co Ltd Multi-chip integrated module
US20050133913A1 (en) * 2003-12-17 2005-06-23 Dan Okamoto Stress distribution package
US7476555B2 (en) * 2006-11-15 2009-01-13 Airdio Wireless Inc. Method of chip manufacturing
JP2010050445A (ja) * 2008-07-22 2010-03-04 Panasonic Corp 基板の接合構造および基板の接合方法
JP5293469B2 (ja) * 2009-07-13 2013-09-18 大日本印刷株式会社 半導体装置用複合配線部材および樹脂封止型半導体装置
US9226402B2 (en) * 2012-06-11 2015-12-29 Mc10, Inc. Strain isolation structures for stretchable electronics
CN103617965B (zh) * 2013-11-20 2019-02-22 常州唐龙电子有限公司 一种外型具有引线的扁平集成电路封装结构
JP7014645B2 (ja) * 2018-03-06 2022-02-01 シャープ株式会社 半導体発光装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4147889A (en) * 1978-02-28 1979-04-03 Amp Incorporated Chip carrier
JPS6052084A (ja) * 1983-08-31 1985-03-23 株式会社東芝 印刷配線基板
US4655524A (en) * 1985-01-07 1987-04-07 Rogers Corporation Solderless connection apparatus
US4647959A (en) * 1985-05-20 1987-03-03 Tektronix, Inc. Integrated circuit package, and method of forming an integrated circuit package
US4744009A (en) * 1986-10-31 1988-05-10 Amp Incorporated Protective carrier and securing means therefor
US4783719A (en) * 1987-01-20 1988-11-08 Hughes Aircraft Company Test connector for electrical devices
US4811081A (en) * 1987-03-23 1989-03-07 Motorola, Inc. Semiconductor die bonding with conductive adhesive
JPH01183837A (ja) * 1988-01-18 1989-07-21 Texas Instr Japan Ltd 半導体装置

Also Published As

Publication number Publication date
EP0435093A3 (en) 1991-11-06
EP0435093A2 (en) 1991-07-03
JPH04129262A (ja) 1992-04-30
US5018005A (en) 1991-05-21

Similar Documents

Publication Publication Date Title
KR910013444A (ko) 전자장치 및 그 제조방법
US5818698A (en) Method and apparatus for a chip-on-board semiconductor module
KR970013236A (ko) 금속 회로 기판을 갖는 칩 스케일 패키지
KR960026505A (ko) 반도체 장치 및 그 제조방법
KR930017153A (ko) 반도체 장치
TW341722B (en) Surface-mounted semiconductor package and its manufacturing method
KR940022755A (ko) 반도체 장치 및 그 제조방법과 반도체장치용 리드프레임(Lead frame)
KR950007070A (ko) 반도체 디바이스 패키지 제조 방법
KR940001363A (ko) 로우 프로필 오버몰드된 패드 배열 반도체 디바이스 및 그 제조방법
KR950004467A (ko) 반도체장치 및 그 제조방법
KR910019184A (ko) 반도체 장치와 그 제조방법, 리이드프레임 및 메모리 카드와 그 제조방법
KR890013751A (ko) 반도체 장치
KR840009177A (ko) 집적회로모듈 및 그 제조방법
KR100647090B1 (ko) 다수의 반도체 칩을 포함하는 반도체 소자
GB2137807B (en) A semiconductor component and method of manufacture
KR890001172A (ko) 반도체 장치
KR910008824A (ko) 반도체소자패키지 및 반도체소자패키지 탑재배선회로기판
US4258411A (en) Electronic device packaging arrangement
KR960035997A (ko) 반도체 패키지 및 그 제조방법
US7119420B2 (en) Chip packaging structure adapted to reduce electromagnetic interference
KR910017598A (ko) 반도체 장치의 실장 구조
KR960019683A (ko) 반도체 장치
JPS61177763A (ja) 半導体装置
KR920017219A (ko) 반도체장치와 반도체장치의 제조방법 및 테이프 캐리어
JPS6453568A (en) Semiconductor package

Legal Events

Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19901220

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid