KR880014690A - 상부측 기판 접촉부를 갖고 있는 cmos 집적회로 및 이의 제조방법 - Google Patents
상부측 기판 접촉부를 갖고 있는 cmos 집적회로 및 이의 제조방법 Download PDFInfo
- Publication number
- KR880014690A KR880014690A KR1019880005031A KR880005031A KR880014690A KR 880014690 A KR880014690 A KR 880014690A KR 1019880005031 A KR1019880005031 A KR 1019880005031A KR 880005031 A KR880005031 A KR 880005031A KR 880014690 A KR880014690 A KR 880014690A
- Authority
- KR
- South Korea
- Prior art keywords
- layer
- substrate
- aperture
- top surface
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 239000000758 substrate Substances 0.000 title claims 13
- 239000004065 semiconductor Substances 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims 9
- 238000000034 method Methods 0.000 claims 4
- 230000008878 coupling Effects 0.000 claims 3
- 238000010168 coupling process Methods 0.000 claims 3
- 238000005859 coupling reaction Methods 0.000 claims 3
- 230000001681 protective effect Effects 0.000 claims 3
- 238000009413 insulation Methods 0.000 claims 2
- 238000000059 patterning Methods 0.000 claims 2
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 238000005468 ion implantation Methods 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/85—Complementary IGFETs, e.g. CMOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
- H01L21/743—Making of internal connections, substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02293—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process formation of epitaxial layers by a deposition process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Electrodes Of Semiconductors (AREA)
- Superconductors And Manufacturing Methods Therefor (AREA)
- Element Separation (AREA)
Abstract
Description
Claims (4)
- 상부 표면 및 저부 표면을 갖고 있는 기판과, 능동회로 부품이 형성될 수 있도록 상부 표면상에 형성된 층을 포함하는 결합부를 포함하는 반도체 장치를 제조하는 방법에 있어서, 상기 층 상에 절연층을 형성하는 수단, 절연층을 통해 애퍼츄어를 형성하기 위해 절연층을 패턴화시키는 수단, 불순물 영역이 상기 애퍼츄어 밑의 상기 층내에 피착되도록 상기 애퍼츄어를 통하여 불순물을 유입시키는 수단, 및 상기 불순물 영역을 상기 층을 통해 상기 기판으로 하향 확산시키어, 기판과 애퍼츄어 사이에 도전 경로를 형성하는 수단을 포함하는 것을 특징으로 하는 방법.
- 제1항에 있어서, 상기 불순물이 이온 주입 방법에 의해 유입되는 것을 특징으로 하는 방법.
- 상부 표면 및 저부 표면을 갖고 있는 기판과, 능동회로 부품이 형서오딜 수 있도록 상부표면 상에 형성된 층을 포함하는 결합부를 포함하는 반도체 장치에 있어서, 상기 층상에 배치되고, 이를 통해 배치된 애퍼츄어를 갖고 있는 절연층, 및 상기 층을 통하여 연장되고 상기 기판과 접촉되는 도전 경로를 형성하는, 불순물 영역으로 구성되는 것을 특징으로 하는 반도체 장치.
- 상부 표면 및 저부 표면을 갖고 있는 기판과, 능동회로 부품이 형성될 수 있도록 상부 표면 상에 형성된 층을 포함하는 결합부를 포함하는 반도체 장치를 제조하는 방법에 있어서, 상기 층 상에 절연 층을 형성하는 수단, 절연층을 통해 다수의 애퍼츄어를 형성하기 위해 상기 절연층을 패턴화시키는 수단, 불순물 영역이 각각의 애퍼츄어 밑의 상기 층내에 피착되도록 모든 애퍼츄어를 통해 불순물을 유입하는 수단, 부품 애퍼츄어만이 보호 피막에 의해 덮히도록 미리 선택한 패턴으로 형성되는 임시 보호 피막을 상기 절연층에 인가하는 수다느 상기 기판 접촉 애퍼츄어를 통하여 상기 층내로 부수적인 불순물을 유입하는 수다느 상기 보호 피막을 제거하는 수단, 및 상기 불순물을 상기 층을 통해 상기 기판으로 하향 확산시키어, 기판과 기판 접촉 애퍼츄어 사이에 도전 경로를 형성하는 수단을 포함하고, 최소한 한 애퍼츄어는 기판 접촉 애퍼츄어로 되러, 상기 기판에의 도전 경로 위치를 정하고, 최소한 한 개의 다른 애퍼츄어는 부품 애퍼츄어로 되어, 미리 선택한 반도체 부품의 위치를 정하는 것을 특징으로 하는 방법.※ 참고사항:최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US4561087A | 1987-05-01 | 1987-05-01 | |
US45,610 | 1987-05-01 | ||
US045,610 | 1987-05-01 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR880014690A true KR880014690A (ko) | 1988-12-24 |
KR930011468B1 KR930011468B1 (ko) | 1993-12-08 |
Family
ID=21938912
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019880005031A Expired - Lifetime KR930011468B1 (ko) | 1987-05-01 | 1988-04-30 | 상부측 기판 접속부를 갖는 상보 금속 산화물 반도체 디바이스 및 이의 제조방법 |
Country Status (10)
Country | Link |
---|---|
EP (1) | EP0290305B1 (ko) |
JP (2) | JPS6428861A (ko) |
KR (1) | KR930011468B1 (ko) |
CN (1) | CN1019434B (ko) |
AT (1) | ATE78121T1 (ko) |
AU (1) | AU605853B2 (ko) |
BR (1) | BR8802165A (ko) |
CA (1) | CA1315020C (ko) |
DE (1) | DE3872590T2 (ko) |
MX (1) | MX168378B (ko) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
AU617779B2 (en) * | 1988-03-30 | 1991-12-05 | Unisearch Limited | Improved method of manufacturing buried contact solar cells |
US5361842A (en) * | 1993-05-27 | 1994-11-08 | Shell Oil Company | Drilling and cementing with blast furnace slag/silicate fluid |
US5337824A (en) * | 1993-06-28 | 1994-08-16 | Shell Oil Company | Coal slag universal fluid |
EP2457978A1 (en) | 2010-11-24 | 2012-05-30 | Evonik Degussa GmbH | Process for pyrolysis of lignin-rich biomass, carbon-rich solid obtained and use thereof as soil amendment or adsorbent |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5673446A (en) * | 1979-11-21 | 1981-06-18 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Manufacture of semiconductor device |
JPS58218158A (ja) * | 1982-06-11 | 1983-12-19 | Toshiba Corp | 相補型mos半導体装置 |
JPS60128655A (ja) * | 1983-12-16 | 1985-07-09 | Hitachi Ltd | 半導体装置 |
JPH0770604B2 (ja) * | 1985-04-17 | 1995-07-31 | ソニー株式会社 | 相補型電界効果トランジスタの製法 |
US4721682A (en) * | 1985-09-25 | 1988-01-26 | Monolithic Memories, Inc. | Isolation and substrate connection for a bipolar integrated circuit |
-
1988
- 1988-04-07 EP EP88400836A patent/EP0290305B1/en not_active Expired - Lifetime
- 1988-04-07 AT AT88400836T patent/ATE78121T1/de not_active IP Right Cessation
- 1988-04-07 DE DE8888400836T patent/DE3872590T2/de not_active Expired - Fee Related
- 1988-04-15 AU AU14666/88A patent/AU605853B2/en not_active Ceased
- 1988-04-20 MX MX011181A patent/MX168378B/es unknown
- 1988-04-29 BR BR8802165A patent/BR8802165A/pt not_active Application Discontinuation
- 1988-04-29 CA CA000565481A patent/CA1315020C/en not_active Expired - Fee Related
- 1988-04-30 CN CN88102631A patent/CN1019434B/zh not_active Expired
- 1988-04-30 KR KR1019880005031A patent/KR930011468B1/ko not_active Expired - Lifetime
- 1988-05-02 JP JP63109821A patent/JPS6428861A/ja active Pending
- 1988-07-18 JP JP63178893A patent/JPS6448454A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
AU605853B2 (en) | 1991-01-24 |
MX168378B (es) | 1993-05-20 |
CN1031155A (zh) | 1989-02-15 |
AU1466688A (en) | 1988-11-03 |
EP0290305B1 (en) | 1992-07-08 |
JPS6428861A (en) | 1989-01-31 |
EP0290305A1 (en) | 1988-11-09 |
CN1019434B (zh) | 1992-12-09 |
ATE78121T1 (de) | 1992-07-15 |
CA1315020C (en) | 1993-03-23 |
JPS6448454A (en) | 1989-02-22 |
DE3872590T2 (de) | 1993-03-11 |
KR930011468B1 (ko) | 1993-12-08 |
BR8802165A (pt) | 1988-12-06 |
DE3872590D1 (de) | 1992-08-13 |
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Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 19880430 |
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Patent event code: PA02012R01D Patent event date: 19900213 Comment text: Request for Examination of Application Patent event code: PA02011R01I Patent event date: 19880430 Comment text: Patent Application |
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Comment text: Notification of reason for refusal Patent event date: 19930127 Patent event code: PE09021S01D |
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Comment text: Decision on Publication of Application Patent event code: PG16051S01I Patent event date: 19931115 |
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