AU617779B2 - Improved method of manufacturing buried contact solar cells - Google Patents

Description

1 COMMONWEALTH OF AUSTRALIA Patent Act 1952 1 7779 ICAT ION COMPL E TE S P E C IF

(ORIGINAL)

Class Int. Class Application Number Lodged PI 7511 :30 March 1988 SComplete Specification Lodged Accepted Published Priority: Priority: Related Art REPRNT -OF RECEIPT sOO 64 4 6 3O/O3/ 89

V

44 I) t Name of Applicant UNISEARCH LIMITED Address of Applicant 221-227 Anzac Parade, Kensington, New South Wales, Commonwealth of Australia.

Actual Inventors MARTIN ANDREW GREEN and STUART ROSS WENHAM Address for Sec'ice F.B. RICE CO., Patent Attorneys, 28A Montague Street, BALMAIN. 2041.

Complete Specification for the invention entitled: "IMPROVED METHOD OF MANUFACTURING BURIED CONTACT SOLAR CELLS" The following statement is a full description of this invention including the best method of performing it known to Us:i -l-*Llti -2- The present invention relates to electrical contacts and more particularly to improved electrical contacts formed on a substrate, a solar cell of the type described in Australian Patent No. 570309 (40395/85).

This invention will be described with particular reference to solar cells but it will be appreciated that it is not limited to such an application, it being applicable to any comparable layered structure where electrical contacts are required.

Conventional solar cells may be screen printed which have their main advantages lying with their simplicity of fabrication and the associated low production costs.

SHowever, there are numerous disadvantages. Screen printed contacts typically have a minimum metallisation width of 15 about 150 m. The consequence is a fairly high degree of shading of the top surface of the solar cell, often in the vicinity of 12%.

In addition, the high shadii losses require a minimum spacing between fingers usually of at least 3mm.

sea* 20 This results in the silicon surface requiring very heavy doping to give sufficiently good conductivity in the diffused laver so as to reduce the lateral resistance *0 losses to respectable values. The unfortunate consequence of the heavy doping is a poor response of the solar cell to short wavelength light. This is because the high energy photons generate electron-hole pairs near the :go: surface in the heavily doped region which recombine without contributing to the generated current. Another problem area for screen printed contacts is the associated high contact resistance that is established between the metallisation and the silicon surface. Optimisation of infra-red furnace firing conditions or subsequent immersion in hydrofluoric acid can reduce this problem although neither will totally eliminate it. These problems may also occur in other solar cell construction 3 types. Further, any solar cell with the diffused layer confined to the top surface will suffer from a poor response to long wavelength light unless it has extremely long bulk minority carrier lifetimes. Solar cells fabricated on polycrystalline substrates are a good example of such solar cells as they typically will possess bulk minority carrier lifetimes of only about 70 m for a 1 ohm centimetre resistivity.

Australian Patent 570309 addresses these problems and alleviates them by providing a manufacturing sequence that can be broadly summarised in the following: (Sequence A) for p-type silicon substrates: texture/etch incoming wafers (ii) Phosphorus diffusion of top surface 15 (iii) wet oxidation/anti-reflection coating application (iv) mechanically or laser scribe grooves through the oxide, penetrating to or into the silicon substrate S chemically etch/clean grooves (vi) heavy Phosphorus diffusion of grooves 20 (vii) deposition of material for back surface field formation aluminium or boron glass, etc.) (viii) high temperature sinter (ix) electroless plating of front and rear contacts using nickel and copper and perhaps a capping layer such as silver.

By the present invention a first level of improvement to this sequence is obtained by the inclusion of a single step diffusion to co-diffuse the wafer top surface and the grooves giving approximately 100 ohms per square and 10 ohms per square respectively. This can be achieved by growing the thick oxide, scribing the grooves, and then simultaneously diffusing phosphorus into the grooves and into the top surface via the oxide. Under normal conditions, a few hundred angstroms of oxide are sufficient to mask the top surface from the majority of S- 4 the phosphorus hence giving the required sheet resistivities in the grooves and across the top surface.

The main problem, however, is that such a thin oxide is almost instantly removed during the step for removing the diffusion oxide, and in any case would be too thin for masking against the electroless plating and also for acting as a rudimentary anti-reflection coating.

By introducing hydrogen into the ambient during the diffusion, the rate of diffusion of the phosphorus through the silicon dioxide is greatly inicreased. It thus becomes feasible in the presence of forming gas (hydrogen/nitrogen mixture) to form an n-type layer of the desired sheet resistivity through 3000 angstroms of surface oxide, while simultaneously diffusing the grooves. This has recently 15 been demonstrated using forming gas containing hydrogen.

The improved processing sequence of the present invention (Sequence B) can thus be described broadly as: texture/etch incoming wafers i 20 (ii) wet oxidation or anti-reflection coating application (iii) laser or mechanically scribe grooves (iv) chemical clean/etch of grooves phosphorus co-diffusion of grooves and surface (vi) aluminium (or other back surface field forming compound or element) deposition .I (vii) high temperature sinter (with additional forming gas if necessary) (viii) electroless nickel/copper plating plus optional 3 capping layer such as silver (ix) edge isolate The thickness of the silicon dioxide layer can be reduced in this sequence as the etch of the phosphorus contaminated oxide layer appears to be lower. This probably indicates the presence of a reduced concentration of phosphorus even though some phosphorus has been 5 diffused entirely through the silicon dioxide layer.

Further importance, however, is placed on the uniformity of the oxide layer thickness as this will determine the uniformity of the sheet resistivity of the n-type layer.

In one case, this led to an improvement in sheet resistivity uniformities as the oxides tend to be more uniform in thickness than are the solid sources in transferring phosphorus glass.

A further modification is to combine two more high temperature steps and (vii) from Sequence B, by switching to an external source of phosphorus such as POC1 3 or solid source material in the end of the tube.

SThis gives a sequence (Sequence C): texture/etch incoming wafers 15 (ii) wet oxidation or anti-reflection coating application (iii) laser or mechanically scribe the grooves S. (iv) chemically etch/clean the grooves aluminium deposition (or equivalent) (vi) high temperature sinter including phosphorus glass 20 transfer to wafers (vii) electroless nickel/copper plating plus optional capping layer (viii) edge isolate Step (vi) in Sequence C becomes an extremely versatile one which effectively includes: the sintering of the aluminium metal contact; the formation of the back surface field by aluminium diffusion; a light phosphorus diffusion of the top surface; and a heavy phosphorus diffusion of the grooves. In this step, the aluminium diffusion commences as soon as the wafers teach a high temperature. The phosphorus diffusion of the grooves, however, only commences after the phosphorus glass transfer takes place which is independently initiated through the external source. Furthermore, the diffusion of the top surface can be virtually turned on or off 6 through the presence of hydrogen.

The benefits of this sequence are numerous. Firstly, the combining of three high temperature steps into one greatly simplifies the sequence which should equate to lower costs, better yields, and reduce the risk of contamination. Secondly, delaying the introduction of phosphorus until after the aluminium sinter/diffusion has commenced, should reduce any harmful effects that can potentially occur through the presence of phosphorus in the rear. Thirdly, the growth of the protecting/masking oxide as the first high temperature step should enable subsequent processing to be carried out with substantially Sless stringent cleanliness conditions. Most contaminants that are potentially harmful to the minority carrier 15 lifetimes of the bulk of the silicon material tend to diffuse relatively slowly through silicon dioxide and hence are unlikely to cause harm even if present in moderate quantities. Finally, with an external phosphorus source, the phosphorus glass can be deposited on the 20 wafers to any desired thickness prior to diffusion commencing. Consequently, improved uniformity in the groove diffusion should be feasible as, too, should ths diffusion across the top surface which basically depends only on the uniformity of the oxide layer.

In Sequences B and C, the aluminium (or equivalent) can actually be applied at various different points within the respective sequence. For instance, the aluminium S* layer could even be potentially deposited as the first 4 step after the texturing was completed.

In the described sequences, it is feasible to replace the oxide layer with an appropriate anti-reflection coating such as silicon nitride. The enchanced diffusion of phosphorus in the presence of hydrogen can be used in similar manner as with an oxide layer, provided appropriate re-optimisation of sintering times and LI -~ill I 7

S

j S

S

.9 temperatures takes place. It should be noted that it is feasible to deposit or grow an anti-reflection coating without removing the diffusion glass in the original sequence. However, in Sequences B and C it may be necessary to grow or deposit a passivating layer (such as silicon dioxide) directly onto the silicon surface prior to depositing the anti-reflection layer.

After the aluminium has been deposited onto the rear of the cells, it is beneficial in subsequent high temperature steps to place the cells in the furnace in such a way that the rear surfaces remain slightly hotter than the corresponding front surfaces. One way this can be done is by placing the wafers back to back with extremely small spacing, while maintaining a larger 15 spacing between the cell front surfaces. The purpose of keeping the rear surfaces hotter is to prevent thermal gradient zone melting from taking place which would otherwise cause the molten aluminium/silicon region to migrate into the substrate, hence destroying diffusion of 20 the aluminium.

The described sequences have been optimised for float zone wafers but are quite applicable with minor variations to Czochralski, polycrystalline, ribbon and other bulk and thin film silicon substrates. For instance, it is well known in the art that Czochralski wafers have the tendency to form oxygen precipitates in the 1000-1200 0 temperature range, particularly when preceded by a nucleating step. It can be beneficial, therefore, to grow the oxide layer (Step (ii) in Sequences 8 and C) in oxygen at about 1200 0 C to form a denuded zone at the wafer surfaces in which the out diffusion of oxygen has reduced oxygen level concentrations to sufficiently low levels to prevent precipitates from subsequently forming in the denuded regions. These denudid zones at the surfaces subsequently during processing become the sites for the 9*

S

S S *r S -8diffused emitter, the p-n junction and the back surface field, which importantly remain free from the presence of precipitates. An alternative approach is to select all processing conditions so as to avoid the temperature range in which nucleation takes place. Without the nucleation step, oxygen precipitates will not form, even if the oxygen concentration is high. Another alternative is to deliberately form precipitates in a controlled manner, in specific regions of the cell, to facilitate and enhance gettering.

The present invention will now be described by way of example with reference to the accompanying drawings, in Swhich:- Fig. 1 is a schematic cross-sectional view of a 15 portion of a solar cell incorporating a buried contact in accordance with the invention; and Figs. and are profile shapes for three different grooves for receiving "buried" contacts in accordance with the present invention, 20 In Fig. 1 there is shown a section of a solar cell 1 having a top surface 10 formed of n-type material, a rear metal contact 11 and a cell body 12 of p-type material. A groove 13 formed in top surface 10 contains a metallised contact 14.

The solar cell 1 has a plurality of grooves 13 in the wafer surface to define the contact metallisation. The grooves 13 may be formed by laser scribing, chemically etching or mechanical abrasion. The metallisation can be applied by electroplating or solder dipping.

Alternatively it may be applied successfully in paste form by a sweeping stroke of a squeegee or equivalent, across the wafer surface forcing the metal paste into the grooves 13. In some cases it may be preferred to firstly apply a thin layer of metal such as titanium, to the bottom of each groove 13 by e.g. vacuum evaporation or equivalent.

AA

i~ 9 Any of the above may be carried out in conjunction with appropriate photo lithographic work for defining grooves or for metal definition.

Formation of grooved contacts is particularly suited to polycrystalline substrates where the different grain orientations provide strength in the grooved regions.

Grooves, however, can also be used in single crystal substrates but may require greater handling care during processing, and/or thicker substrates 600 m thick). However depths of 150 m can be obtained.

Typically, but not necessarily, the width of a groove relative to its depth is in the range 1:2 to 1:7.

Various parameters to be considered in designing a j buried contact solar cell in accordance with the invention 15 include: Sheet resistivity Ps is desirably 60 as the response of the resultant cell to short wavelength Clight deteriorates rapidly below this value.

(ii) Groove width Wg is preferably 25 m but should off 20 not be too wide 100 m) as shading losses S. become excessive.

(iii) Groove depth tg is preferably not greater than half the width of the wafer as too much weakening of the substrate results.

Preferably, tg 5000/Wg for tg and Wg in m for screen printed silver paste or tg 1 7 00 /Wg for tg and Wg in m for plated silver or copper as this provides adequate cross sectional area for the silver conductor.

(iv) Finger spacing should preferably be in the range of 2.5mm depending upon the Ps and the shading losses created by Wg.

An embodiment of the present invention utilises a finger spacing of 1.8mm, a finger width of 45-50 m and a finger depth of 100-150 m. The resulting shading losses are 3.5-4.0% and the necessary top diffused layer sheet resistivity is about 80 The corresponding power loss in the top diffused layer is of the order of Assuming the grooves are full of silver paste, although other conducting metals can be used, the cross sectional area of the fingers is about 6000sq. m thus allowing 10cm length of finger to be utilised without exceeding the specified current density.

One preferred example of a processing sequence suitable for producing a buried contact solar cell in accordance with the present invention is: Texture/etch incoming wafers by any convenient *15 conventional method (ii) Wet or dry oxidation, or anti-reflection coating *e application S" For a wet or dry oxidation, an oxide thickness in the range 1500-3000 angstroms is adequate to 20 facilitate the subsequent single step diffusion process while simultaneously providing a sufficient post processing oxide thickness. At the completion of the oxide growth, an anneal of this oxide for about 30 minutes in nitrogen or argon is beneficial, although unnecessary if ~the subsequent duration of step (vi) exceeds minutes.

(iii) Laser or mechanically scribe the grooves A range of laser and mechanical scribers can be used to adequately form the grooves. For uniform metal plating the oxide should be damaged in continuous strips, with corresponding groove geometries being far less critical. For a Q-switched laser such as the Quantronix Q-switched Nd:YAG laserr, the pulse I I--i~ 11 frequency and power can be varied to give desired groove depths. Typical groove depths and widths are 60 microns and 20 microns respectively. Most mechanical scribers will ,.ve reduced depth to width ratios with corresponding increases in both shading and resistive losses for finished devices.

(iv) Chemical etch/clean the grooves A 12% W/V NaOH or KOH etch at 50-5500 will adequately remove slag and damage from the groove regions in about 20 minutes and leave a surface well prepared for subsequent processing. However, a wide range of concentrations, temperatures and times can be 15 used, particularly if different groove shapes are required as described in U.S. Patent 4626613 "Laser Grooved Solar Cell".

Aluminium deposition (or equivalent) Aluminium can be deposited on the rear of the 20 wafer by numerous techniques such as vacuum evaporation, sputtering, screen printing, application of aluminium foil, etc. Layer thickness between 0.2 microns and 40 microns have been demonstrated to be compatible with 1 25 the laser grooved processing sequence.

(vii) High temperature sinter including phosphorus glass i. i* transfer to wafers Wafers may be placed in the high temperature furnace in an 02, N2 or Argon ambient although the presence of 02 is recommended for no more than a couple of minutes or else excessive oxidation of the aluminium results.

The sintering conditions are quite flexible with regard to when the phosphorus and hydrogen are introduced, and the time and temperature i 0 0 sloe is 41 0 ii 12 regimes used. An example of suitable conditions is: sinter wafers in N2 at 1000 0 C for minutes; introduce POC1 3 using N 2 carrier gas for minutes; cease flow of POC1 3 for 5 minutes before introducing forming gas hydrogen) for 4 hours; return to N 2 gas flow, wait 5 minutes, then remove wafers.

This sequence provides adequate phosphorus diffusion for the groove regions and through the oxide (2200 angstroms) into the wafer top surface.

15 (vii) Electroless nickel/copper plating plus optional capping layer Electroless plating needs to be preceded by a suitable chemical treatment such as immersion in diluted hydrofluoric acid, to remove the diffusion glass from the grooved region, Excessive time int he hydrofluoric acid is to be avoided or the top surface oxide or antireflection coating will be completed removed. A brief (typically 3-4 minutes) rinse in deionised water is to be followed by electroless nickel deposition by conventional techniques, and thel electroless copper deposition. A range of commercially available nickel and copper plating solutions are suitable. On completion, a capping layer may be formed such as through the use of an immersion silver plating solution.

(viii) Edge isolate This may be done via a range of techniques well known in the art.

4*.g 0 04e* cc *e .0 0

Claims (13)

1. A method of producing electrical contacts on a substrate which includes forming an anti-reflection coating over a top surface and forming grooves extending through the coating and within the substrate and characterized by further including a phosphorus diffusion step of heating said substrate in the presence of phosphorus and hydrogen so as to simultaneously diffuse phosphorus directly into said grooves and through said anti reflection coating into said top surface.

2. A method as defined in claim 1 wherein said anti reflection coating is an oxide coating.

3. A method as defined in claim 1 or 2 wherein said phosphorus diffusion step comprises controlling the supply of hydrogen so as to control the phosphorus diffusion into the top surface through the anti reflection layer.

4. A method as defined in claim 1, 2 or 3 wherein prior to said phosphorus diffusion step a back surface material sub& h-Lizx is deposited ori a back surface of the ayeed=mher-pso as to form by effect of heat during said phosphorus diffusion step a diffused back surface layer. A method as defined in claim 4 where the back surface S* material is aluminium.

S.

6. A method as defined in claim 5 wherein the aluminium is applied so as to additionally form by effect of heat during said phosphorus diffusion step a sintered aluminium metal contact.

7. A method as defined in claim 3, 4, 5 or 6 wherein said phosphorus diffusion step is performed by heating said material ii a gas ambient and phosphorus is introduced into the ambient under control so as to control the relative rate of phosphorus diffusion.

8. A method as defined in claim 7 wherein said phosphorus is introduced as a gas compound or as a solid source located within the ambient and physically separated from the "ea> A '1 .i 7 14

9. A method as defined in claim 7 or 8 where said ambient gas is nitrogen.

A method as defined in claim 7, 8 or 9 wherein said phosphorus is introduced after a predetermined amount of back surface diffusion has occurred.

11. A method as defined in any one of thq preceding claims wherein a plurality of similar iyy m 'al articlea are placed closely spaced back surface to back surface and widely spaced top surface to top surface prior to said phosphorus step.

12. A method of producing electrical contacts on a substrate, comprising: forming an anti-reflective coating on a top surface of the substrate; forming grooves on the top surface; and heating the substrate having the grooves and anti-reflection coating thereon in the presence of phosphorus and a controlled supply of hydrogen in a manner so as to simultaneously diffuse, in a controlled manner, phosphorus through the anti-reflection coating and into *i the grooves.

13, A method substantially as described herein with reference to the drawings. S* DATED this 30th day of May 1991 UNISEARCH LIMITED Patent Attorneys for the Applicant: F.B. RICE CO.