CN114188431B - Solar cell and preparation method thereof - Google Patents

Abstract

The application discloses a solar cell, which comprises a silicon substrate, a tunneling layer, a first doped polysilicon layer, a first dielectric layer and a first electrode; a tunneling layer, a first doped polysilicon layer and a first dielectric layer are sequentially laminated on one side surface of the silicon substrate; the first electrode comprises a first main gate electrode and a first thin gate electrode, and the first thin gate electrode is intersected with and electrically connected with the first main gate electrode; the first main gate electrode burns through the first dielectric layer and extends into the first doped polysilicon layer; a first metal nano particle with a crystalline state at the junction of the first doped polysilicon layer and the first main gate electrode; a plurality of first openings penetrating through the first dielectric layer are formed in the first dielectric layer; the first thin gate electrode is electroplated on the first doped polysilicon layer exposed by the first opening. The application also provides a preparation method of the solar cell. The solar cell reduces the usage amount of the first main gate electrode slurry, and also enhances the bonding strength of the first main gate electrode and the first thin gate electrode.

Description

A solar cell and its preparation method

Technical field

The present application relates to the technical field of solar cells, and specifically to a solar cell and a preparation method thereof.

Background technique

Crystalline silicon solar cells currently have the highest market share due to their high energy conversion efficiency. How to improve the conversion efficiency of crystalline silicon solar cells and modules while reducing their production costs is the biggest problem facing the industry. In current large-scale silicon solar cell manufacturing, screen printing is usually used to realize the metallization process of silicon solar cells. However, the accuracy of screen printing is limited. The shape of the printed electrode is undulating, and the electrode broadens greatly after printing and sintering. As a result, the height-to-width ratio of the formed gate is low, thereby reducing the effective light-receiving area of the light-receiving surface of the silicon solar cell. In addition, the series resistance of the silicon solar cell made by screen printing is large. As the market and production capacity of the photovoltaic industry expands, the continued and stable supply of silver paste will become a severe test, and cost competitiveness is also an issue due to rising silver prices. Therefore, research on the use of plating methods has been actively conducted in recent years.

Because electroplating is difficult when the seed layer is not formed on the silicon wafer, it is required to form a conductive layer on the silicon wafer in advance for subsequent electroplating processes. The seed layer formation process is performed independently in a separate device, such as by sputtering or light-induced plating. However, sputtering the seed layer requires additional sputtering equipment in the existing production line to sputter the required pattern. A masking step is also required, which is complex and difficult to reduce production costs. Moreover, the sputtered seed layer is usually not conductive enough to carry the large current density generated by silicon-based solar cells and needs to be coated with other metals such as nickel and copper to enhance Conductivity.

Contents of the invention

In response to the above problems, this application proposes a solar cell and a preparation method thereof. The solar cell not only reduces the usage of slurry of the first main grid electrode, but also enhances the connection between the first main grid electrode and the first fine grid. The bonding strength of the electrodes increases the current collection efficiency.

This application provides a solar cell, including a silicon substrate, a tunneling layer, a first doped polysilicon layer, a first dielectric layer, and a first electrode;

The tunneling layer, the first doped polysilicon layer, and the first dielectric layer are sequentially stacked on one side of the silicon substrate;

The first electrode includes a first main gate electrode and a first fine gate electrode, the first fine gate electrode intersects and is electrically connected to the first main gate electrode;

The first main gate electrode burns through the first dielectric layer and extends into the first doped polysilicon layer; there is a crystalline state at the interface between the first doped polysilicon layer and the first main gate electrode. The first metal nanoparticles;

A plurality of first openings penetrating the first dielectric layer are opened on the first dielectric layer; the first fine gate electrode is electroplated on the first doped polysilicon layer exposed by the first openings.

Further, the crystalline first metal nanoparticles include the same metal as the metal material in the first main gate electrode;

The crystalline first metal nanoparticles are discretely distributed in an island shape at the interface between the first doped polysilicon layer and the first main gate electrode.

Further, the crystalline first metal nanoparticles include metallic silver.

Further, the first main gate electrode includes a stacked first printed sintering layer and a first metal layer,

The first printed and sintered layer extends through the first dielectric layer into the first doped polysilicon layer, and has the crystalline layer at the interface between the first doped polysilicon layer and the first printed and sintered layer. The first metal nanoparticles in the state;

The first metal layer is disposed on a side surface of the first printed sintering layer facing away from the first doped polysilicon layer.

Further, the first main gate electrode further includes a first auxiliary electrode, the first auxiliary electrode is located at the intersection of the first main gate electrode and the first fine gate electrode; the first auxiliary electrode is at A cross-sectional area along a direction perpendicular to the silicon substrate gradually decreases in a direction away from the first main gate electrode and closer to the first thin gate electrode.

Further, a second electrode with an opposite polarity to the first electrode is included. The second electrode includes a second main gate electrode and a second fine gate electrode. The second fine gate electrode is connected to the second main gate electrode. The gate electrodes intersect and are electrically connected;

The second main gate electrode also includes a second auxiliary electrode located at the intersection of the second main gate electrode and the second fine gate electrode; the second auxiliary electrode is located along an edge perpendicular to The cross-sectional area in the direction of the silicon substrate gradually decreases in a direction away from the second main gate electrode and closer to the second thin gate electrode.

Further, a doped layer is formed on a side surface of the silicon substrate facing away from the tunnel layer, and a second dielectric layer is provided on the surface of the doped layer;

The second main gate electrode burns through the second dielectric layer and extends into the doped layer;

There are crystalline second metal nanoparticles at the interface between the doping layer and the second main gate electrode; or there is a eutectic layer at the interface between the doping layer and the second main gate electrode. Local back field.

Further, the second main gate electrode includes metal aluminum or metal silver;

When the second main gate electrode includes metallic aluminum, there is a eutectic layer and a local back field at the interface with the second main gate electrode in the doped layer;

When the second main gate electrode includes metallic silver, there are crystalline second metal nanoparticles at the interface with the second main gate electrode in the doped layer; the crystalline second metal nanoparticles are Metal nanoparticles are discretely distributed in an island shape at the interface between the doping layer and the second main gate electrode.

Further, the second main gate electrode includes a stacked second printed sintering layer and a second metal layer,

The second printed and sintered layer extends through the second dielectric layer into the doped layer, and in the doped layer, there is the second crystalline layer at the interface with the second printed and sintered layer. metal nanoparticles;

The second metal layer is disposed on a side surface of the second printed sintering layer facing away from the doped layer.

Further, the first electrode and the second electrode are located on the same side of the silicon substrate.

Further, the second fine gate electrode and the first fine gate electrode are alternately parallel to each other;

The second main gate electrodes and the first main gate electrodes are alternately parallel to each other.

Further, on the surface of the silicon substrate, the tunneling layer includes a plurality of tunneling units arranged at intervals,

The area between adjacent tunnel units is the first area,

The first dielectric layer covers the surface of the first doped polysilicon layer, the side surfaces of the first doped polysilicon layer, the side surfaces of the tunneling unit and the surface of the silicon substrate in the first region.

Further, the second main gate electrode is connected to the silicon substrate through the first dielectric layer in the first region.

Further, on the surface of the tunneling layer, the first doped polysilicon layer includes a plurality of first doped polysilicon units spaced apart;

The area between adjacent first doped polysilicon units is the second area;

A second doped polysilicon unit is provided in the second region, and a plurality of the second doped polysilicon units constitute a second doped polysilicon layer;

The first dielectric layer covers the surfaces of the first doped polysilicon unit and the second doped polysilicon unit;

The second main gate electrode penetrates the first dielectric layer and is connected to the second doped polysilicon layer.

This application provides a method for preparing a solar cell, which includes the following steps:

Provide silicon substrate;

disposing a tunneling layer on one side surface of the silicon substrate;

Deposit a first doped polysilicon layer on the side of the tunnel layer facing away from the silicon substrate;

Deposit a first dielectric layer on the side of the first doped polysilicon layer facing away from the tunnel layer;

A first printed electrode paste is printed on the side of the first dielectric layer facing away from the first doped polysilicon layer and sintered so that the first printed electrode paste burns through the first dielectric layer to form a connection with the first dielectric layer. A first printed and sintered layer connected to the first doped polysilicon layer, and crystalline first metal nanoparticles are formed at the interface between the first doped polysilicon layer and the first printed and sintered layer;

Provide a plurality of first openings penetrating the first dielectric layer on the first dielectric layer;

Electroplating and depositing metal on the surface of the first printed and sintered layer forms a first metal layer, and the first printed and sintered layer and the first metal layer constitute the first main gate electrode;

Metal is electroplated and deposited on the silicon substrate having the first opening.

Further, it also includes heat treatment of the deposited metal; the sintering temperature is 750°C-900°C, and the heat treatment temperature is 250°C-500°C.

Further, a second dielectric layer is deposited on a side surface of the silicon substrate facing away from the tunnel layer;

The first doped polysilicon layer and the tunneling layer are ablated at intervals on the surface of the first doped polysilicon layer to expose the silicon substrate, thereby forming a first region;

The first dielectric layer is deposited on the surface of the first doped polysilicon layer and the side surfaces of the first doped polysilicon layer, the side surfaces of the tunneling unit and the surface of the silicon substrate in the first region.

Further, a second printed electrode slurry is printed on the surface of the first dielectric layer in the first area, a second printed sintered layer is formed through the sintering, and the second printed electrode slurry burns through the first printed electrode slurry. The two dielectric layers are connected to the doped layer, and a crystalline second metal nanoparticle or eutectic layer and a local back field are formed at a junction of the doped layer close to the second printed and sintered layer;

Electroplating and depositing metal on the surface of the second printing and sintering layer to form a second metal layer;

The second printed sintering layer and the second metal layer constitute a second main gate electrode.

Further, a plurality of second openings penetrating the first dielectric layer are provided on the first dielectric layer, metal is electroplated and deposited in the second openings, and a second fine gate electrode is formed through the heat treatment, and The second fine gate electrode is connected to the silicon substrate;

The second fine gate electrode intersects and is electrically connected to the second main gate electrode to form a second electrode.

Further, on the surface of the tunnel layer, first doped polysilicon units and second doped polysilicon units are deposited at intervals in sequence,

A plurality of the first doped polysilicon units constitute the first doped polysilicon layer;

A plurality of the second doped polysilicon units constitute the second doped polysilicon layer;

The first dielectric layer is deposited on the surface of the first doped polysilicon unit and the surface of the second doped polysilicon unit.

Further, a second printed electrode slurry is printed on the surface of the first dielectric layer corresponding to the second doped polysilicon layer, and a second printed sintered layer is formed through the sintering, and the second printed electrode slurry is burned through. The first dielectric layer is connected to the second doped polysilicon layer;

Electroplating and depositing metal on the surface of the second printing and sintering layer to form a second metal layer;

The second printed sintering layer and the second metal layer constitute a second main gate electrode.

Further, a plurality of second openings penetrating the first dielectric layer are provided on the first dielectric layer, metal is electroplated in the second openings, and a second fine gate electrode is formed through the heat treatment, and the The second fine gate electrode is connected to the second doped polysilicon layer;

The second fine gate electrode intersects and is electrically connected to the second main gate electrode to form a second electrode.

In the solar cell provided by the present application, the plurality of crystalline first metal nanoparticles have relatively low resistance and move from the silicon substrate through the tunneling layer to carriers (for example, electrons) in the first conductive type semiconductor region. ) can be directly moved (contacted) to the first main gate electrode by the first metal nanoparticles in the crystalline state, or can be multi-step transition between the first metal nanoparticles in the crystalline state and the first metal nanoparticles in the crystalline state , and move to the first electrode. The crystalline first metal nanoparticles can therefore be used to help carriers move to the first electrode more easily. Moreover, the crystalline first metal nanoparticles are located at the interface between the first doped polysilicon layer and the first main gate electrode and will not damage the performance of the tunneling layer. Both the first fine gate electrode and the second fine gate electrode adopt an electroplating process, which will not damage the tunneling layer. Moreover, the electroplating process does not require the formation of an additional seed layer. The main grid serves as the connection point. The bonding force between the main grid and the polysilicon is better, which is more conducive to improving the pull-out force between the main grid and the welding ribbon.

Description of the drawings

The accompanying drawings are used for a better understanding of the present application and do not constitute an undue limitation of the present application. in:

Figure 1 is a schematic structural diagram of a solar cell provided by this application.

Figure 2 is a schematic structural diagram of a solar cell provided by this application.

Figure 3 is a schematic structural diagram of a solar cell provided by this application.

Figure 4 is a schematic structural diagram of the light-receiving surface or backlight surface of the solar cell provided by this application.

Figure 5 is a schematic structural diagram of the light-receiving surface or backlight surface of the solar cell provided by this application.

Figure 6 is a schematic structural diagram of the light-receiving surface or backlight surface of the solar cell provided by this application.

Explanation of reference signs

1-Silicon substrate, 2-Tunnel layer, 3-First doped polysilicon layer, 4-First dielectric layer, 5-First main gate electrode, 6-Crystalline first metal nanoparticles, 7-First Fine gate electrode, 8-doped layer, 9-second dielectric layer, 10-anti-reflection layer, 11-second main gate electrode, 12-second fine gate electrode, 13-eutectic layer, 14-first connection point, 15-first connection gate line, 16-second connection point, 17-second connection gate line, 18-first auxiliary electrode, 19-local back field, 20-second doped polysilicon layer.

Detailed ways

Exemplary embodiments of the present application are described below, including various details of the embodiments of the present application to facilitate understanding, and they should be considered to be exemplary only. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the application. Also, descriptions of well-known functions and constructions are omitted from the following description for clarity and conciseness. In this application, the upper and lower positions are determined according to the incident direction of the light, and the incident point of the light is upward.

This application provides three types of solar cells, as follows.

"The First Solar Cell"

As shown in Figure 1, the solar cell provided by this application includes a silicon substrate 1, a first electrode and a second electrode. On the back (rear surface) of the silicon substrate 1, a tunneling layer 2, a first doped The polysilicon layer 3 and the first dielectric layer 4 are sequentially formed on the front surface (front surface) of the silicon substrate 1 with a doping layer 8 and a second dielectric layer 9 . The first electrode penetrates the first dielectric layer 4 and extends into the first doped polysilicon layer 3 , and has a crystalline state at the interface between the first doped polysilicon layer 3 and the first electrode. The first metal nanoparticles 6. The second electrode extends through the second dielectric layer 9 into the doped layer 8 , and has crystalline second metal nanoparticles at the interface between the doped layer 8 and the second electrode. Or eutectic layer 13 and local back field 19.

Specifically, the first electrode includes a plurality of first main gate electrodes 5 and a plurality of first fine gate electrodes 7, each of the first main gate electrodes 5 intersects with each of the first fine gate electrodes 7 and Electrical connection. In the first doped polysilicon layer 3 , there are crystalline first metal nanoparticles 6 at the interface with the first main gate electrode 5 . In the first doped polysilicon layer 3 , there are no crystalline first metal nanoparticles 6 at the interface with the first fine gate electrode 7 .

Specifically, the second electrode includes a plurality of second main gate electrodes 11 and a plurality of second fine gate electrodes 12, each of the second main gate electrodes 11 intersects with each of the second fine gate electrodes 12, and Electrical connection.

Further, when the second main gate electrode 11 includes metallic silver, there are crystalline second metal nanoparticles in the doped layer 8 at the interface with the second main gate electrode 11 . within the doped layer 8 . There are no crystalline second metal nanoparticles at the interface with the second fine gate electrode 12 .

Further, when the second main gate electrode 11 includes metallic aluminum, there is a eutectic layer 13 and a local back field 19 at the interface with the second main gate electrode 11 in the doped layer 8 . Within the doped layer 8 , there is no eutectic layer 13 and local back field 19 at the interface with the second fine gate electrode 12 .

In this application, the silicon substrate 1 may be made of single crystal or polycrystalline semiconductor (eg, single crystal or polycrystalline silicon). The front and/or back of the silicon substrate 1 may have a pyramid shape of irregular dimensions. The textured structure on the front side can reduce the reflectivity of light incident through the front side of the silicon substrate 1 . Therefore, light loss can be minimized, and the amount of light reaching the pn junction formed by the base region and the first doped polysilicon layer 3 or the doped layer 8 is increased. Texture has been illustrated in Figure 1 as being formed in the front and back surfaces of the silicon substrate 1, thereby effectively preventing reflection of light incident through these two surfaces. The texture structure may also be formed only in the front surface of the silicon substrate 1 , and the texture structure may not be formed in the back surface of the silicon substrate 1 . In this case, the back surface of the silicon substrate 1 on which the tunnel layer 2 is formed may be formed to have a smaller surface roughness than the front surface thereof, so that the tunnel layer 2 is formed more stably and uniformly.

In the present application, the tunneling layer 2 may be disposed on the rear surface of the first doped polysilicon layer 3 and may be in direct contact with the first doped polysilicon layer 3 . The tunneling layer 2 and the first doped polysilicon layer 3 formed thereon may be formed on the entire surface of the rear surface; or may be formed on part of the rear surface. The tunneling layer 2 can produce a tunneling effect and serve as a barrier for electrons and holes. After minority carriers are accumulated in the portion adjacent to the tunneling layer 2 , only majority carriers having energy of a specific level or higher can pass through the tunneling layer 2 . Majority carriers with energy of a specific level or higher can easily pass through the tunneling layer 2 through the tunneling effect. Furthermore, the tunneling layer 2 may also serve as a diffusion barrier for preventing dopants of the first doped polysilicon layer 3 from diffusing into the silicon substrate 1 . Tunneling layer 2 may include various materials through which majority carriers can tunnel. For example, the tunneling layer 2 may include oxides, nitrides, semiconductors, and conductive polymers.

Specifically, the tunneling layer 2 may be formed of a silicon oxide layer including silicon oxide (SiOx). The silicon oxide layer has excellent passivation properties and carriers can easily tunnel through the silicon oxide layer. In some embodiments, tunneling layer 2 may be made of SiCx, or may be made of SiNx, hydrogenated SiNx, AlOx, SiON or hydrogenated SiON. In order to fully realize the tunneling effect, the thickness of the tunneling layer 2 may be 0.5nm˜2.5nm. The tunneling layer 2 may be formed by, for example, an oxidation process, a LPCVD process or a PECVD deposition process.

In the present application, the first doped polysilicon layer 3 is spaced apart from the silicon substrate 1 as shown in FIG. 1 , and the first doped polysilicon layer 3 is included on the rear surface of the tunneling layer 2 The doped polysilicon material formed on the solar cell has good conductivity and can smoothly generate tunneling of carriers in the tunneling layer 2 made of oxide, which can further increase the open circuit voltage Voc of the solar cell. The thickness of the first doped polysilicon layer 3 may be 50 nm to 500 nm. The first doped polysilicon layer 3 may be formed by doping impurities into the amorphous silicon material or the polysilicon material through various methods, such as deposition.

Specifically, the silicon substrate 1 may be doped with impurities of the first doped polysilicon layer 3 or the doped layer 8 at a low doping concentration. In this case, the silicon substrate 1 may have a lower doping concentration, a higher resistance, or a lower carrier concentration than one of the first doped polysilicon layer 3 and the doped layer 8 , which The first doped polysilicon layer 3 or the doped layer 8 has the same conductivity type as the silicon substrate 1 .

Specifically, the doped layer 8 is provided on the opposite surface of the silicon substrate 1 , for example, the front surface of the silicon substrate 1 onto which light is incident. The doped layer 8 may include impurities of the opposite conductivity type to that of the semiconductor substrate. The doped layer 8 may be formed as a doped region formed by doping impurities in the doped layer 8 into a portion of the silicon substrate 1 .

Specifically, for example, in this application, the first doped polysilicon layer 3 (the impurities in the first doped polysilicon layer 3 and the silicon substrate 1 are of p-type conductivity type) and the silicon substrate 1 have the same conductivity type, A back surface field (BSF) region having a higher doping concentration than the silicon substrate 1 and forming the BSF may be formed. The doped layer 8 (the impurities in the doped layer 8 are of n-type conductivity type) and the silicon substrate 1 have the opposite conductivity type, and can form the emitter region of the pn junction, so that the light entering the pn junction region is Path minimization.

In this application, both the first dielectric layer 4 and the second dielectric layer 9 can be a single-layer or multi-layer film structure. The first dielectric layer 4 can be a silicon nitride film or a silicon nitride film containing hydrogen. , one or more of silicon oxide film, silicon oxynitride film, aluminum oxide film, MgF ₂ film, MgF ₂ film, TiO ₂ film, and CeO ₂ film. An anti-reflective layer 10 may also be provided on a side surface of the second dielectric layer 9 away from the doped layer 8 , and the anti-reflective layer 10 may be a silicon nitride layer.

Specifically, the first dielectric layer 4 may be a first passivation film, that is, a silicon nitride film, may have a refractive index of 1.9 to 2.1, and may have a thickness of 30 nm to 50 nm.

Specifically, the second dielectric layer 9 may be a second passivation film, and may have a double-layer structure in which an aluminum oxide film and a silicon nitride film are sequentially stacked on the doped layer 8 . In this case, the aluminum oxide film may have a refractive index of 1.5 to 1.7 and a thickness of 5 nm to 10 nm. The silicon nitride film may have a refractive index of 1.9 to 2.1 and a thickness of 70 nm to 120 nm.

In this application, the height of the first fine gate electrode 7 may be 15 microns or less, for example less than 10 microns, and the width is less than 35 microns. The height difference between the first main gate electrode 5 and the first fine gate electrode 7 is 5-35 microns. Such a setup can reduce the area and amount of electrode setup and production costs by depositing metal electrodes with low resistivity.

In this application, the first main gate electrode 5 burns through the first dielectric layer 4 and extends into the first doped polysilicon layer 3. The opening burned in the first dielectric layer 4 is the first sintering port. A plurality of first openings penetrating the first dielectric layer 4 are opened on the first dielectric layer 4; the first fine gate electrode 7 is electroplated on the first doped polysilicon exposed by the first openings. layer, that is, the first dielectric layer 4 is provided with a plurality of first windows (the first windows include a first opening and a first sintering port), and the first fine gate electrode 7 penetrates the first opening , the first main gate electrode 5 is connected to the first doped polysilicon layer 3 through the first sintering port.

In this application, the first main gate electrode 5 and the first fine gate electrode 7 have a double-layer or multi-layer structure, and the number of layers of the first main gate electrode 5 is greater than the number of layers of the first fine gate electrode 7 . The first fine gate electrode 7 may include at least two or a combination of aluminum, copper, silver, gold and/or nickel, tungsten, titanium, and cobalt. The first main gate electrode 5 includes nickel (Ni), copper (Cu), silver (Ag), aluminum (Al), tin (Sn), zinc (Zn), indium (In), titanium (Ti) and At least one of gold (Au) and its combinations, including but not limited to this.

Specifically, the first main gate electrode 5 includes a stacked first printed and sintered layer and a first metal layer. The first printed and sintered layer extends through the first dielectric layer 4 into the first doped polysilicon. Layer 3, and in the first doped polysilicon layer 3, there are the crystalline first metal nanoparticles 6 at the interface with the first printed and sintered layer; the first metal layer is disposed on the The first printed sintering layer is on a side surface facing away from the first doped polysilicon layer 3 . The first metal layer may be a stack of multiple metal layers. The metal contained in the first printing and sintering layer is different from that of the first metal layer. For example, the metal in the first printing and sintering layer is silver, and the metal in the first metal layer can be Ni/Cu/ Sn, this setting can save the high-cost amount of silver and reduce the cost of electrode materials. The first fine gate electrode 7 may be a stack of multiple metal layers. The first metal layer may be the same as the first fine gate electrode 7 .

Specifically, the electrode paste forming the first printed sintering layer is silver paste or aluminum paste.

Specifically, the electrode paste forming the first metal layer is silver paste, aluminum paste, silver-aluminum paste, copper paste or nickel paste.

Specifically, the electrode paste forming the first fine gate electrode 7 is silver paste, aluminum paste, silver-aluminum paste, copper paste or nickel paste.

In this application, as shown in FIG. 5 , the first main gate electrode 5 includes a plurality of first connection points 14 and a plurality of first connection gate lines 15 , and two adjacent first connection points 14 pass through all the first connection points 14 . The first connection gate lines 15 are connected, that is, the first connection points 14 and the first connection gate lines 15 are connected and extended in sequence to form the first main gate electrode 5; a plurality of the first main gate electrodes 5 parallel and equally spaced settings.

Specifically, the width of the first connection point 14 is greater than the width of the first connection grid line 15. The first connection point 14 is arranged discontinuously in a point shape, with a single area of 0.5-10 mm ² . The first connection point 14 is a welding point, and the cross section of the first connection point 14 can be a rectangular, circular, elliptical or other geometric shape. The specific size of the first connection point 14 may be, for example, 1.2mm*1mm, 0.7mm*0.8mm, or 1mm*0.5mm.

Specifically, a plurality of first fine gate electrodes 7 are arranged in parallel and at equal intervals, and the first fine gate electrodes 7 include a plurality of first fine gate lines spaced apart by the first main gate electrodes 5 , and the Both ends of the first thin gate line are connected to the first main gate electrode 5. Specifically, both ends of the first thin gate line are connected to the first connection gate line 15, and part of the first thin gate line is connected to the first connection gate line 15. Both ends of the gate line are connected to the first connection point 14 .

The first fine gate electrode 7 vertically intersects the first main gate electrode 5 .

In this application, as shown in Figure 6, the first main gate electrode 5 also includes a first auxiliary electrode 18. The first auxiliary electrode 18 is located between the first main gate electrode 5 and the first fine gate. At the intersection of the electrodes 7, one end of the first auxiliary electrode 18 is connected to the first connection point 14 or the first connection grid line 15, and the other end is connected to the first thin grid line; the first auxiliary electrode 18 The arrangement of the electrode 18 can strengthen the connection between the first fine grid electrode 7 and the first main grid electrode 5 , avoid or reduce the possibility of the first fine grid electrode 7 being disconnected by welding, and improve the performance and reliability of the solar cell.

Specifically, the shape of the first auxiliary electrode 18 may be arc-shaped, V-shaped, U-shaped, etc., including but not limited to these. Preferably, the first auxiliary electrode 18 is arc-shaped, and the cross-sectional area of the first auxiliary electrode 18 in the direction perpendicular to the silicon substrate is away from the first main gate electrode 5 and close to the first fine gate. The direction of the electrode 7 gradually decreases; that is, the cross-sectional area of the first auxiliary electrode 18 in the direction perpendicular to the silicon substrate decreases in the direction away from the first connection point 14 or the first connection gate line 15 the trend of.

The plurality of first metal nanoparticles 6 in the crystalline state have a relatively low resistance compared to the first doped polysilicon layer 3 made of doped polysilicon. Since the crystalline first metal nanoparticles 6 are located at the interface between the first doped polysilicon layer 3 and the first main gate electrode 5 , they pass through the tunnel layer 2 from the silicon substrate 1 Carriers (eg, electrons) moving to the first doped polysilicon layer 3 may directly move (contact) to the first main gate electrode 5 through the first metal nanoparticles 6 in the crystalline state, or may be in the crystalline state. a multi-step transition between the first metal nanoparticle 6 and the crystalline first metal nanoparticle 6 (tunneling through the glass layer between the crystalline first metal nanoparticle 6 and the first main gate electrode 5 ) and Move to the first electrode. The crystalline first metal nanoparticles 6 can therefore be used to help carriers move to the first electrode more easily.

Specifically, during the preparation process of the first main gate electrode 5, a first printed electrode slurry is printed on the first dielectric layer 4, and through sintering, the first printed electrode slurry burns through the first main gate electrode 5. A dielectric layer 4 is in contact with the first doped polysilicon layer 3. The metal material in the first printed electrode paste is dissolved into the glass frit, grows onto the first doped polysilicon layer 3 through the growth of the glass, and is recrystallized. Crystalline first metal nanoparticles 6 are formed, so the crystalline first metal nanoparticles 6 include the same metal as the metal material in the first main gate electrode 5; if the first printed electrode paste For example, if silver (Ag) is included, the crystalline first metal nanoparticles 6 may also include silver (Ag).

In addition, the metal morphology and distribution in the crystalline first metal nanoparticles 6 are different from the metal in the first printed sintering layer. For example, the metal in the crystalline first metal nanoparticles 6 is discretely distributed in an island shape in the first printing sintering layer. The interface between the doped polysilicon layer 3 and the first main gate electrode 5 (that is, the interface between the first doped polysilicon layer 3 and the first connection point 14, the first connection gate line 15, the first auxiliary gate The intersection of lines), and the metal in the first printed sintering layer is combined with the glass body after heat treatment. There are many formed in the first printed sintering layer due to the volatilization of the solvent in the first printed electrode paste. holes, which are filled by the subsequently deposited first metal layer.

The plurality of crystalline first metal nanoparticles 6 are not located in the tunnel layer 2 to prevent the crystalline first metal nanoparticles 6 from damaging the tunnel layer 2 or the silicon substrate 1 and reducing the performance of the solar cell. .

In this application, the height of the second fine gate electrode 12 may be 15 microns or less, for example less than 10 microns, and the width is less than 35 microns. The height difference between the second main gate electrode 11 and the second fine gate electrode 12 is 5-35 microns. Such a setup can reduce the area and amount of electrode setup and production costs by depositing metal electrodes with low resistivity.

The second main gate electrode 11 burns through the second dielectric layer 9 and extends into the doping layer 8 , and the opening burned in the second dielectric layer 9 is a second sintering port. A plurality of second openings penetrating the second dielectric layer 9 are also opened on the second dielectric layer 9; the second fine gate electrode 12 is electroplated on the doped layer 8 exposed by the second openings. on the second dielectric layer 9, that is, a plurality of second openings (the second openings include second openings and second sintering ports) are provided on the second dielectric layer 9, and the second thin gate electrode 12 penetrates the second openings, The second main gate electrode 11 is connected to the doping layer 8 through the second sintering port.

In this application, the second main gate electrode 11 and the second fine gate electrode 12 have a double-layer or multi-layer structure, and the number of layers of the second main gate electrode 11 is greater than the number of layers of the second fine gate electrode 12 . The second fine gate electrode 12 may include at least two or a combination of at least two of aluminum, copper, silver, gold, and/or nickel, tungsten, titanium, and cobalt. The second main gate electrode 11 includes nickel (Ni), copper (Cu), silver (Ag), aluminum (Al), tin (Sn), zinc (Zn), indium (In), titanium (Ti) and At least one of gold (Au) and its combinations, including but not limited to this.

Specifically, the second main gate electrode 11 includes a stacked second printed and sintered layer and a second metal layer, and the second printed and sintered layer extends through the second dielectric layer 9 and into the doped layer 8, And in the doped layer 8, there are the second metal nanoparticles in the crystalline state at the interface with the second printed and sintered layer; the second metal layer is disposed at a distance from the second printed and sintered layer. on one side surface of the doped layer 8. The second metal layer may be a stack of multiple metal layers. The metal contained in the second printed and sintered layer is different from that of the second metal layer. For example, the metal in the second printed and sintered layer is silver, and the metal in the second metal layer can be Ni/Cu/ Sn, this setting can save the high-cost amount of silver and reduce the cost of electrode materials. The second fine gate electrode 12 may be a stack of multiple metal layers. The second metal layer may be the same as the second fine gate electrode 12 .

Specifically, the electrode paste forming the second printed sintering layer is silver paste or aluminum paste.

Specifically, the electrode paste forming the second metal layer is silver paste, aluminum paste, silver-aluminum paste, copper paste or nickel paste.

Specifically, the electrode paste forming the second fine gate electrode 12 is silver paste, aluminum paste, silver-aluminum paste, copper paste or nickel paste.

In this application, as shown in FIG. 5 , the second main gate electrode 11 includes a plurality of second connection points 16 and a plurality of second connection gate lines 17 , and two adjacent second connection points 16 pass through all the second connection points 16 . The second connection gate lines 17 are connected, that is, the second connection points 16 and the second connection gate lines 17 are connected and extended in sequence to form the second main gate electrode 11; a plurality of the second main gate electrodes 11 parallel and equally spaced settings.

Specifically, the width of the second connection point 16 is greater than the width of the second connection grid line 17. The second connection point 16 is arranged discontinuously in a point shape, with a single area of 0.5-10 mm ² . The second connection point 16 is a welding point, and the cross section of the second connection point 16 can be a rectangular, circular, oval or other geometric shape. The specific size of the second connection point 16 may be, for example, 1.2mm*1mm, 0.7mm*0.8mm, or 1mm*0.5mm.

A plurality of second fine gate electrodes 12 are arranged in parallel and at equal intervals. The second fine gate electrodes 12 include a plurality of second fine gate lines spaced apart by the second main gate electrodes 11 , and the second fine gate electrodes 12 are spaced apart from each other. Both ends of the gate line are connected to the second main gate electrode 11. Specifically, both ends of part of the second thin gate line are connected to the second connecting gate line 17, and part of the second thin gate line Both ends are connected to the second connection point 16 .

The second fine gate electrode 12 vertically intersects the second main gate electrode 11 .

In this application, the second main gate electrode 11 also includes a second auxiliary electrode located at the intersection of the second main gate electrode 11 and the second fine gate electrode 12. One end of the second auxiliary electrode is connected to the second connection point 16 or the second connection gate line 17, and the other end is connected to the second fine gate line; the arrangement of the second auxiliary electrode can strengthen the second fine gate line. The connection between the electrode 12 and the second main grid electrode 11 avoids or reduces the possibility of the second fine grid electrode 12 being disconnected by welding, thereby improving the performance and reliability of the solar cell.

Specifically, the shape of the second auxiliary electrode may be arc-shaped, V-shaped, U-shaped, etc., including but not limited to these. Preferably, the second auxiliary electrode is arc-shaped, and the cross-sectional area of the second auxiliary electrode in the direction perpendicular to the silicon substrate 1 is away from the second main gate electrode 5 and close to the second fine gate electrode. gradually decreases in the direction of 12. That is, the cross-sectional area of the second auxiliary electrode in the direction perpendicular to the silicon substrate 1 tends to decrease in the direction away from the second connection point 16 or the second connection gate line 17 .

The projections of the first main gate electrode 5 and the second main gate electrode 11, and the first fine gate electrode 7 and the second fine gate electrode 12 in the thickness direction of the silicon substrate 1 do not overlap, so that the first window can be opened. and the second opening is asymmetrically arranged to avoid significantly reducing the mechanical strength of the silicon substrate 1 by symmetrically arranging the openings on both sides of the substrate during the opening process.

When the second main gate electrode 11 includes metallic silver, there are crystalline second metal nanoparticles in the doped layer 8 at the interface with the second main gate electrode 11 . The plurality of said crystalline second metal nanoparticles have a relatively low resistance compared to the doped layer 8 made of doped polysilicon. Since the crystalline second metal nanoparticles are located at the interface with the second main gate electrode 11 in the doping layer 8 , they move from the silicon substrate 1 through the tunneling layer 2 to the Carriers (eg, electrons) of the doping layer 8 may directly move (contact) to the second main gate electrode 11 through the second metal nanoparticles in the crystalline state, or may interact with the second main gate electrode 11 in the crystalline state. A multi-step transition between the second metal nanoparticles (tunneling through the glass layer between the crystalline second metal nanoparticles and the second main gate electrode 11) and moves to the second electrode. The crystalline second metal nanoparticles can therefore be used to help carriers move to the second electrode more easily.

Specifically, during the preparation process of the second main gate electrode 11, a second printed electrode paste is printed on the second dielectric layer 9, and through sintering, the second printed electrode paste burns through the second main gate electrode 11. The second dielectric layer 9 is in contact with the doped layer 8. The metal material in the second printed electrode paste is dissolved into the glass frit, grows on the doped layer 8 through the glass, and recrystallizes to form the second crystalline layer. Metal nanoparticles, so the crystalline second metal nanoparticles include the same metal as the metal material in the second main gate electrode 11; if the second printed electrode paste includes, for example, silver (Ag), then The crystalline second metal nanoparticles may also include silver (Ag).

In addition, the metal morphology and distribution in the crystalline second metal nanoparticles are different from the metal in the second printed sintering layer. For example, the metal in the crystalline second metal nanoparticles is discretely distributed in the doping layer 8 in an island shape. The interface between the doped layer 8 and the second main gate electrode 11 (that is, the interface between the doped layer 8 and the second connection point 16, the second connection gate line 17, and the second auxiliary gate line), and the The metal in the second printed sintering layer is combined with the glass body after heat treatment. Many holes are formed in the second printed sintering layer due to the volatilization of the solvent in the second printed electrode paste. These holes are subsequently deposited. The second metal layer is filled.

The plurality of crystalline second metal nanoparticles are not located in the tunnel layer 2 to prevent the crystalline second metal nanoparticles from damaging the tunnel layer 2 or the silicon substrate 1 and reducing the performance of the solar cell.

Further, when the second main gate electrode 11 includes metallic aluminum, there is a eutectic layer 13 and a local back field 19 at the interface with the second main gate electrode 11 in the doped layer 8 . The eutectic layer 13 has good conductivity and is conducive to forming a strong ohmic contact. The local back field 19 can block the movement of electrons, reduce the recombination rate on the surface, reduce light penetration into the silicon substrate 1 and enhance the absorption of long waves.

Specifically, during sintering, p-type aluminum doping infiltrates to form a layer of p+-type Si that is originally doped with boron and forms a layer of p+-type Si several microns thick as a local back field 19 to reduce the back surface recombination rate and improve The open circuit voltage Voc of the cell; due to the poor absorption coefficient of the silicon substrate 1, when the thickness becomes thinner, the absorption of incident light by the second dielectric layer 9 decreases. At this time, the existence of the local back field 19 can reach the silicon substrate 1 Deeper long-wave light absorption is helpful, so the impact of short-circuit current density is more obvious; the energy level difference between p and p+ can also increase the open circuit voltage Voc, and p+ can form a low-resistance ohmic contact, so the fill factor FF can also be improved.

In this application, the first solar cell preparation method includes the following steps:

Step 1: Provide silicon substrate 1.

Step 2: Form a doped layer 8 on one side surface (front surface or front surface) of the silicon substrate.

Step 3: Set a tunneling layer 2 on one side surface (back surface or rear surface) of the silicon substrate 1 .

Step 4: Deposit the first doped polysilicon layer 3 on the side of the tunnel layer 2 facing away from the silicon substrate 1 .

Step 5: Deposit a first dielectric layer 4 on the side of the first doped polysilicon layer 3 facing away from the tunnel layer 2 .

Step 6: Print the first printed electrode paste on the side of the first dielectric layer 4 away from the first doped polysilicon layer 3 to form a first printed sintering layer, and the first printed electrode paste burns through the The first dielectric layer 4 is connected to the first doped polysilicon layer 3, and crystalline first metal nanoparticles are formed at the interface between the first doped polysilicon layer 3 and the first printing and sintering layer. 6.

Step 7: Electroplating and depositing metal on the surface of the first printing and sintering layer to form a first metal layer. The first printing and sintering layer and the first metal layer constitute the first main gate electrode 5 .

Step 8: Provide a plurality of first openings penetrating the first dielectric layer 4 on the first dielectric layer 4, electroplating metal in the first openings to form the first fine gate electrode 7, and each of the first thin gate electrodes 7 is formed. The first fine gate electrode 7 intersects and is electrically connected to each of the first main gate electrodes 5 , and the first fine gate electrode 7 and the first main gate electrode 5 constitute a first electrode.

Step 9: Deposit a second dielectric layer 9 on the side of the doped layer 8 facing away from the silicon substrate 1 .

Step 10: Print a second printed electrode paste on the side of the second dielectric layer 9 away from the doped layer 8, form a second printed sintering layer through sintering, and burn through the second printed electrode paste. The second dielectric layer 9 is connected to the doped layer 8 and forms a crystalline second metal nanoparticle or eutectic layer 13 at the interface between the doped layer 8 and the second printed sintering layer. and local backfield19.

Step 11: Electroplating and depositing metal on the surface of the second printed and sintered layer to form a second metal layer. The second printed and sintered layer and the second metal layer constitute the second main gate electrode 11 .

Step 12: Provide a plurality of second openings penetrating the second dielectric layer 9 on the second dielectric layer 9 , electroplating metal in the second openings to form a second fine gate electrode 12 , each of the second thin gate electrodes 12 is formed. Two fine gate electrodes 12 intersect and are electrically connected to each of the second main gate electrodes 11 to form a second electrode.

Specifically, in step one, the silicon substrate 1 can be obtained by cleaning, alkali texturing and edge etching of the silicon wafer. After texturing, a pyramid texture is formed on the front surface (front surface) of the silicon wafer.

Specifically, in step two, boron on the front side of the silicon substrate is diffused to form a doped layer;

The boron diffusion can be: using a boron source to diffuse the silicon substrate under high temperature conditions, and through the boron diffusion, a doping layer is formed on the front side.

The boron source for boron diffusion may include boron tribromide, the diffusion temperature of the boron diffusion ranges from 950 to 1000°C, and the diffusion time ranges from 1.5 to 2.5 hours.

Specifically, in step three, a tunnel layer 2 is grown on the back side of the silicon substrate 1 using thermal oxidation.

Specifically, in step four, LPCVD is used to pass silane and phosphorane to deposit an impurity-doped amorphous silicon film on the side of the tunnel layer 2 facing away from the silicon substrate 1, and then anneal the amorphous silicon film. , where the annealing temperature is controlled at 800-1000°C and the annealing time is controlled at 30 minutes, thereby crystallizing amorphous silicon into polysilicon and forming the first doped polysilicon layer.

When forming the first doped polysilicon layer, an amorphous silicon film is formed on the doped layer. The amorphous silicon film is removed. Specifically, a chain type single-sided etching equipment is used, and an HF solution is first used to remove the amorphous silicon. The oxide layer on the surface of the film is etched away from the amorphous silicon film coated on the front using KOH solution.

Specifically, in step five, a passivation film is deposited on the side of the first doped polysilicon layer 3 away from the tunnel layer 2 using tube PECVD to form the first dielectric layer 4 .

Specifically, in step six, a first printed electrode paste is printed on the first dielectric layer 4 , and the first printed electrode paste burns through the first dielectric layer 4 and the first doped material. In contact with the polysilicon layer 3, the metal material in the first printed electrode paste is dissolved into the glass frit, grows onto the first doped polysilicon layer 3 through the growth of the glass, and recrystallizes to form crystalline first metal nanoparticles 6, Therefore, the crystalline first metal nanoparticles 6 include the same metal as the metal material in the first main gate electrode 5; if the first printed electrode paste includes, for example, silver (Ag), the crystalline The first metal nanoparticles 6 may also include silver (Ag).

In addition, the metal morphology and distribution in the crystalline first metal nanoparticles 6 are different from the metal in the first printed sintering layer. For example, the metal in the crystalline first metal nanoparticles 6 is discretely distributed in an island shape in the first printing sintering layer. The interface between the doped polysilicon layer 3 and the first main gate electrode 5 (that is, the interface between the first doped polysilicon layer 3 and the first connection point 14, the first connection gate line 15, the first auxiliary gate The intersection of lines), and the metal in the first printed sintering layer is combined with the glass body after heat treatment. There are many formed in the first printed sintering layer due to the volatilization of the solvent in the first printed electrode paste. holes, which are filled by the subsequently deposited first metal layer.

The plurality of crystalline first metal nanoparticles 6 are not located in the tunnel layer 2 to prevent the crystalline first metal nanoparticles 6 from damaging the tunnel layer 2 or the silicon substrate 1 and reducing the performance of the solar cell. .

The first printed electrode paste may be silver paste or aluminum paste.

The sintering temperature is 750°C-900°C, and the heat treatment temperature is 250°C-500°C. For example, the sintering temperature may be 750°C, 800°C, 850°C or 900°C.

Specifically, the step of opening the first opening on the first dielectric layer 4 and the step of forming the first main gate electrode 5 on the first dielectric layer 4 may be in no particular order, that is, the first main gate electrode 5 may be formed first. The first main gate electrode 5 may be formed first, and then the first main gate electrode 5 may be formed, and then the first opening may be opened on the first dielectric layer 4 .

Specifically, step eight also includes heat treatment of the deposited metal, and the temperature of the heat treatment may be 250°C, 300°C, 350°C, 400°C, 450°C or 500°C.

Specifically, in steps seven and eight, the electrode slurry used to form the first metal layer is the same as the first fine gate electrode 7 slurry. The first fine gate electrode 7 paste may be silver paste, aluminum paste, silver-aluminum paste, copper paste or nickel paste.

Specifically, in step nine, a passivation film is deposited on the side of the doped layer 8 away from the tunnel layer 2 using tube PECVD to form the second dielectric layer 9 .

Further, before step ten, it also includes depositing an anti-reflective layer 10 on a side of the second dielectric layer 9 away from the doped layer 8 . When light shines on the solar cell, the anti-reflection layer 10 can reduce the reflection of light and enhance the utilization of light.

Further, in step ten, after the anti-reflective layer 10 is deposited on the second dielectric layer 9 , the second main gate electrode 11 burns through the anti-reflective layer 10 and the second dielectric layer 9 . into the doped layer 8.

Specifically, in step ten, when the second printed electrode paste includes metallic silver, after the second printed electrode paste is printed on the second dielectric layer 9, the second printed electrode paste After burning through the second dielectric layer 9 and contacting the doped layer 8, the metal material in the second printed electrode paste is dissolved into the glass frit, and is formed by recrystallization through the growth of the glass onto the doped layer 8. The crystalline second metal nanoparticles, therefore, the crystalline second metal nanoparticles include the same metal silver (Ag) as the metal material in the second main gate electrode 11 .

In addition, the metal morphology and distribution in the crystalline second metal nanoparticles are different from the metal in the second printed sintering layer. For example, the metal in the crystalline second metal nanoparticles is discretely distributed in the doping layer 8 in an island shape. The interface between the doped layer 8 and the second main gate electrode 11 (that is, the interface between the doped layer 8 and the second connection point 16, the second connection gate line 17, and the second auxiliary gate line), and the The metal in the second printed sintering layer is combined with the glass body after heat treatment. Many holes are formed in the second printed sintering layer due to the volatilization of the solvent in the second printed electrode paste. These holes are subsequently deposited. The second metal layer is filled. The plurality of crystalline second metal nanoparticles are not located in the tunnel layer 2 to prevent the crystalline second metal nanoparticles from damaging the tunnel layer 2 or the silicon substrate 1 and reducing the performance of the solar cell.

Specifically, in step ten, when the second main gate electrode 11 includes metal aluminum, after the second printed electrode paste is printed on the second dielectric layer 9, the second printed electrode paste is The metal (such as Al) in the electrode paste is a trivalent element, and silicon is a tetravalent element. During the heat treatment, aluminum diffuses into the doped layer 8 and forms a eutectic at the interface with the second main gate electrode 11 Layer 13 and local backfield 19. Within the doped layer 8 , there is no eutectic layer 13 and local back field 19 at the interface with the second fine gate electrode 12 . The eutectic layer 13 has good conductivity and is conducive to forming a strong ohmic contact. The local back field 19 can block the movement of electrons, reduce the recombination rate on the surface, reduce light penetration into the silicon substrate 1 and enhance the absorption of long waves.

Specifically, the anti-reflection layer 10 is provided with a third opening that penetrates the second opening, and the second fine gate electrode 12 penetrates the second opening and the third opening to be connected to the doped layer 8 .

The sintering temperature is 750°C-900°C, and the heat treatment temperature is 250°C-500°C. For example, the sintering temperature may be 750°C, 800°C, 850°C or 900°C.

Specifically, step 12 also includes performing heat treatment on the deposited metal, and the temperature of the heat treatment may be 250°C, 300°C, 350°C, 400°C, 450°C or 500°C.

The second printed electrode paste may be silver paste or aluminum paste.

Specifically, in steps 11 and 12, the electrode slurry used to form the second metal layer is the same as the second fine gate electrode 12 slurry. The second fine gate electrode 12 paste may be silver paste, aluminum paste, silver-aluminum paste, copper paste or nickel paste.

Further specifically, the first fine gate electrode 7 slurry may be the same as the second fine gate electrode 12 slurry.

In this application, the first solar cell preparation method includes the following steps:

Step 1: Provide silicon substrate 1.

Specifically, the silicon substrate 1 can be obtained by cleaning, alkali texturing and edge etching of the silicon wafer. After texturing, a pyramid texture is formed on the front surface (front surface) of the silicon wafer.

Step 2: Form a doping layer 8 on one side surface (front surface or front surface) of the silicon substrate 1 .

Boron diffusion on the front side of the silicon substrate forms a doped layer;

The boron diffusion can be: using a boron source to diffuse the silicon substrate under high temperature conditions, and through the boron diffusion, a doping layer is formed on the front side.

The boron source for boron diffusion may include boron tribromide, the diffusion temperature of the boron diffusion ranges from 950 to 1000°C, and the diffusion time ranges from 1.5 to 2.5 hours.

Step 3: Set a tunneling layer 2 on one side surface (back surface or rear surface) of the silicon substrate 1 .

Specifically, a tunnel layer 2 is grown on the back side of the silicon substrate 1 using thermal oxidation.

Step 4: Deposit the first doped polysilicon layer 3 on the side of the tunnel layer 2 facing away from the silicon substrate 1 .

Specifically, LPCVD is used to pass silane and phosphorane to deposit an impurity-doped amorphous silicon film on the side of the tunnel layer 2 facing away from the silicon substrate 1, and then anneal the amorphous silicon film, where the annealing temperature is controlled At 800-1000°C, the annealing time is controlled at 30 minutes, thereby crystallizing amorphous silicon into polysilicon to form the first doped polysilicon layer.

When forming the first doped polysilicon layer, an amorphous silicon film is formed on the doped layer. The amorphous silicon film is removed. Specifically, a chain type single-sided etching equipment is used, and an HF solution is first used to remove the amorphous silicon. The oxide layer on the surface of the film is etched away from the amorphous silicon film coated on the front using KOH solution.

Step 5: Deposit a first dielectric layer 4 on the side of the first doped polysilicon layer 3 facing away from the tunnel layer 2 .

Specifically, a passivation film is deposited on the side of the first doped polysilicon layer 3 away from the tunnel layer 2 using tube PECVD to form the first dielectric layer 4 .

Step 6: Print the first printed electrode slurry on the side of the first dielectric layer 4 away from the first doped polysilicon layer 3, and sinter it to form a first printed sintered layer. The first printed electrode slurry burns through The first dielectric layer 4 extends into the first doped polysilicon layer 3 and forms crystalline first metal nanometers at the interface between the first doped polysilicon layer 3 and the first printing and sintering layer. Particle 6.

Specifically, a first printed electrode paste is printed on the first dielectric layer 4, and the first printed electrode paste burns through the first dielectric layer 4 and contacts the first doped polysilicon layer 3, The metal material in the first printed electrode slurry dissolves into the glass frit, grows onto the first doped polysilicon layer 3 through glass, and recrystallizes to form crystalline first metal nanoparticles 6, so the crystalline state The first metal nanoparticles 6 include the same metal as the metal material in the first main gate electrode 5; if the first printed electrode paste includes, for example, silver (Ag), the crystalline first metal nanoparticles 6 Silver (Ag) may also be included.

In addition, the metal morphology and distribution in the crystalline first metal nanoparticles 6 are different from the metal in the first printed sintering layer. For example, the metal in the crystalline first metal nanoparticles 6 is discretely distributed in an island shape in the first printing sintering layer. The interface between the doped polysilicon layer 3 and the first main gate electrode 5 (that is, the interface between the first doped polysilicon layer 3 and the first connection point 14, the first connection gate line 15, the first auxiliary gate The intersection of lines), and the metal in the first printed sintering layer is combined with the glass body after heat treatment. There are many formed in the first printed sintering layer due to the volatilization of the solvent in the first printed electrode paste. holes, which are filled by the subsequently deposited first metal layer.

The plurality of crystalline first metal nanoparticles 6 are not located in the tunnel layer 2 to prevent the crystalline first metal nanoparticles 6 from damaging the tunnel layer 2 or the silicon substrate 1 and reducing the performance of the solar cell. .

The sintering temperature is 750°C-900°C. For example, the sintering temperature may be 750°C, 800°C, 850°C or 900°C.

The first printed electrode paste may be silver paste or aluminum paste.

Step 7: Electroplating and depositing metal on the surface of the first printing and sintering layer to form a first metal layer. The first printing and sintering layer and the first metal layer constitute the first main gate electrode 5 .

Step 8: Provide a plurality of first openings penetrating the first dielectric layer 4 on the first dielectric layer 4, electroplating metal in the first openings, forming the first fine gate electrode 7 through heat treatment, and The first fine gate electrode 7 is connected to the first main gate electrode 5 , and the first fine gate electrode 7 and the first main gate electrode 5 constitute a first electrode.

The temperature of the heat treatment is 250°C-500°C. For example, the temperature of the heat treatment may be 250°C, 300°C, 350°C, 400°C, 450°C or 500°C.

The electrode paste used to form the first metal layer is the same as the first fine gate electrode 7 paste. The first fine gate electrode 7 paste may be silver paste, aluminum paste, silver-aluminum paste, copper paste or nickel paste.

Step 9: Deposit a second dielectric layer 9 on the side of the doped layer 8 facing away from the silicon substrate 1 .

Specifically, in step nine, a passivation film is deposited on the side of the doped layer 8 away from the tunnel layer 2 using tube PECVD to form the second dielectric layer 9 .

Further, after step nine and before step ten, it further includes depositing an anti-reflection layer 10 on a side of the second dielectric layer 9 away from the doped layer 8 . When light shines on the solar cell, the anti-reflection layer 10 can reduce the reflection of light and enhance the utilization of light.

Step 10: Print a second printed electrode paste on the side of the second dielectric layer 9 away from the doped layer 8, and sinter it to form a second printed sintering layer. The second printed electrode paste burns through the first Two dielectric layers 9 extend into the doped layer 8 .

Further, after the anti-reflection layer 10 is deposited on the second dielectric layer 9 , the second main gate electrode 11 burns through the anti-reflection layer 10 and the second dielectric layer 9 extends into the doped Layer 8.

Specifically, when the second printed electrode paste includes metallic silver, after the second printed electrode paste is printed on the second dielectric layer 9 , the second printed electrode paste burns through the second dielectric layer 9 . The second dielectric layer 9 is in contact with the doped layer 8. The metal material in the second printed electrode paste is dissolved into the glass frit, grows on the doped layer 8 through the glass, and recrystallizes to form the second crystalline layer. The metal nanoparticles, therefore the crystalline second metal nanoparticles include the same metal silver (Ag) as the metal material in the second main gate electrode 11 .

In addition, the metal morphology and distribution in the crystalline second metal nanoparticles are different from the metal in the second printed sintering layer. For example, the metal in the crystalline second metal nanoparticles is discretely distributed in the doping layer 8 in an island shape. The interface between the doped layer 8 and the second main gate electrode 11 (that is, the interface between the doped layer 8 and the second connection point 16, the second connection gate line 17, and the second auxiliary gate line), and the The metal in the second printed sintering layer is combined with the glass body after heat treatment. Many holes are formed in the second printed sintering layer due to the volatilization of the solvent in the second printed electrode paste. These holes are subsequently deposited. The second metal layer is filled. The plurality of crystalline second metal nanoparticles are not located in the tunnel layer 2 to prevent the crystalline second metal nanoparticles from damaging the tunnel layer 2 or the silicon substrate 1 and reducing the performance of the solar cell.

Specifically, in step ten, when the second main gate electrode 11 includes metal aluminum, after the second printed electrode paste is printed on the second dielectric layer 9, the second printed electrode paste is The metal (such as Al) in the electrode paste is a trivalent element, and silicon is a tetravalent element. During the heat treatment, aluminum diffuses into the doped layer 8 and forms a eutectic at the interface with the second main gate electrode 11 Layer 13 and local backfield 19. Within the doped layer 8 , there is no eutectic layer 13 and local back field 19 at the interface with the second fine gate electrode 12 .

The eutectic layer 13 has good conductivity and is conducive to forming a strong ohmic contact. The local back field 19 can block the movement of electrons, reduce the recombination rate on the surface, reduce light penetration into the silicon substrate 1 and enhance the absorption of long waves.

Specifically, the anti-reflection layer 10 is provided with a third opening that penetrates the second opening, and the second fine gate electrode 12 penetrates the second opening and the third opening to be connected to the doped layer 8 .

Specifically, the sintering temperature is 750°C-900°C. For example, the sintering temperature may be 750°C, 800°C, 850°C or 900°C.

The second printed electrode paste may be silver paste or aluminum paste.

Step 11: Electroplating and depositing metal on the surface of the second printed and sintered layer to form a second metal layer. The second printed and sintered layer and the second metal layer constitute the second main gate electrode 11 .

Specifically, the temperature of the heat treatment is 250°C-500°C. For example, the temperature of the heat treatment may be 250°C, 300°C, 350°C, 400°C, 450°C or 500°C.

Step 12: Provide a plurality of second openings penetrating the second dielectric layer 9 on the second dielectric layer 9 , electroplating metal in the second openings, and forming the second fine gate electrode 12 through the heat treatment. The second fine gate electrode 12 is connected to the second main gate electrode 11 to form a second electrode.

Specifically, the electrode paste used to form the second metal layer is the same as the second fine gate electrode 12 paste. The second fine gate electrode 12 paste may be silver paste, aluminum paste, silver-aluminum paste, copper paste or nickel paste.

Further specifically, the first fine gate electrode 7 slurry may be the same as the second fine gate electrode 12 slurry.

"Second Solar Cell"

As shown in Figure 2, the solar cell provided by this application includes a silicon substrate 1, a first electrode and a second electrode. A second dielectric layer 9 is provided on the front side of the silicon substrate 1. A tunnel layer 2, a first doped polysilicon layer 3, and a first dielectric layer 4 are sequentially stacked on the back side of the silicon substrate 1. The first electrode penetrates the first dielectric layer 4 and extends into the first Doped polysilicon layer 3. There are crystalline first metal nanoparticles 6 at the interface between the first doped polysilicon layer 3 and the first electrode. The second electrode penetrates the first dielectric layer 4 and is connected to the back surface of the silicon substrate 1 .

Specifically, the first electrode includes a plurality of first main gate electrodes 5 and a plurality of first fine gate electrodes 7, each of the first main gate electrodes 5 intersects with each of the first fine gate electrodes 7 and Electrical connection. There are crystalline first metal nanoparticles 6 at the interface between the first doped polysilicon layer 3 and the first main gate electrode 5 . There are no crystalline first metal nanoparticles 6 at the interface between the first doped polysilicon layer 3 and the first fine gate electrode 7 .

Specifically, the second electrode includes a second main gate electrode 11 and a second fine gate electrode 12, and the second main gate electrode 11 and the second fine gate electrode 12 intersect and are electrically connected.

Specifically, on the back side of the silicon substrate 1, the tunneling layer 2 includes a plurality of tunneling units arranged at intervals. The area between adjacent tunneling units is a first area, and the first dielectric layer 4 covers the surface of the first doped polysilicon layer 3 and the side surfaces of the first doped polysilicon layer 3 in the first region, the side surfaces of the tunneling unit and the surface of the silicon substrate 1 . The second main gate electrode 11 penetrates the first dielectric layer 4 in the first region and is connected to the silicon substrate 1 .

Further, when the second main gate electrode 11 includes metallic silver, there are crystalline second metal nanoparticles in the silicon substrate 1 at the interface with the second main gate electrode 11 . In the silicon substrate 1 , there are no crystalline second metal nanoparticles at the interface with the second fine gate electrode 12 .

Further, when the second main gate electrode 11 includes metallic aluminum, there is a eutectic layer 13 and a local back field 19 at the interface with the second main gate electrode 11 in the silicon substrate 1 . In the silicon substrate 1 , there is no eutectic layer 13 and local back field 19 at the interface with the second fine gate electrode 12 .

Specifically, as shown in FIG. 4 , a plurality of first fine gate electrodes 7 are arranged at equal intervals. The first fine gate electrode 7 includes a plurality of first main gate electrodes 5 and second main gate electrodes 11 . First thin gate lines are spaced apart, and one end of the first thin gate line is connected to the first main gate electrode 5 , and the other end is spaced apart by the second main gate electrode 11 . The first fine gate electrode 7 vertically intersects the first main gate electrode 5 .

A plurality of second fine gate electrodes 12 are arranged at equal intervals, and the second fine gate electrode 12 includes a plurality of second fine gate lines spaced apart by the first main gate electrode 5 and the second main gate electrode 11, One end of the second thin gate line is connected to the second main gate electrode 11 , and the other end is separated by the first main gate electrode 5 . The second fine gate electrode 12 vertically intersects the second main gate electrode 11 .

The second fine gate electrode 12 and the first fine gate electrode 7 are alternately parallel to each other, that is, the first fine gate electrode 7 and the second fine gate electrode 12 are parallel to each other in sequence and adjacent to the first fine gate electrode. The second thin gate electrode 12 is disposed between 7 . The second main gate electrode 11 and the first main gate electrode 5 are alternately parallel to each other, that is, the first main gate electrode 5 and the second main gate electrode 11 are parallel to each other in sequence and adjacent to the first main gate electrode. The second main gate electrode 11 is disposed between 5 .

In this embodiment, the tunneling layer 2 , the first doped polysilicon layer 3 , the first dielectric layer 4 , the first electrode and the crystalline first metal nanoparticles 6 can all refer to the aforementioned method for the first solar cell. For description, that is, the specific structures and materials of the tunneling layer 2 of the solar cell, the first doped polysilicon layer 3, the first dielectric layer 4, the first electrode and the crystalline first metal nanoparticles 6 can be referred to in The first type of solar cell is described in the section.

The material of the second electrode in this embodiment may be the same as the material of the first electrode, or may be different from the material of the first electrode. When the material of the second electrode is the same as the material of the first electrode, At the same time, reference may be made to the material description of the first electrode in the aforementioned first solar cell part. When the materials of the second electrode are different, the second printed electrode paste is silver paste or aluminum paste. The electrode paste of the second metal layer is silver paste, aluminum paste, silver-aluminum paste, copper paste or nickel paste. The electrode paste of the second fine gate electrode 12 is silver paste, aluminum paste, silver-aluminum paste, copper paste or nickel paste.

In the solar cell in this embodiment, since the second doped polysilicon layer and the second electrode are not provided on the front side of the silicon substrate 1, when light shines on the solar cell, the light can directly shine on the silicon substrate. 1, so the solar cell not only has a simple structure, but also has a high light utilization rate. In addition, since the first electrode and the second electrode are located on the same side of the silicon substrate 1, the amount of electrode slurry can be greatly reduced and the cost is low.

In this application, the second method of preparing a solar cell includes the following steps:

Step 1: Provide silicon substrate 1.

Step 2: Form a second dielectric layer 9 on one side surface (front surface or front surface) of the silicon substrate 1 .

Step 3: Provide a tunneling layer 2 on one side surface of the silicon substrate 1 .

Step 4: Deposit the first doped polysilicon layer 3 on the side of the tunnel layer 2 facing away from the silicon substrate 1 .

Step 5: Deposit a first dielectric layer 4 on the side of the first doped polysilicon layer 3 facing away from the tunnel layer 2 .

Step 6: Print the first printed electrode paste and the second printed electrode paste at intervals on the side of the first dielectric layer 4 away from the first doped polysilicon layer 3, and sinter to form the first printed and sintered layer and the second printed electrode paste. Two printed sintering layers, the first printed electrode paste burns through the first dielectric layer 4 and extends into the first doped polysilicon layer 3, and is in contact with the first doped polysilicon layer 3. Crystalline first metal nanoparticles 6 are formed at the interface of the first printed sintering layer, and the second printed electrode paste burns through the first dielectric layer 4 and is connected to the silicon substrate 1 .

Step 7: Electroplating and depositing metal on the surface of the first printing and sintering layer to form a first metal layer. The first printing and sintering layer and the first metal layer constitute the first main gate electrode 5 .

Step 8: Electroplating and depositing metal on the surface of the second printed and sintered layer to form a second metal layer. The second printed and sintered layer and the second metal layer constitute the second main gate electrode 11 .

Step 9: Provide a plurality of first openings and second openings penetrating the first dielectric layer 4 on the first dielectric layer 4, electroplating metal in the first openings and second openings, and forming them through heat treatment. The first fine gate electrode 7 and the second fine gate electrode 12 intersect and are electrically connected to the first main gate electrode 5 . The first fine gate electrode 7 and the first main gate electrode 5 intersect and are electrically connected. The main gate electrode 5 constitutes a first electrode, the second fine gate electrode 12 intersects and is electrically connected to the second main gate electrode 11 , and the second fine gate electrode 12 and the second main gate electrode 11 constitute a third electrode. Two electrodes.

Step 10: Provide a second dielectric layer 9 on the surface of the silicon substrate 1 facing away from the tunnel layer 2 .

Specifically, in step one, the silicon substrate 1 can be obtained by cleaning, alkali texturing and edge etching of the silicon wafer. After texturing, pyramid textures are formed on both sides of the silicon wafer.

Specifically, in step two, the front side of the silicon substrate is oxidized, and a silicon oxide layer is formed on the front side of the silicon substrate, that is, the silicon oxide layer is the second dielectric layer.

Specifically, in step three, the tunnel layer 2 is grown on the back side of the silicon substrate 1 using thermal oxidation.

Specifically, in step five, the first doped polysilicon layer 3 and the tunneling layer 2 are ablated at intervals on the surface of the first doped polysilicon layer 3 to expose the silicon substrate 1, thereby forming First area of multiple intervals. A first dielectric layer is deposited on the surface of the first doped polysilicon layer and the side surfaces of the first doped polysilicon layer, the side surfaces of the tunnel layer and the surface of the silicon substrate in the first region.

Further, on the surface of the first doped polysilicon layer 3, laser technology is used to ablate the first doped polysilicon layer 3 and the tunneling layer 2 at intervals to expose the silicon substrate 1, thereby forming a plurality of The first area of the interval.

Specifically, in step six, a second printed electrode slurry is printed on the surface of the first dielectric layer 4 in the first area and sintered to form a second printed sintered layer, and the second printed electrode slurry is burned through the The second dielectric layer 9 is connected to the silicon substrate 1 .

Further, when the second main gate electrode 11 slurry includes metallic silver, crystalline second metal nanoparticles are formed in the silicon substrate 1 at the interface with the second main gate electrode 11 .

Further, when the second main gate electrode 11 paste includes metallic aluminum, a eutectic layer 13 and a local back field 19 are formed in the silicon substrate 1 at the interface with the second main gate electrode 11 .

Specifically, in step eight, a plurality of second openings penetrating the first dielectric layer 4 are provided on the first dielectric layer 4 , metal is electroplated in the second openings, and a third opening is formed through the heat treatment. Two fine gate electrodes 12 are connected to the silicon substrate 1; the second fine gate electrode 12 intersects and is electrically connected to the second main gate electrode 11 to form a second electrode.

In this application, the second method of preparing a solar cell includes the following steps:

Step 1: Provide silicon substrate 1.

Step 2: Form a second dielectric layer 9 on one side surface (front surface or front surface) of the silicon substrate 1 .

Step 3: Provide a tunneling layer 2 on one side surface of the silicon substrate 1 .

Specifically, the tunnel layer 2 is grown on the back side of the silicon substrate 1 using thermal oxidation.

Step 4: Deposit the first doped polysilicon layer 3 on the side of the tunnel layer 2 facing away from the silicon substrate 1 .

Step 5: Deposit a first dielectric layer 4 on the side of the first doped polysilicon layer 3 facing away from the tunnel layer 2 .

Specifically, on the surface of the first doped polysilicon layer 3, the first doped polysilicon layer 3 and the tunneling layer 2 are ablated at intervals to expose the silicon substrate 1, thereby forming a plurality of spaced-apart third layers. a region. A first dielectric layer is deposited on the surface of the first doped polysilicon layer and the side surfaces of the first doped polysilicon layer, the side surfaces of the tunnel layer and the surface of the silicon substrate in the first region.

Further, on the surface of the first doped polysilicon layer 3, laser technology is used to ablate the first doped polysilicon layer 3 and the tunneling layer 2 at intervals to expose the silicon substrate 1, thereby forming a plurality of The first area of the interval.

Step 6: Print the first printed electrode paste and the second printed electrode paste at intervals on the side of the first dielectric layer 4 away from the first doped polysilicon layer 3, and sinter to form the first printed and sintered layer and the second printed electrode paste. Two printed sintering layers, the first printed electrode paste burns through the first dielectric layer 4 into the first doped polysilicon layer 3, and interacts with the first doped polysilicon layer 3 within the first doped polysilicon layer 3 Crystalline first metal nanoparticles 6 are formed at the junction of the printed and sintered layers, and the second printed electrode paste burns through the first dielectric layer 4 and is connected to the silicon substrate 1 .

Specifically, a second printed electrode paste is printed on the surface of the first dielectric layer 4 in the first area and sintered to form a second printed sintering layer, and the second printed electrode paste burns through the second dielectric. Layer 9 is connected to silicon substrate 1 .

Further, when the second printed electrode paste includes metallic silver, crystalline second metal nanoparticles are formed in the silicon substrate 1 at the interface with the second printed sintering layer.

Further, when the second printed electrode paste includes metallic aluminum, a eutectic layer 13 and a local back field 19 are formed in the silicon substrate 1 at the interface with the second printed sintering layer.

Step 7: Electroplating and depositing metal on the surface of the first printing and sintering layer to form a first metal layer. The first printing and sintering layer and the first metal layer constitute the first main gate electrode 5 .

Step 8: Electroplating and depositing metal on the surface of the second printed and sintered layer to form a second metal layer. The second printed and sintered layer and the second metal layer constitute the second main gate electrode 11 .

Step 9: Provide a plurality of first openings and second openings penetrating the first dielectric layer 4 on the first dielectric layer 4, electroplating metal in the first openings and second openings, and forming them through heat treatment. The first fine gate electrode 7 and the second fine gate electrode 12, and each of the first fine gate electrodes 7 intersects and is electrically connected to each of the first main gate electrodes 5. The first fine gate electrodes 7 and The first main gate electrode 5 constitutes a first electrode, each of the second fine gate electrodes 12 intersects and is electrically connected to each of the second main gate electrodes 11 , and the second fine gate electrodes 12 and the The second main gate electrode 11 constitutes a second electrode.

Specifically, a plurality of second openings penetrating the first dielectric layer 4 are provided on the first dielectric layer 4 , metal is electroplated in the second openings, and the second fine gate electrode 12 is formed through the heat treatment. , and the second fine gate electrode 12 is connected to the silicon substrate 1; each of the second fine gate electrodes 12 intersects and is electrically connected to each of the second main gate electrodes 11 to form a second electrode.

Step 10: Provide a second dielectric layer 9 on the surface of the silicon substrate 1 facing away from the tunnel layer 2 .

In this embodiment, the tunneling layer 2 , the first doped polysilicon layer 3 , the first dielectric layer 4 , the first electrode and the crystalline first metal nanoparticles 6 can all refer to the aforementioned method for the first solar cell. Description of the preparation method, that is, the materials, structure, and preparation method of the tunneling layer 2 of the solar cell, the first doped polysilicon layer 3, the first dielectric layer 4, the first electrode, and the crystalline first metal nanoparticles 6 Reference may be made to the content described in the first solar cell and its preparation method.

"The Third Solar Cell"

As shown in Figure 3, of the solar cells provided by this application, the third solar cell is a variation of the second solar cell. The solar cell includes a silicon substrate 1, a first electrode and a second electrode, and a second dielectric layer 9 is provided on the front side of the silicon substrate 1. A tunnel layer 2, a first doped polysilicon layer 3, and a first dielectric layer 4 are sequentially stacked on the back side of the silicon substrate 1. The first electrode penetrates the first dielectric layer 4 and extends into the first In the doped polysilicon layer 3; in the first doped polysilicon layer 3, there are crystalline first metal nanoparticles 6 at the interface with the first electrode.

Specifically, the first electrode includes a plurality of first main gate electrodes 5 and a plurality of first fine gate electrodes 7, each of the first main gate electrodes 5 intersects with each of the first fine gate electrodes 7 and Connection; There are crystalline first metal nanoparticles 6 at the interface between the first doped polysilicon layer 3 and the first main gate electrode 5 .

Specifically, the second electrode includes a second main gate electrode 11 and a second fine gate electrode 12, and each second main gate electrode 11 and each second fine gate electrode 12 intersect and are connected.

On the surface of the tunnel layer 2, the first doped polysilicon layer 3 includes a plurality of first doped polysilicon units arranged at intervals; the area between the adjacent first doped polysilicon units is the second doped polysilicon unit. area; a second doped polysilicon unit is provided in the second area, and a plurality of the second doped polysilicon units constitute the second doped polysilicon layer 20; the first dielectric layer 4 covers the first doped polysilicon unit The surface of the polysilicon unit and the second doped polysilicon unit.

There is a region between the first doped polysilicon unit and the second doped polysilicon unit, that is, the width of the second doped polysilicon layer 20 is smaller than the width of the second region, and the first doped polysilicon Layer 3 is not in contact with said second doped polysilicon layer 20 . The second doped polysilicon layer 20 is located in the middle of the second region.

The second main gate electrode 11 penetrates the first dielectric layer 4 and is connected to the second doped polysilicon layer 20 . The conductivity type of the second doped polysilicon layer 20 is opposite to that of the first doped polysilicon layer 3 , and the second main gate electrode 11 is different from the first main gate electrode 5 .

Further, when the second main gate electrode 11 includes metallic silver, crystalline second metal nanometers are formed in the second doped polysilicon layer 20 at the interface with the second main gate electrode 11 Particles.

Further, when the second main gate electrode 11 includes metallic aluminum, a eutectic layer 13 and a local back layer are formed at the interface with the second main gate electrode 11 in the second doped polysilicon layer 20 . Field 19.

In this embodiment, the tunneling layer 2 , the first doped polysilicon layer 3 , the first dielectric layer 4 , the first electrode and the crystalline first metal nanoparticles 6 can all refer to the aforementioned method for the first solar cell. For description, that is, the specific structures and materials of the tunneling layer 2 of the solar cell, the first doped polysilicon layer 3, the first dielectric layer 4, the first electrode and the crystalline first metal nanoparticles 6 can be referred to in The first type of solar cell is described in the section.

The material of the second electrode in this embodiment is the same as the material of the second electrode in the aforementioned second solar cell. Please refer to the content described in the aforementioned second solar cell.

In this embodiment, the positional relationship between the second electrode and the first electrode on the surface of the first dielectric layer 4 is shown in Figure 4 , and reference can be made to the content described in the second solar cell section.

In this application, the third method for preparing solar cells includes the following steps:

Step 1: Provide silicon substrate 1.

Step 2: Form a second dielectric layer 9 on one side surface (front surface or front surface) of the silicon substrate 1 .

Step 3: Set a tunneling layer 2 on one side surface (back surface or rear surface) of the silicon substrate 1 .

Step 4: Deposit first doped polysilicon units and second doped polysilicon units at intervals on the side of the tunnel layer 2 facing away from the silicon substrate 1. A plurality of the first doped polysilicon units constitute the A first doped polysilicon layer 3, and a plurality of second doped polysilicon units constitute the second doped polysilicon layer 20.

Step 5: Deposit a first dielectric layer 4 on the side of the first doped polysilicon layer 3 and the second doped polysilicon layer 20 away from the tunnel layer 2 .

Step 6: Print the first printed electrode slurry on the side of the first dielectric layer 4 away from the first doped polysilicon layer 3, and sinter to form a first printed and sintered layer. The first printed electrode slurry burns through The first dielectric layer 4 is connected to the first doped polysilicon layer 3 and forms crystalline first metal nanometers at the interface between the first doped polysilicon layer 3 and the first printing and sintering layer. Particle 6.

Step 7: Electroplating and depositing metal on the surface of the first printing and sintering layer to form a first metal layer. The first printing and sintering layer and the first metal layer constitute the first main gate electrode 5 .

Step 8: Print a second printed electrode slurry on the side of the first dielectric layer 4 away from the second doped polysilicon layer 20, and sinter it to form a second printed sintered layer. The second printed electrode slurry burns through The first dielectric layer 4 extends into the second doped polysilicon layer 20 and is connected.

Step 9: Electroplating and depositing metal on the surface of the second printed and sintered layer to form a second metal layer. The second printed and sintered layer and the second metal layer constitute the second main gate electrode 11 .

Step 10: Provide a plurality of first openings and second openings penetrating the first dielectric layer 4 on the first dielectric layer 4, electroplating metal in the first openings, and electroplating metal in the second openings. Metal, the first fine gate electrode 7 and the second fine gate electrode 12 are formed through heat treatment, and each of the first fine gate electrodes 7 intersects and is electrically connected to each of the first main gate electrodes 5, and each of the first fine gate electrodes 7 intersects and is electrically connected to each of the first main gate electrodes 5. The second fine gate electrode 12 intersects and is electrically connected to each of the second main gate electrodes 11 .

Specifically, in step four, a plurality of first doped polysilicon units are arranged at equal intervals; a plurality of second doped polysilicon units are arranged at equal intervals.

Specifically, in step five, the first dielectric layer 4 is deposited on the surface of the first doped polysilicon unit and the surface of the second doped polysilicon unit, that is, the first dielectric layer 4 covers the first The surface of the doped polysilicon unit and the second doped polysilicon unit.

Specifically, in step six, the first printed electrode paste is printed on the surface of the first dielectric layer 4 corresponding to the first doped polysilicon layer 3 and sintered to form a first printed and sintered layer.

Specifically, in step eight, a second printed electrode paste is printed on the surface of the first dielectric layer 4 corresponding to the second doped polysilicon layer 20 and sintered to form a second printed and sintered layer.

In this application, the third method for preparing solar cells includes the following steps:

Step 1: Provide silicon substrate 1.

Step 2: Form a second dielectric layer 9 on one side surface (front surface or front surface) of the silicon substrate 1 .

Step 3: Provide a tunneling layer 2 on one side surface of the silicon substrate 1 .

Step 4: Deposit first doped polysilicon units and second doped polysilicon units at intervals on the side of the tunnel layer 2 facing away from the silicon substrate 1. A plurality of the first doped polysilicon units constitute the A first doped polysilicon layer 3, and a plurality of second doped polysilicon units constitute the second doped polysilicon layer 20.

Specifically, a plurality of first doped polysilicon units are arranged at equal intervals; a plurality of second doped polysilicon units are arranged at equal intervals.

Step 5: Deposit a first dielectric layer 4 on the side of the first doped polysilicon layer 3 and the second doped polysilicon layer 20 away from the tunnel layer 2 .

Specifically, the first dielectric layer 4 is deposited on the surface of the first doped polysilicon unit and the surface of the second doped polysilicon unit, that is, the first dielectric layer 4 covers the first doped polysilicon unit and the surface of the second doped polysilicon unit. The surface of the second doped polysilicon unit.

Step 6: Print the first printed electrode slurry on the side of the first dielectric layer 4 away from the first doped polysilicon layer 3, and sinter it to form a first printed sintered layer. The first printed electrode slurry burns through The first dielectric layer 4 extends into the first doped polysilicon layer 3 and forms crystalline first metal nanometers at the interface between the first doped polysilicon layer 3 and the first printing and sintering layer. Particle 6.

Specifically, the first printed electrode paste is printed on the surface of the first dielectric layer 4 corresponding to the first doped polysilicon layer 3 and sintered to form a first printed and fired layer.

Step 7: Electroplating and depositing metal on the surface of the first printing and sintering layer to form a first metal layer. The first printing and sintering layer and the first metal layer constitute the first main gate electrode 5 .

Step 8: Print a second printed electrode slurry on the side of the first dielectric layer 4 away from the second doped polysilicon layer 20, and sinter it to form a second printed sintered layer. The second printed electrode slurry burns through The first dielectric layer 4 extends into the second doped polysilicon layer 20 .

Specifically, in step eight, a second printed electrode paste is printed on the surface of the first dielectric layer 4 corresponding to the second doped polysilicon layer 20 and sintered to form a second printed and sintered layer.

Step 9: Electroplating and depositing metal on the surface of the second printed and sintered layer to form a second metal layer. The second printed and sintered layer and the second metal layer constitute the second main gate electrode 11 .

Step 10: Provide a plurality of first openings and second openings penetrating the first dielectric layer 4 on the first dielectric layer 4, electroplating metal in the first openings, and electroplating metal in the second openings. Metal, the first fine gate electrode 7 and the second fine gate electrode 12 are formed through heat treatment, and the first fine gate electrode 7 is connected to the first main gate electrode 5, and the second fine gate electrode 12 is connected to the first main gate electrode 5. The second main gate electrode 11 is connected.

In this embodiment, the tunneling layer 2 , the first doped polysilicon layer 3 , the first dielectric layer 4 , the first electrode and the crystalline first metal nanoparticles 6 can all refer to the aforementioned method for the first solar cell. Description of the preparation method, that is, the materials, structure, and preparation method of the tunneling layer 2 of the solar cell, the first doped polysilicon layer 3, the first dielectric layer 4, the first electrode, and the crystalline first metal nanoparticles 6 Reference may be made to the content described in the first solar cell and its preparation method.

Example

The experimental methods used in the following examples are all conventional methods unless there are special requirements.

The materials, reagents, etc. used in the following examples can all be obtained from commercial sources unless otherwise specified.

Example 1

The solar cell in this embodiment is the first solar cell and includes the following steps:

Step 1: Provide silicon substrate.

It is obtained by cleaning, alkali texturing and edge etching of the silicon wafer. After texturing, a pyramid texture is formed on the front surface (front surface) of the silicon wafer to obtain a p-type crystalline silicon layer.

Step 2: Form the doped layer

Boron diffusion on the front side of the silicon substrate forms a doped layer;

The boron diffusion can be: using a boron source to diffuse the silicon substrate under high temperature conditions, and through the boron diffusion, a doping layer is formed on the front side.

The boron source for boron diffusion may include boron tribromide, the diffusion temperature of the boron diffusion ranges from 950 to 1000°C, and the diffusion time ranges from 1.5 to 2.5 hours.

Step 3: Form the tunneling layer.

In step two, boron is diffused on the back surface (back surface) of the silicon substrate to form a back boron diffusion layer, and then the back boron diffusion layer is removed, and a thermal oxidation method is used to grow a tunneling layer on the back surface of the silicon substrate. layer, the tunneling layer is a silicon oxide layer with a thickness of 1 nm.

The backside boron diffusion layer is removed using wet etching equipment.

Specifically, wet etching equipment can be used to remove the backside boron diffusion layer on the backside through wet etching. The wet etching equipment can achieve single-side cleaning and etching, and the etching depth can be 1.5 to 3 microns.

Step 4: Form the first doped polysilicon layer

Use LPCVD to pass silane and phosphorane to deposit an in-situ phosphorus-doped amorphous silicon film on the side of the tunnel layer away from the silicon substrate, and then anneal the amorphous silicon film, where the annealing temperature is controlled at 800 to 1000 ℃, and the annealing time is controlled at 30 minutes, thereby crystallizing amorphous silicon into polysilicon and forming the first doped polysilicon layer. The thickness of the first doped polysilicon layer is 100 nm.

When forming the first doped polysilicon layer, an amorphous silicon film is formed on the doped layer. The amorphous silicon film is removed by using chain-type single-sided etching equipment and first using HF solution to remove the front amorphous silicon film. The oxide layer on the surface of the silicon film is removed by etching the amorphous silicon film around the front using KOH solution.

Step 5: Form the first dielectric layer.

A silicon nitride film is deposited on the side of the first doped polysilicon layer away from the tunnel layer using tubular PECVD to form a first dielectric layer. The thickness of the first dielectric layer is 50 nm.

Step 6: Form the first electrode

A first printed electrode paste is printed on the side of the first dielectric layer facing away from the first doped polysilicon layer. The first printed electrode paste burns through the first dielectric layer at a sintering temperature of 900°C. Connected to the first doped polysilicon layer, and forming crystalline first metal nanoparticles at the interface between the first doped polysilicon layer and the first printed sintering layer. An electrode metal is electroplated and deposited on the surface of the first printed and sintered layer to form a first metal layer, and the first printed and sintered layer and the first metal layer constitute the first main gate electrode.

A plurality of first openings penetrating the first dielectric layer are opened on the first dielectric layer, a first fine gate electrode metal is electroplated in the first openings, and the first fine gate electrode is formed by heat treatment at 250°C. , the first fine gate electrode is connected to the first doped polysilicon layer. The straight line where the first fine gate electrode is located is perpendicular to the straight line where the first main gate electrode is located, and each of the first fine gate electrodes intersects and is electrically connected to each of the first main gate electrodes, and the The first fine gate electrode and the first main gate electrode constitute a first electrode.

The first main gate electrode includes a plurality of first connection points, a plurality of first connection gate lines and a plurality of first auxiliary electrodes. The first connection points and the first connection gate lines are connected and extend in sequence, so The first auxiliary electrode is located at the connection between the first main gate electrode and the first fine gate electrode. One end of the first auxiliary electrode is connected to the first connection point or the first connection gate line, and the other end of the first auxiliary electrode is connected to the first connection point or the first connection gate line. One end is connected to the first thin grid line. The first auxiliary electrode is in an arc shape, and the width of the first auxiliary electrode tends to decrease in a direction away from the first connection point or the first connection grid line.

The first printed electrode paste is Ag paste.

The crystalline first metal nanoparticles include silver.

The first metal layer is formed of Ni.

The first fine gate electrode is Ni.

The height of the first main gate electrode is 10 microns. Width is 100 microns.

The height of the first fine gate electrode is 5 microns. Width is 10 microns.

Step 7: Form the second dielectric layer

A silicon nitride film is deposited on the surface of the side of the doped layer away from the tunnel layer using tube PECVD to form a second dielectric layer. The thickness of the second dielectric layer is 50 nm.

Step 8: Form anti-reflective layer

An anti-reflective layer is deposited on a side of the second dielectric layer facing away from the doped layer.

The anti-reflection layer is an aluminum oxide layer and a silicon nitride layer combined together. The thickness of the aluminum oxide layer is 10 nm and the thickness of the silicon nitride is 60 nm.

Step 9: Form the second electrode

A second printed electrode paste is printed on one side of the anti-reflective layer. At the sintering temperature of 900°C, the second printed electrode paste burns through the anti-reflective layer and the second dielectric layer. The doping layer is connected, and crystalline second metal nanoparticles are formed at the interface between the doping layer and the second printing and sintering layer. Metal is electroplated and deposited on the surface of the second printed and sintered layer to form a second metal layer, and the second printed and sintered layer and the second metal layer constitute the second main gate electrode.

A third opening penetrating the anti-reflective layer is formed on the anti-reflective layer, a plurality of second openings penetrating the second dielectric layer is formed on the second dielectric layer, and the second openings It is connected with the third opening. Electroplating is performed in the second opening and the third opening, and a second fine gate electrode is formed through heat treatment at 250° C., and the second fine gate electrode is connected to the doped layer. The straight line where the second fine gate electrode is located is perpendicular to the straight line where the second main gate electrode is located, and each of the second fine gate electrodes intersects and is electrically connected to each of the second main gate electrodes, and the The second fine gate electrode and the second main gate electrode constitute a second electrode.

The second printed electrode paste is Ag paste.

The crystalline second metal nanoparticles include silver.

The second metal layer is formed of Ni.

The second fine gate electrode is Ni.

The height of the second main gate electrode is 10 microns. Width is 100 microns.

The height of the second thin gate electrode is 5 microns. Width is 10-micron.

Example 2

The solar cell in this embodiment is the second type of solar cell and includes the following steps:

Step 1: Provide a silicon substrate (for specific processes, please refer to Embodiment 1)

Step 2: Form the second dielectric layer

The front surface of the silicon substrate is oxidized to form a silicon oxide layer on the front surface of the silicon substrate, that is, the silicon oxide layer is the second dielectric layer.

Step 3: Form a tunneling layer (for specific processes, please refer to Embodiment 1)

Step 4: Form the first doped polysilicon layer (for specific processes, please refer to Embodiment 1)

Step 5: Form the first dielectric layer

On the surface of the first doped polysilicon layer, a laser is used to ablate the first doped polysilicon layer and the tunneling layer at intervals to expose the silicon substrate, thereby forming a plurality of spaced first regions.

A first dielectric layer is deposited on the surface of the first doped polysilicon layer and the side of the first doped polysilicon layer, the side of the tunnel layer and the surface of the silicon substrate in the first region (for specific deposition processes, please refer to Embodiment 1) .

Step 6: Form the first electrode and the second electrode

A first printed electrode paste and a second printed electrode paste are printed at intervals on the side of the first dielectric layer away from the first doped polysilicon layer, and the first printed electrode paste is printed on the first The doped polysilicon layer corresponds to the area on the first dielectric layer, and the second printed electrode paste is printed on the area of the first dielectric layer corresponding to the first area. Then, through sintering at 800° C., a first printed and fired layer and a second printed and fired layer were formed. The first printed electrode paste burns through the first dielectric layer, extends into the first doped polysilicon layer, and is formed at the interface between the first doped polysilicon layer and the first printed sintering layer. Crystalline first metal nanoparticles, the second printed electrode paste burns through the first dielectric layer, extends into the silicon substrate, and is close to the junction of the second printed sintering layer in the silicon substrate Formation of eutectic layer and local back field.

Metal is electroplated and deposited on the surface of the first printing and sintering layer to form a first metal layer, and the first printing and sintering layer and the first metal layer constitute the first main gate electrode.

Metal is electroplated and deposited on the surface of the second printed and sintered layer to form a second metal layer, and the second printed and sintered layer and the second metal layer constitute the second main gate electrode.

A plurality of first openings and second openings penetrating the first dielectric layer are opened on the first dielectric layer, metal is electroplated in the first opening and the second opening respectively, and the first opening is formed by heat treatment at 250°C. a fine gate electrode and a second fine gate electrode, and each of the first fine gate electrodes intersects and is electrically connected to each of the first main gate electrodes; the first fine gate electrode and the first main gate electrode Constituting a first electrode, each second fine gate electrode intersects and is electrically connected to each second main gate electrode, and the second fine gate electrode and the second main gate electrode constitute a second electrode.

The first main gate electrode includes a plurality of first connection points and a plurality of first connection grid lines. Two adjacent first connection points are connected through the first connection grid lines, that is, the second connection point The first main gate electrodes are sequentially connected and extended with the second connection gate lines to form the first main gate electrodes; a plurality of the first main gate electrodes are arranged in parallel and at equal intervals.

The second main gate electrode includes a plurality of second connection points and a plurality of second connection grid lines. Two adjacent second connection points are connected by the second connection grid lines, that is, the second connection points The second connection gate lines are connected and extended in sequence to form the second main gate electrode; a plurality of the second main gate electrodes are arranged in parallel and at equal intervals.

The second fine gate electrodes and the first fine gate electrodes are alternately parallel to each other. The second main gate electrodes and the first main gate electrodes are alternately parallel to each other.

A plurality of first fine gate electrodes are arranged at equal intervals, and the first fine gate electrode includes a plurality of first fine gate lines spaced apart by the first main gate electrode and the second main gate electrode, and the first fine gate electrode One end of a thin gate line is connected to the first main gate electrode, and the other end is separated by the second main gate electrode. The first fine gate electrode vertically intersects the first main gate electrode.

A plurality of second fine gate electrodes are arranged at equal intervals, the second fine gate electrode includes a plurality of second fine gate lines spaced apart by the first main gate electrode and the second main gate electrode, and the second fine gate electrode One end of the two thin gate lines is connected to the second main gate electrode, and the other end is separated by the first main gate electrode. The second fine gate electrode vertically intersects the second main gate electrode.

The first printed electrode paste is Ag paste.

The crystalline first metal nanoparticles include silver.

The first metal layer is made of Cu.

The first fine gate electrode is Cu.

The height of the first main gate electrode is 30 microns. Width is 1000 microns.

The height of the first fine gate electrode is 15 microns. Width is 40 microns.

The second printed electrode paste is Ag paste.

The second metal layer is formed of Cu.

The second fine gate electrode is Cu.

The second main gate electrode has a height of 30 microns and a width of 1000 microns.

The second thin gate electrode has a height of 15 microns and a width of 40 microns.

Example 3

In this application, the third method for preparing solar cells includes the following steps:

Step 1: Provide a silicon substrate (for specific processes, please refer to Embodiment 1).

Step 2: Form the second dielectric layer

The front surface of the silicon substrate is oxidized to form a silicon oxide layer on the front surface of the silicon substrate, that is, the silicon oxide layer is the second dielectric layer.

Step 3: Provide a tunneling layer on one side surface of the silicon substrate (for specific processes, please refer to Embodiment 1).

Step 4: Form the first doped polysilicon layer and the second doped polysilicon layer

First doped polysilicon units and second doped polysilicon units are sequentially deposited on a side of the tunnel layer facing away from the silicon substrate.

A plurality of the first doped polysilicon units constitute the first doped polysilicon layer; a plurality of the second doped polysilicon units constitute the second doped polysilicon layer.

The width of the first doped polysilicon layer is 600 nm, and the width of the second doped polysilicon layer is 1200 nm.

The first doped polysilicon layer and the second doped polysilicon layer have the same height, which is 250 nm.

Step 5: Form the first dielectric layer (for specific processes, please refer to Embodiment 1)

A first dielectric layer is deposited on a side surface of the first doped polysilicon layer and the second doped polysilicon layer facing away from the tunnel layer. The first dielectric layer covers surfaces of the first doped polysilicon unit and the second doped polysilicon unit.

Step 6: Form the first electrode (for specific processes, please refer to Embodiment 1)

A first printed electrode slurry is printed on the side of the first dielectric layer away from the first doped polysilicon layer, and a first printed sintered layer is formed by sintering at 900°C. The first printed electrode slurry burns through all The first dielectric layer extends into the first doped polysilicon layer, and forms crystalline first metal nanoparticles at the interface between the first doped polysilicon layer and the first printing and sintering layer. Metal is electroplated and deposited on the surface of the first printing and sintering layer to form a first metal layer, and the first printing and sintering layer and the first metal layer constitute the first main gate electrode.

A plurality of first openings penetrating the first dielectric layer are provided on the first dielectric layer, the first openings correspond to the first doped polysilicon units, and first fine particles are electroplated in the first openings. The gate electrode slurry is heat treated at 300°C to form the first fine gate electrode. Each of the first fine gate electrodes intersects and is electrically connected to each of the first main gate electrodes.

The first printed electrode paste is Ag paste.

The crystalline first metal nanoparticles include silver.

The first metal layer is /Sn.

The first fine gate electrode is Sn.

The height of the first main gate electrode is 30 microns. Width is 1000 microns.

The height of the first fine gate electrode is 5 microns. Width is 10 microns.

Step 7: Form the second electrode

A second printed electrode slurry is printed on the side surface of the first dielectric layer facing away from the second doped polysilicon layer, and a second printed sintered layer is formed by sintering at 900°C. The second printed electrode slurry burns through The first dielectric layer is connected to the second doped polysilicon layer.

Metal is electroplated and deposited on the surface of the second printed and sintered layer to form a second metal layer, and the second printed and sintered layer and the second metal layer constitute the second main gate electrode.

A plurality of second openings penetrating the first dielectric layer are provided on the first dielectric layer. The second openings correspond to the second doped polysilicon units. A second fine layer is electroplated in the second openings. The gate electrode paste is heat treated at 300°C to form a second fine gate electrode. Each of the second fine gate electrodes intersects and is electrically connected to each of the second main gate electrodes.

The second printed electrode paste is Ag paste.

The second metal layer is made of Sn.

The second fine gate electrode is Sn.

The second main gate electrode has a height of 30 microns and a width of 100 microns.

The second thin gate electrode has a height of 15 microns and a width of 40 microns.

In this embodiment, the arrangement of the first electrode and the second electrode on the surface of the first dielectric layer may refer to Embodiment 2.

Although the embodiments of the present application have been described above, the present application is not limited to the above-mentioned specific embodiments and application fields. The above-mentioned specific embodiments are only illustrative and instructive, rather than restrictive. Under the inspiration of this description and without departing from the scope of protection of the claims of this application, those of ordinary skill in the art can also make many forms, which all belong to the scope of protection of this application.

Claims (22)

1. A solar cell, which is characterized by comprising a silicon substrate, a tunneling layer, a first doped polysilicon layer, a first dielectric layer and a first electrode;

the tunneling layer, the first doped polysilicon layer and the first dielectric layer are sequentially laminated on one side surface of the silicon substrate;

the first electrode comprises a first main gate electrode and a first thin gate electrode, and the first thin gate electrode is intersected with and electrically connected with the first main gate electrode;

the first main gate electrode burns through the first dielectric layer and stretches into the first doped polysilicon layer; a first metal nano particle with a crystalline state at the junction of the first doped polysilicon layer and the first main gate electrode;

a plurality of first openings penetrating through the first dielectric layer are formed in the first dielectric layer; the first thin gate electrode is electroplated on the first doped polysilicon layer exposed by the first opening.

2. The solar cell of claim 1, wherein the crystalline first metal nanoparticles comprise the same metal as the metal material in the first main gate electrode;

the crystalline first metal nano particles are discretely distributed in island shapes at the junction of the first doped polysilicon layer and the first main gate electrode.

3. The solar cell of claim 1, wherein the crystalline first metal nanoparticle comprises metallic silver.

4. The solar cell of claim 1, wherein the first main gate electrode comprises a first printed sintered layer and a first metal layer disposed in a stack,

the first printed sintering layer penetrates through the first dielectric layer and stretches into the first doped polycrystalline silicon layer, and crystalline first metal nano particles are arranged at the junction of the first doped polycrystalline silicon layer and the first printed sintering layer;

the first metal layer is arranged on the surface of one side of the first printing sintering layer, which is away from the first doped polysilicon layer.

5. The solar cell of claim 1, wherein the first main gate electrode further comprises a first auxiliary electrode located at an intersection of the first main gate electrode and the first thin gate electrode; the first auxiliary electrode gradually decreases in cross-sectional area in a direction perpendicular to the silicon substrate in a direction away from the first main gate electrode and toward the first thin gate electrode.

6. The solar cell of any one of claims 1-5, further comprising a second electrode of opposite polarity to the first electrode, the second electrode comprising a second main gate electrode and a second thin gate electrode intersecting and electrically connected to the second main gate electrode;

The second main gate electrode further comprises a second auxiliary electrode, and the second auxiliary electrode is positioned at the intersection of the second main gate electrode and the second fine gate electrode; the second auxiliary electrode gradually decreases in cross-sectional area in a direction perpendicular to the silicon substrate in a direction away from the second main gate electrode and toward the second thin gate electrode.

7. The solar cell according to claim 6, wherein a doped layer is formed on a surface of a side of the silicon substrate facing away from the tunneling layer, and a second dielectric layer is disposed on a surface of the doped layer;

the second main gate electrode burns through the second dielectric layer and stretches into the doping layer;

a second metal nanoparticle having a crystalline state at the junction of the doped layer and the second main gate electrode; or a eutectic layer and a local back field are arranged at the junction of the doped layer and the second main gate electrode.

8. The solar cell of claim 7, wherein the second main gate electrode comprises metallic aluminum or metallic silver;

when the second main gate electrode comprises metal aluminum, a eutectic layer and a local back field are arranged at the junction of the doped layer and the second main gate electrode;

When the second main gate electrode comprises metallic silver, second metal nano particles with crystalline state are arranged at the junction with the second main gate electrode in the doping layer; the crystalline second metal nano particles are discretely distributed at the junction of the doped layer and the second main gate electrode in an island shape.

9. The solar cell of claim 7 wherein the second main gate electrode comprises a second printed sintered layer and a second metal layer disposed in a stack,

the second printed sintering layer penetrates through the second medium layer and stretches into the doping layer, and the junction between the second printed sintering layer and the second printed sintering layer in the doping layer is provided with the crystalline second metal nano particles;

the second metal layer is arranged on the surface of one side of the second printing sintering layer, which is away from the doped layer.

10. The solar cell of any of claims 6, wherein the first electrode and the second electrode are on the same side of the silicon substrate.

11. The solar cell of claim 10, wherein the second thin-gate electrode and the first thin-gate electrode are alternately parallel to each other;

the second main gate electrode and the first main gate electrode are alternately parallel to each other.

12. The solar cell according to claim 10 or 11, wherein the tunneling layer comprises a plurality of tunneling cells arranged at intervals on the surface of the silicon substrate,

the area between adjacent tunneling units is a first area,

the first dielectric layer covers the surface of the first doped polysilicon layer and the side surface of the first doped polysilicon layer, the side surface of the tunneling unit and the surface of the silicon substrate in the first region.

13. The solar cell of claim 12, wherein the second main gate electrode is connected to the silicon substrate through a first dielectric layer in the first region.

14. The solar cell of claim 10 or 11, wherein the first doped polysilicon layer comprises a plurality of first doped polysilicon units disposed at intervals on a surface of the tunneling layer;

the area between the adjacent first doped polysilicon units is a second area;

a second doped polysilicon unit is arranged in the second region, and a plurality of second doped polysilicon units form a second doped polysilicon layer;

the first dielectric layer covers the surfaces of the first doped polysilicon unit and the second doped polysilicon unit;

The second main gate electrode penetrates through the first dielectric layer and is connected with the second doped polysilicon layer.

15. A method of manufacturing a solar cell, comprising the steps of:

providing a silicon substrate;

providing a tunneling layer on one side surface of the silicon substrate;

depositing a first doped polysilicon layer on a side of the tunneling layer facing away from the silicon substrate;

depositing a first dielectric layer on one side of the first doped polysilicon layer away from the tunneling layer;

printing a first printing electrode slurry on one side of the first medium layer, which is away from the first doped polysilicon layer, and sintering the first printing electrode slurry to enable the first printing electrode slurry to burn through the first medium layer to form a first printing sintering layer connected with the first doped polysilicon layer, and forming crystalline first metal nano particles at the junction of the first doped polysilicon layer and the first printing sintering layer;

a plurality of first openings penetrating through the first dielectric layer are formed in the first dielectric layer;

electroplating and depositing metal on the surface of the first printed sintering layer to form a first metal layer, wherein the first printed sintering layer and the first metal layer form the first main gate electrode;

A metal is electrodeposited on a silicon substrate having a first opening.

16. The method of claim 15, further comprising heat treating the deposited metal; the sintering temperature is 750-900 ℃, and the heat treatment temperature is 250-500 ℃.

17. The method of claim 15 or 16, wherein a second dielectric layer is deposited on a surface of the silicon substrate on a side facing away from the tunneling layer;

ablating the first doped polysilicon layer and the tunneling layer at intervals on the surface of the first doped polysilicon layer to expose the silicon substrate, thereby forming a first region;

the first dielectric layer is deposited on the surface of the first doped polysilicon layer and the side surface of the first doped polysilicon layer, the side surface of the tunneling unit and the surface of the silicon substrate in the first region.

18. The method of claim 17, wherein a second printed electrode paste is printed on a surface of the first dielectric layer in the first region, a second printed sintered layer is formed by the sintering, the second printed electrode paste is sintered through the second dielectric layer to connect with a doped layer, and crystalline second metal nanoparticles or eutectic layers and a local back field are formed at a junction of the doped layer near the second printed sintered layer;

Electroplating and depositing metal on the surface of the second printing sintering layer to form a second metal layer;

the second printed sintered layer and the second metal layer form a second main gate electrode.

19. The method of claim 18, wherein a plurality of second openings are provided through the first dielectric layer on the first dielectric layer, a metal is deposited by electroplating in the second openings, a second thin gate electrode is formed by the heat treatment, and the second thin gate electrode is connected to the silicon substrate;

the second thin gate electrode intersects and is electrically connected with the second main gate electrode to form a second electrode.

20. The method of claim 15 or 16, wherein first and second doped polysilicon units are sequentially deposited at intervals on the surface of the tunneling layer,

a plurality of the first doped polysilicon units form the first doped polysilicon layer;

a plurality of the second doped polysilicon units form the second doped polysilicon layer;

the first dielectric layer is deposited on the surface of the first doped polysilicon unit and the surface of the second doped polysilicon unit.

21. The method of claim 20, wherein a second printed electrode paste is printed on a surface of the first dielectric layer corresponding to the second doped polysilicon layer and sintered to form a second printed sintered layer, the second printed electrode paste being sintered through the first dielectric layer and connected to the second doped polysilicon layer;

Electroplating and depositing metal on the surface of the second printing sintering layer to form a second metal layer;

the second printed sintered layer and the second metal layer form a second main gate electrode.

22. The method of claim 21, wherein a plurality of second openings are provided through the first dielectric layer on the first dielectric layer, metal is plated in the second openings, a second thin gate electrode is formed by the heat treatment, and the second thin gate electrode is connected to the second doped polysilicon layer;

the second thin gate electrode intersects and is electrically connected with the second main gate electrode to form a second electrode.